 jsowash
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24bfaa3b76
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Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
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2019-07-05 15:55:03 -07:00 |
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jsowash
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ad9193ad5a
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Verified 1rw mask writing and changed verilog.py accordingly.
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2019-07-05 15:08:59 -07:00 |
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jsowash
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f29631695c
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Finished merge
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2019-07-05 11:43:31 -07:00 |
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jsowash
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150259e2ba
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Added write_size to control_logic_r parameters.
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2019-07-05 11:40:02 -07:00 |
|
 mrg
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bfe4213fce
|
Port address added to entire SRAM.
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2019-07-05 09:44:42 -07:00 |
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mrg
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4c6556f1bc
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Add port address module
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2019-07-05 09:04:48 -07:00 |
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mrg
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c0f9cdbc12
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Create port address module
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2019-07-05 09:03:52 -07:00 |
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|
mrg
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dd62269e0b
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Some cleanup
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2019-07-05 08:18:58 -07:00 |
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jsowash
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02a0cd71ac
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fixed merge conflict
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2019-07-04 11:14:32 -07:00 |
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jsowash
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125112b562
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Added wmask flip flop. Need work on placement still.
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2019-07-04 10:34:14 -07:00 |
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mrg
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3176ae9d50
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Fix pnand2 height in bank select. Unsure how it passed before.
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2019-07-03 15:12:22 -07:00 |
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|
Matt Guthaus
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f914ab0ece
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Re-enable replica tests
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2019-07-03 14:57:47 -07:00 |
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mrg
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9204f85bb0
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Merge branch 'rbl_revamp' of github.com:VLSIDA/PrivateRAM into rbl_revamp
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2019-07-03 14:54:10 -07:00 |
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mrg
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ae9dbe203d
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Add freepdk45 dummy cells
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2019-07-03 14:53:44 -07:00 |
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|
Matt Guthaus
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0cb86b8ba2
|
Exclude new precharge in graph build
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2019-07-03 14:46:20 -07:00 |
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mrg
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0fbfa924f7
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Add other SCMOS dummy cells
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2019-07-03 14:28:12 -07:00 |
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mrg
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8b0b2e2817
|
Merge branch 'dev' into rbl_revamp
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2019-07-03 14:05:28 -07:00 |
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mrg
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70c83f20b6
|
Fixes to pass unit tests.
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
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2019-07-03 13:37:56 -07:00 |
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mrg
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bc4a3ee2b7
|
New port_data module works in SCMOS
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2019-07-03 13:17:12 -07:00 |
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jsowash
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474ac67af5
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Added optional write_size and wmask.
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2019-07-03 10:14:15 -07:00 |
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mrg
|
244604fb0d
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Data port module working by itself.
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2019-07-02 15:35:53 -07:00 |
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|
mrg
|
2abe859df1
|
Fix shared bank offset.
|
2019-07-01 16:29:59 -07:00 |
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|
jsowash
|
67c6cdf3bb
|
Fixed error where word_size was compared to num_words and added write_size to control_logic.py
|
2019-07-01 15:51:40 -07:00 |
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|
jsowash
|
242771f710
|
Merge branch 'dev' into add_wmask
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2019-06-28 15:44:27 -07:00 |
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|
jsowash
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1f76afd294
|
Begin wmask functionality. Added wmask to verilog file and config parameters.
|
2019-06-28 15:43:09 -07:00 |
|
 Hunter Nichols
|
3f5b60856a
|
Fixed key error with analytical delay of write ports.
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2019-06-28 13:49:04 -07:00 |
|
|
Hunter Nichols
|
ce7e320505
|
Undid change to add bitcell as input to array mod.
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2019-06-25 18:26:13 -07:00 |
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|
Hunter Nichols
|
4e08e2da87
|
Merged and fixed conflicts with dev
|
2019-06-25 16:55:50 -07:00 |
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|
Hunter Nichols
|
4f3340e973
|
Cleaned up graph additions to characterizer.
|
2019-06-25 16:37:35 -07:00 |
|
|
Hunter Nichols
|
33c17ac41c
|
Moved manual delay chain declarations from tech files to options.
|
2019-06-25 15:45:02 -07:00 |
|
|
Hunter Nichols
|
04ce3d5f45
|
Split control logic into different tests to avoid factory errors.
|
2019-06-25 14:55:28 -07:00 |
|
|
jsowash
|
3bd69d2759
|
Added functionality to express polygons in LEF files.
|
2019-06-25 09:20:00 -07:00 |
|
|
Matt
|
d22d7de195
|
Reapply jsowash update without spice model file
|
2019-06-24 08:59:58 -07:00 |
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|
mrg
|
4523a7b9f6
|
Replica bitcell array working
|
2019-06-19 16:03:21 -07:00 |
|
|
Hunter Nichols
|
2b07db33c8
|
Added bitcell as input to array, but there are DRC errors now.
|
2019-06-17 15:31:16 -07:00 |
|
|
mrg
|
5c4df2410e
|
Fix dummy row LVS issue
|
2019-06-14 15:06:04 -07:00 |
|
|
mrg
|
d35f180609
|
Add dummy row
|
2019-06-14 15:05:14 -07:00 |
|
|
mrg
|
3c3456596a
|
Add replica row with dummy cells.
|
2019-06-14 14:38:55 -07:00 |
|
|
mrg
|
b67f06a65a
|
Add replica column for inclusion in replica bitcell array
|
2019-06-14 12:15:16 -07:00 |
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|
mrg
|
d8baa5384d
|
Remove useless comments. Add missing copyright.
|
2019-06-14 10:13:13 -07:00 |
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|
Matt Guthaus
|
6e044b776f
|
Merge branch 'pep8_cleanup' into dev
|
2019-06-14 08:47:10 -07:00 |
|
|
Matt Guthaus
|
a234b0af88
|
Fix space before comment
|
2019-06-14 08:43:41 -07:00 |
|
|
mrg
|
8418aea95a
|
Revert height to width
|
2019-06-03 15:36:14 -07:00 |
|
|
mrg
|
58f51b72f1
|
Merge fixes
|
2019-06-03 15:31:49 -07:00 |
|
|
mrg
|
7b8c2cac30
|
Starting single layer power router.
|
2019-06-03 15:28:55 -07:00 |
|
|
mrg
|
bd4d965e37
|
Begin single layer supply router
|
2019-06-03 15:27:37 -07:00 |
|
|
mrg
|
4612c9c182
|
Move power pins before no route option
|
2019-06-03 15:27:37 -07:00 |
|
|
mrg
|
fc12ea24e9
|
Add boundary to every module and pgate for visual debug.
|
2019-06-03 15:27:37 -07:00 |
|
|
mrg
|
1268a7927b
|
Pbitcell updates.
Fix module offset error.
Add boundary for debugging.
Line wrap code.
|
2019-06-03 15:27:37 -07:00 |
|
|
mrg
|
17d42d43b4
|
Add boundary layer
|
2019-06-03 15:27:37 -07:00 |
|