luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,981 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3981 Commits

Author SHA1 Message Date
mrg 7195d81736 Adjust WL and GND for contacted via2 spacing. 2022-04-19 10:32:37 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 68d0a56423 Fix WL to gnd spacing for grounded wordlines. 2022-04-04 16:02:47 -07:00
mrg 111533f0b0 Move power pins to horizontal or vertical layer in all cells. 2022-03-31 16:36:19 -07:00
mrg 83e5848728 Change FreePDK and SCMOS 2rw cell to share gnd power rail. 2022-03-30 13:48:53 -07:00
mrg 23b5655cab Split replica_bitcell_array test 2022-03-23 15:59:29 -07:00
mrg 9f7426052d Split port_address tests 2022-03-23 14:46:41 -07:00
mrg e31bec131c Remove 1rw1r combined test and add separate tests. 2022-03-22 11:59:04 -07:00
mrg a8f50f212e Change track spacing for freepdk45 2022-03-18 16:01:57 -07:00
mrg 2bfc94fcdd Add unblocking of source and destination pins to router. 2022-03-18 14:44:13 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 8979612cca Rework macro Makefile to take technology target 2022-03-14 10:14:31 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg b981ad5814 Erase duplicate macro configs 2022-03-11 10:17:24 -08:00
mrg c2589fbb39 Change docker to use debug klayout 2022-03-10 11:48:53 -08:00
mrg 4567c2ebcd Add space after docker command. Regress to klayout v0.27.4 2022-03-10 08:37:48 -08:00
mrg b75856fac9 Merge branch 'dev' into sky130_fixes 2022-03-09 11:31:42 -08:00
mrg e16defdae4 Add a sleep to see if problem is async one 2022-03-09 10:24:50 -08:00
mrg b841e18abd Remove breakpoint 2022-03-07 16:59:55 -08:00
mrg 08c2e21724 Fix tab spacing in Makefile 2022-03-07 16:13:37 -08:00
mrg 2796800898 Fix bug with incorrect pitch while adding channel route trunks. 2022-03-07 16:12:20 -08:00
mrg 772fbd6f96 Remove extra well tap to save area. 2022-03-07 15:38:25 -08:00
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00
mrg f17d661e3a Add spare column option to tests for sky130 2022-03-07 07:58:41 -08:00
mrg ce2b125762 Clean up git action flow 2022-03-07 07:58:26 -08:00
mrg 134d7cde7a Add FREEPDK45 to paths 2022-03-07 07:58:00 -08:00
Jesse Cirimelli-Low 038acd1568 single port rba lvs progress 2022-03-07 01:20:59 -08:00
mrg 4faf97005f Add even columns for sky130 to ring test 2022-03-06 12:21:09 -08:00
mrg 67b51ff7f5 Move vdd pin in freepdk45 sense amp from dout 2022-03-06 12:20:54 -08:00
mrg 5263532a95 Remove setpaths csh version as it is not maintained 2022-03-06 11:57:40 -08:00
mrg 6eeb81b9fe Skip sky130 23_lib tests and 4096 row hierarchical decoder test 2022-03-06 11:27:13 -08:00
mrg ff31990831 Add parallel build for dockerfile 2022-03-06 11:26:57 -08:00
mrg a0f1327f5e Add odd rows to 23_lib tests 2022-03-06 11:26:18 -08:00
mrg 6da3e44b6f Split up 06_hierarchical_decoder test 2022-03-06 11:26:03 -08:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg 10bec414e8 Update usage instructions 2022-03-04 14:21:58 -08:00
mrg e139b4aa81 Swap A and B pins in wordline driver. 2022-03-03 09:53:24 -08:00
mrg 0533920777 Revert to old magic until substrate bug is fixed. 2022-03-03 09:49:20 -08:00
mrg ff471740ed Build docker from config instead of pulling it 2022-03-03 09:01:12 -08:00
mrg febf7031b1 Fix wrong power layer for min area constraint 2022-03-02 17:04:54 -08:00
mrg 7654cd7295 Allow supply pins on m4 too 2022-03-02 16:47:17 -08:00
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg 4fac069c3c Skip hspice tests in docker 2022-03-01 14:44:04 -08:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg 36bbf81624 Upgrade to magic 8.3.274 2022-03-01 14:37:30 -08:00
mrg 0908aa9e25 Add route vertical pins 2022-03-01 14:37:09 -08:00