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OpenRAM
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2983 Commits

Author SHA1 Message Date
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg e0024fa79a Add verbosity to error output 2021-04-07 16:07:56 -07:00
mrg bd28a7a93b Merge branch 'sky130_fixes' into dev 2021-04-01 16:48:22 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 7e29dd7ff2 Reduce verbosity of routing info 2021-03-31 09:38:06 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg e144f03b23 Add status for supply routing. 2021-03-24 11:15:59 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg fb953c19e8 Remove option that causes errors and is unused. 2021-03-01 16:36:27 -08:00
mrg 13bdae2e30 Merge remote-tracking branch 'private/dev' into control-logic-pull 2021-03-01 15:47:33 -08:00
mrg 049d3ffcaf Remove extra test file 2021-03-01 15:25:39 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg f31125645e Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-03-01 14:06:51 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg ae8926c5c2 Merge remote-tracking branch 'private/dev' into dev 2021-03-01 12:12:44 -08:00
mrg 5ab67214e5 Make sure to add path when source and target 2021-03-01 11:37:42 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 f6afef8d4a rbl_bl_delay_bar to rbl_bl_delay for write enable 2021-02-27 19:30:37 -05:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
ota2 9a2987ad07 Add spectre simulator 2021-02-27 19:25:00 -05:00
ota2 48bc47c686 Set pin label size to use zoom factor from tech specifications 2021-02-27 18:30:57 -05:00
mrg 0c2ed487d9 Redundant check if pin contains another 2021-02-26 11:16:19 -08:00
mrg 9f0ab0d081 Route perimeter signals before power grid 2021-02-26 11:14:39 -08:00
mrg 2a9b5db6d4 Rewrite enclose grids to be cleaner 2021-02-26 11:14:08 -08:00
mrg 013836bb3d PEP8 cleanup 2021-02-23 13:33:14 -08:00
mrg 549112fcf8 PEP8 cleanup 2021-02-23 13:32:13 -08:00
mrg 1c6de4591d Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
Hunter Nichols c308dd34a4 Merge branch 'dev' into elmore_model_tuning 2021-02-15 14:50:56 -08:00
mrg 33bc9a597c Remove dashes for Python module name warning. 2021-02-15 08:19:08 -08:00
mrg 506daaec99 Merge remote-tracking branch 'private/dev' into dev 2021-02-13 23:52:18 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
mrg b82b7aaf28 PEP8 format 2021-02-10 12:10:04 -08:00
mrg c78d3a9cca Merge branch 'dev' into runner_test 2021-02-10 11:17:35 -08:00
mrg 29c3d46be6 Warn about threads forced to 1 2021-02-10 10:23:06 -08:00
Bob Vanhoof d14a68847e added cell label checker and cell labels to the freepdk technology 2021-02-09 13:09:26 +01:00
Bob Vanhoof 3dfc039f6f add technology option passtrough in test 30 2021-02-09 09:32:35 +01:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
mrg e043aaffb3 Don't print DRC/LVS/PEX run stats in regress.py 2021-02-03 15:17:28 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Hunter Nichols 7bed5bdd1c Added option for model to specify regression model data path. 2021-01-25 14:24:54 -08:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus eebc2a93b6 Remove redundant pins when adding each pin 2021-01-25 09:36:27 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
Hunter Nichols e26e17c53f Added option to specify exact corners for characterization in config file 2021-01-22 00:50:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
Hunter Nichols d1b240dfb5 Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. 2021-01-21 13:52:55 -08:00
Hunter Nichols 31ad1963f6 Removed nominal pvt corners from golden lib files. 2021-01-21 12:47:18 -08:00
mrg b3e249c722 Merge remote-tracking branch 'private/dev' into dev 2021-01-20 12:36:04 -08:00
Hunter Nichols b0c2722583 Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. 2021-01-19 15:22:50 -08:00
Hunter Nichols 70fe90f0af Added shared classes between regression models, added and changed some debug messages 2021-01-19 14:19:50 -08:00
Hunter Nichols 6d2a35e929 Changed most lists to dict to reduce hardcoded indices 2021-01-19 13:47:54 -08:00
mrg 608e4b81f1 Merge remote-tracking branch 'private/dev' 2021-01-15 16:11:23 -08:00
mrg 3048c61c20 Merge branch 'supply_router' into dev 2021-01-15 14:28:08 -08:00
mrg e8239c5e77 Remove debug print statement 2021-01-15 14:27:54 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 683f4214b2 Differentiate pin and other blockages for easier to understand blockage processing. 2021-01-14 15:58:37 -08:00
Hunter Nichols 7259c197d8 Merge branch 'dev' into automated_analytical_model 2021-01-13 14:18:18 -08:00
Hunter Nichols 1881d43948 Added initial neural network model 2021-01-13 14:07:52 -08:00
mrg e3a888e0f7 Only unblock blockages not grids 2021-01-13 13:57:49 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 3ef56a29ea Bug fix 2021-01-13 13:56:22 -08:00
Hunter Nichols ed3d39a1b8 Added updated model data with slews and loads. Changed linear regressions to account for additional models. 2021-01-13 13:04:34 -08:00
mrg 1b31afd773 Use partial grids for enclosure with note 2021-01-13 13:01:55 -08:00
mrg bc9ab086e5 Clean up imports 2021-01-13 13:01:33 -08:00
mrg 78966824db Second iteration try unblocking partial blocked grids. 2021-01-13 12:37:29 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 408ea15228 Ordering bug fixed in Magic. 2021-01-12 16:20:26 -08:00
mrg 6f5b7c0264 Flatten bug fixed in Magic so don't flatten routes. 2021-01-12 16:20:03 -08:00
mrg 3d7bed0641 Fix typo in comment 2021-01-12 11:22:11 -08:00
Hunter Nichols a802d2a0bd Merge branch 'dev' into automated_analytical_model 2021-01-11 15:33:28 -08:00
Hunter Nichols d6d8a037f1 Added values to datasheet info which will be used for model training 2021-01-11 15:20:56 -08:00
mrg 2101d89646 Merge branch 'dev' into supply_router 2021-01-11 13:52:59 -08:00
mrg 1c6d4eedd1 Add new empty debug function. 2021-01-11 13:52:41 -08:00
Hunter Nichols 6b053c8185 Adjusted margin for the period in elmore model 2021-01-11 12:53:14 -08:00
mrg 7506ba81be Refactor how blocked_grids work. Must still calculate blockages based on enclosed pins. 2021-01-11 11:12:45 -08:00
mrg 504f9aa892 Space tx in pinv_dec for power routing. 2021-01-08 11:34:58 -08:00
mrg f428ff4bfd v1.1.14 2021-01-07 10:33:21 -08:00
mrg 1a1b5a49b2 Merge remote-tracking branch 'private/dev' into dev 2021-01-07 10:32:50 -08:00
mrg c0df3ff1da Merge remote-tracking branch 'private/dev' 2021-01-07 10:20:17 -08:00
mrg 0faa14c0e3 Sort escape pins by distance to perimeter to reduce blockages. 2021-01-07 10:12:02 -08:00
Hunter Nichols d8437249f7 Condensed some datasheet code in lib.py 2021-01-06 15:53:22 -08:00
mrg 66ff1fe990 Only unblock source/target instead of all components for cleaner routes 2021-01-06 15:14:56 -08:00
Hunter Nichols bb841fc84d Added option to output the datasheet.info file. 2021-01-06 12:45:34 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg 9a6ca328f6 Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
mrg be79789097 Return empty string instead of None when no grid type 2021-01-06 09:41:13 -08:00
mrg 72dc1c58da Initialize queue only in init_queue function 2021-01-06 09:40:49 -08:00
mrg ec6f0f1873 Escape route to any side 2021-01-06 09:40:32 -08:00