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OpenRAM
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4,336 Commits 4 Branches 63 Tags 78 MiB
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4336 Commits

Author SHA1 Message Date
Bugra Onal 219b29a833 Fake SRAM and Xyce RAW file option 2022-08-10 12:22:47 -07:00
samuelkcrow 8872a3e312 add tests 2022-08-10 12:22:47 -07:00
samuelkcrow 8d1d3c0e90 disable lvs/drc in char and func scripts 2022-08-10 12:22:47 -07:00
samuelkcrow e621890f78 force netlist only mode in memchar memfunc, rename char and func scripts, add description for func script 2022-08-10 12:22:47 -07:00
samuelkcrow 3e528a3e75 log sim result after func_sim 2022-08-10 12:22:47 -07:00
samuelkcrow 9e29391992 clarify file location message for user 2022-08-10 12:17:14 -07:00
mrg 2adab1ea1a Initial work on separate delay and func simulation 2022-08-10 12:14:47 -07:00
samuelkcrow ebe4393d66 reorder sram __init__() argument order for tests that rely on the order 2022-08-10 12:07:09 -07:00
samuelkcrow 34ee709c69 call create() function from sram/__init__ 2022-08-10 12:07:07 -07:00
samuelkcrow 2bbd293bf2 clarify file location message for user 2022-08-10 12:06:18 -07:00
samuelkcrow 8793dda40a characterizer and functional simulator working from command line 2022-08-10 12:06:18 -07:00
samuelkcrow e2a52ec0f3 Adding characterizer executable 2022-08-10 12:06:18 -07:00
mrg 28128157c0 Initial work on separate delay and func simulation 2022-08-10 12:06:14 -07:00
Bugra Onal 48fce6485d write_size None initialization fixed 2022-08-04 16:37:21 -07:00
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
samuelkcrow caba726cfe add pdks and test results to gitignore 2022-08-02 13:44:56 -07:00
mrg 6f696e312e Revert to old ngspice repo. Other is outdated. 2022-08-02 10:25:23 -07:00
mrg 4b96b539e2 Dockerfile updates 
Remove conditional bash commands and make one per line.
Change ngspice repo to github.
Fix typo in ngspice commit.
Reduce number of cores in klayout compile.
 2022-08-02 10:25:23 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
Bugra Onal fdba1f4d7b Merge after rebase and fixes 2022-07-28 17:14:53 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00