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17992 Commits

Author SHA1 Message Date
AdvaySingh1 5ce8aada27 Added profiling for literal count 2026-02-13 16:34:15 -08:00
AdvaySingh1 3442bc3a85 Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing 2026-02-13 16:15:31 -08:00
AdvaySingh1 80fbdf7e6a Removed duplication of vectors and called clockgate pass post creating enable signals 2026-02-13 15:33:45 -08:00
AdvaySingh1 56502440b3 Added hashing for already seen paths. ODO: add profiling to see if this is effective 2026-02-13 15:32:54 -08:00
AdvaySingh1 fca02c94df Notes for TODOS 2026-02-12 17:04:50 -08:00
AdvaySingh1 feffbbe32c Added initial impl based on OpenROAD 2026-02-12 16:12:50 -08:00
AdvaySingh1 d7277fcb3a Added explanation for safe-gating vs exact-gating 2026-02-12 15:20:39 -08:00
AdvaySingh1 0396bf48d1 Added notes.txt 2026-02-12 14:28:37 -08:00
AdvaySingh1 e4734e6ca9 Added comments explaining the MUX network repair Idea to see if there's a combinational circuit out of the input values which can serve as the enable signal 2026-02-12 12:49:15 -08:00
AdvaySingh1 514c01efd2 Added prune expressions list TODO 2026-02-12 12:14:25 -08:00
AdvaySingh1 745f17a34e Changed input_set_is_enable_exact to XOR Mitter 2026-02-12 11:10:10 -08:00
AdvaySingh1 481e49954d Added notes for a fixed input_set_is_enable implementation 2026-02-11 17:05:13 -08:00
AdvaySingh1 532d1d45a8 Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob 2026-02-11 15:08:49 -08:00
AdvaySingh1 4ca4392e9b Simplied recursion in sat_clockgate pass 2026-02-11 14:56:46 -08:00
AdvaySingh1 19060eeee7 Added TODO for how to add the COI set 2026-02-11 14:40:32 -08:00
AdvaySingh1 143a860673 Added future TODOs 2026-02-11 14:39:47 -08:00
AdvaySingh1 da8febc3b7 Added to notes.txt 2026-02-11 14:22:26 -08:00
AdvaySingh1 d2300b2a9f Added nodes for the MITER 2026-02-11 14:19:29 -08:00
AdvaySingh1 dd3f2e370c Fixed naming for bfs_find_potential_enable_inputs 2026-02-11 12:31:13 -08:00
AdvaySingh1 5b384511f2 Added initial SatClockgateWorker 2026-02-11 11:02:15 -08:00
AdvaySingh1 9e544aa95c Added pseudocode for create_ce_logic 2026-02-11 11:01:49 -08:00
AdvaySingh1 b4cd82bacf Added initial printing of the clocks with dump_flipflops_to_file 2026-02-11 10:56:07 -08:00
AdvaySingh1 5aeb19fb66 Added initial version 1 pseudocode 2026-02-11 10:55:43 -08:00
AdvaySingh1 e4f69cba30 Initialized notes 2026-02-11 09:53:03 -08:00
AdvaySingh1 6ad01fa850 Added initial pass structure 2026-02-10 14:33:37 -08:00
AdvaySingh1 b53acb0ff0 Added pass in Makefile.inc 2026-02-10 14:33:17 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00
Akash Levy f8a095e404
Merge pull request #105 from Silimate/negopt-fixes 
fixed edge cases in negopt passes, fixed cell naming inconsistencies
 2026-02-08 23:37:04 -08:00
Akash Levy ee46f498e1
Update negopt.cc 2026-02-07 17:54:16 -08:00
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
Akash Levy dc1847f89a
Merge pull request #104 from Silimate/mux_push_implementation 
mux_push implementation
 2026-02-05 17:55:51 -08:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
Akash Levy 5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Akash Levy f74ac17a5f Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
Akash Levy 09fd53aaae Update abc 2026-02-04 17:01:27 -08:00
github-actions[bot] 0640a5904b Bump version 2026-02-05 00:33:25 +00:00
Akash Levy d3ab45c2fa
Merge branch 'YosysHQ:main' into main 2026-02-04 15:53:43 -08:00
Akash Levy dbeeb7a7cf
Merge pull request #98 from Silimate/nr_cleanup 
Nr cleanup
 2026-02-04 15:49:01 -08:00
AdvaySingh1 8d22f6d7e1 Merged with main 2026-02-04 13:00:22 -08:00
AdvaySingh1 607ef02339 Added abc_max_node_retention_origins flag in AbcConfig struct 2026-02-04 12:12:04 -08:00
AdvaySingh1 16b5a8e350 ABC: added -M flag for nMaxOrigins 2026-02-04 12:02:31 -08:00
AdvaySingh1 43027720d2 Fixed no sources log error to only output error if node_retention mode is on 2026-02-04 10:22:24 -08:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 2aa0e1d009
Merge pull request #5629 from rocallahan/remove-zero-wires 
Avoid scanning entire module in `Module::remove()` if there are no wires to remove
 2026-02-04 17:44:24 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Akash Levy 48e7b5a167 Let's go back to a simpler time for abc... 2026-02-04 04:33:19 -08:00
Akash Levy c57c49873e Please just stop modifying yosys... 2026-02-04 03:48:58 -08:00
Akash Levy ea6b968618
Merge pull request #102 from Silimate/merge2 
Merge2
 2026-02-04 02:54:00 -08:00
Akash Levy 241852eebd Test merge from upstream 2026-02-04 02:07:01 -08:00