mirror of https://github.com/YosysHQ/yosys.git
Added hashing for already seen paths. ODO: add profiling to see if this is effective
This commit is contained in:
parent
fca02c94df
commit
56502440b3
|
|
@ -101,11 +101,16 @@ struct SatGen
|
|||
else
|
||||
vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
|
||||
} else {
|
||||
std::string wire_name = RTLIL::unescape_id(bit.wire->name);
|
||||
std::string name = pf +
|
||||
(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset));
|
||||
vec.push_back(ez->frozen_literal(name));
|
||||
imported_signals[pf][bit] = vec.back();
|
||||
// Check cache first to avoid creating duplicate literals
|
||||
if (imported_signals[pf].count(bit)) {
|
||||
vec.push_back(imported_signals[pf].at(bit));
|
||||
} else {
|
||||
std::string wire_name = RTLIL::unescape_id(bit.wire->name);
|
||||
std::string name = pf +
|
||||
(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset));
|
||||
vec.push_back(ez->frozen_literal(name));
|
||||
imported_signals[pf][bit] = vec.back();
|
||||
}
|
||||
}
|
||||
return vec;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue