nella
57ab8ef2c6
Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2
2026-09-22 16:49:41 +02:00
nella
d4f0028e7f
Merge pull request #6178 from YosysHQ/nella/muladd-reassoc
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canonicalize $macc unmapping for better DSP inference [sc-814]
2026-09-22 13:04:16 +00:00
nella
5c338c559a
Reassociate sums of products via $macc.
2026-09-16 14:26:07 +02:00
nella
a651db986a
xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
nella
77bca709d4
Declare synth_fabulous pad cells as blackboxes.
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iopadmap inserted $__FABULOUS_* cells with no module, so their port
directions were unknown to later passes. Read with -icells so the module
names match the cell types.
2026-09-14 13:50:09 +02:00
Emil J. Tywoniak
0b384527c4
prep: also sequence checks better
2026-09-02 15:13:39 +02:00
Emil J. Tywoniak
5d393b8207
synth*: run check after proc before opt_clean to discover process-initial driver conflicts
2026-09-02 14:44:36 +02:00
Lofty
030e13569c
synth_gatemate: remove classic ABC mapping for LUTs
2026-08-20 09:33:47 +01:00
Lofty
4cb0a5e2f2
synth: remove classic ABC mapping for LUTs
2026-08-19 11:43:00 +01:00
Lofty
1f72d02f39
synth_microchip: remove classic ABC mapping
2026-08-19 11:43:00 +01:00
Lofty
ee75cd3ea0
synth_lattice: remove classic ABC mapping
2026-08-19 11:43:00 +01:00
Lofty
dd4b6689e8
synth_intel: remove classic ABC mapping
2026-08-19 11:43:00 +01:00
Lofty
3a148d7633
synth_gowin: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
737560c471
synth_fabulous: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
5fe16f60f9
synth_efinix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
6df15312cc
synth_anlogic: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
873bed6300
synth_achronix: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
63fbb31921
synth_sf2: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
8a01ff15f4
synth_quicklogic: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
6824ee065a
synth_nanoxplore: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
c053706540
synth_analogdevices: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
086cd8e685
synth_xilinx: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
44bab117d7
synth_ice40: remove classic ABC mapping
2026-08-19 11:42:59 +01:00
Lofty
fc6433bbae
Merge pull request #6132 from YosysHQ/lofty/abc-refactor-12
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synth_greenpak4, nlutmap: remove
2026-08-19 10:19:14 +00:00
Lofty
edb411a622
synth_greenpak4, nlutmap: remove
2026-08-19 10:56:16 +01:00
Lofty
541d240930
synth_coolrunner2: remove
2026-08-18 10:04:45 +01:00
nick
bd90d0e83a
cmp2lut techmap fix
2026-08-14 10:17:30 -06:00
nella
7f5b7aacb9
Count module output ports as consumers.
2026-08-12 10:00:30 +02:00
nella
f93651e6ba
Latches always err add missing.
2026-08-10 15:56:02 +02:00
nella
8b50a13181
Add global latch policy.
2026-08-10 15:56:02 +02:00
nella
fcffeba238
Extend latch policy.
2026-08-10 15:56:02 +02:00
nella
431d5f5e33
check make always_latch exempt.
2026-08-10 15:56:02 +02:00
Catherine
1277640bdf
CMake: add missing dependency edges for synth_* passes.
2026-08-06 14:48:56 +00:00
nella
511017acc1
Merge branch 'main' into nella/fuse-2
2026-07-24 12:20:35 +02:00
nella
526ab7aab3
Use Nexus DSP pipelined registers.
2026-07-24 12:10:07 +02:00
Lofty
f0b5225134
flowmap: remove
2026-07-22 13:50:33 +01:00
drewbabel
3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers
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run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.
Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
2026-07-20 23:59:40 -07:00
myrtle
a0fbe6e133
Merge pull request #6054 from YosysHQ/gatecat/nexus-radiant-fix
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nexus: Fix Radiant netlist compatibility
2026-07-19 13:22:46 +00:00
gatecat
15c54ae15e
nexus: Fix Radiant netlist compatibility
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Signed-off-by: gatecat <[email protected]
2026-07-19 12:44:40 +02:00
Johan Olby
63457de80e
mul2dsp: normalize operand order
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Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
2026-07-15 16:21:07 +02:00
nella
388ed215c4
Remove old techmap.
2026-07-08 12:07:58 +02:00
nella
fe1ce9e5c1
Fix merge.
2026-07-08 11:54:55 +02:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle
2026-07-08 11:41:08 +02:00
nella
362e828dc2
Simplify check -latchonly calls in synth.
2026-07-07 10:10:00 +02:00
Leo Moser
b06c57b2bf
fabulous: remove unused -blif option
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Signed-off-by: Leo Moser <[email protected]
2026-07-01 13:38:45 +02:00
Leo Moser
655cb40d0f
fabulous: add --cells-map option
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Signed-off-by: Leo Moser <[email protected]
2026-06-30 16:09:51 +02:00
Leo Moser
4fac567673
fabulous: add -arith-map option
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Signed-off-by: Leo Moser <[email protected]
2026-06-30 16:09:51 +02:00
Leo Moser
d50999ea45
fabulous: format using clang
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Signed-off-by: Leo Moser <[email protected]
2026-06-30 16:09:51 +02:00
Leo Moser
2535504217
fabulous: update CMakeLists.txt
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Signed-off-by: Leo Moser <[email protected]
2026-06-30 16:09:51 +02:00
Leo Moser
aa84f4a13b
fabulous: remove legacy arith_map.v mapping
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Signed-off-by: Leo Moser <[email protected]
2026-06-30 16:09:51 +02:00
nella
nella
Emil J. Tywoniak
Lofty
Lofty
nick
Catherine
drewbabel
myrtle
Johan Olby
Leo Moser