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Latches always err add missing.

This commit is contained in:
nella 2026-08-10 15:02:43 +02:00 committed by nella
parent 8b50a13181
commit f93651e6ba
6 changed files with 4 additions and 46 deletions
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1
techlibs/analogdevices/CMakeLists.txt
View File

@ -58,7 +58,6 @@ yosys_pass(synth_analogdevices
arith_map.v
ff_map.v
latches_map.v
lut_map.v
mux_map.v
dsp_map.v

11
techlibs/analogdevices/latches_map.v
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@ -1,11 +0,0 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

13
techlibs/analogdevices/synth_analogdevices.cc
View File

@ -22,7 +22,6 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -109,8 +108,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log("\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
@ -118,7 +115,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
}
std::string top_opt, edif_file, json_file, tech, tech_param;
SynthLatchesConfig latches;
bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp;
bool abc9, dff;
bool flatten_before_abc;
@ -131,7 +127,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
edif_file.clear();
tech = "t16ffc";
tech_param = " -D IS_T16FFC";
latches = SynthLatchesConfig();
flatten = true;
retime = false;
noiopad = false;
@ -249,8 +244,6 @@ struct SynthAnalogDevicesPass : public ScriptPass
json_file = args[++argidx];
continue;
}
if (latches.parse(args, argidx))
continue;
break;
}
extra_args(args, argidx, design);
@ -283,7 +276,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
}
if (check_label("prepare")) {
run(stringf("proc -latches %s", latches.str()));
run("proc -latches error");
if (flatten || help_mode) {
run("check");
run("flatten", "(with '-flatten')");
@ -446,9 +439,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
}
if (check_label("map_ffs")) {
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/analogdevices/latches_map.v");
run("check -latchonly -assert");
run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r");
if (abc9 || help_mode) {
if (dff || help_mode)

1
techlibs/intel_alm/CMakeLists.txt
View File

@ -41,7 +41,6 @@ yosys_pass(synth_intel_alm
common/arith_alm_map.v
common/dff_map.v
common/dff_sim.v
common/latches_map.v
common/dsp_sim.v
common/dsp_map.v
common/mem_sim.v

11
techlibs/intel_alm/common/latches_map.v
View File

@ -1,11 +0,0 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

13
techlibs/intel_alm/synth_intel_alm.cc
View File

@ -22,7 +22,6 @@
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -73,15 +72,12 @@ struct SynthIntelALMPass : public ScriptPass {
log(" -noclkbuf\n");
log(" do not insert global clock buffers\n");
log("\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, family_opt, bram_type;
SynthLatchesConfig latches;
bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
void clear_flags() override
@ -89,7 +85,6 @@ struct SynthIntelALMPass : public ScriptPass {
top_opt = "-auto-top";
family_opt = "cyclonev";
bram_type = "m10k";
latches = SynthLatchesConfig();
flatten = true;
nolutram = false;
nobram = false;
@ -150,8 +145,6 @@ struct SynthIntelALMPass : public ScriptPass {
noclkbuf = true;
continue;
}
if (latches.parse(args, argidx))
continue;
break;
}
extra_args(args, argidx, design);
@ -190,7 +183,7 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("coarse")) {
run(stringf("proc -latches %s", latches.str()));
run("proc -latches error");
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
@ -248,10 +241,8 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_ffs")) {
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("check -latchonly -assert");
run("techmap");
run("techmap -map +/intel_alm/common/latches_map.v");
run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0");
run("techmap -map +/intel_alm/common/dff_map.v");
run("opt -full -undriven -mux_undef");