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Add global latch policy.

This commit is contained in:
nella 2026-08-10 10:53:58 +02:00 committed by nella
parent fcffeba238
commit 8b50a13181
15 changed files with 162 additions and 140 deletions
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1
passes/proc/CMakeLists.txt
View File

@ -23,6 +23,7 @@ yosys_pass(proc_mux
)
yosys_pass(proc_dlatch
proc_dlatch.cc
proc_dlatch.h
)
yosys_pass(proc_dff
proc_dff.cc

19
passes/proc/proc_dlatch.cc
View File

@ -22,6 +22,7 @@
#include "kernel/ffinit.h"
#include "kernel/consteval.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
#include <sstream>
#include <stdlib.h>
#include <stdio.h>
@ -416,12 +417,6 @@ struct proc_dlatch_db_t
}
};
enum LatchPolicy {
POLICY_INFO,
POLICY_WARN,
POLICY_ERROR
};
void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
{
RTLIL::SigSig latches_bits, nolatches_bits;
@ -556,10 +551,10 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
else if (proc->get_bool_attribute(ID::always_latch))
log("Latch inferred for signal `%s.%s' from always_latch process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else if (policy == POLICY_ERROR)
else if (policy == LatchPolicy::Error)
log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else if (policy == POLICY_WARN)
else if (policy == LatchPolicy::Warn)
log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else
@ -610,13 +605,7 @@ struct ProcDlatchPass : public Pass {
policy_str = design->scratchpad_get_string("proc.latches", "warn");
LatchPolicy policy;
if (policy_str == "info")
policy = POLICY_INFO;
else if (policy_str == "warn")
policy = POLICY_WARN;
else if (policy_str == "error")
policy = POLICY_ERROR;
else
if (!latch_policy_from_string(policy_str, policy))
log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", policy_str.c_str());
for (auto mod : design->all_selected_modules()) {

67
passes/proc/proc_dlatch.h Normal file
View File

@ -0,0 +1,67 @@
#ifndef PROC_DLATCH_H
#define PROC_DLATCH_H
#include "kernel/yosys_common.h"
#include "kernel/log.h"
YOSYS_NAMESPACE_BEGIN
enum class LatchPolicy {
Info,
Warn,
Error
};
inline bool latch_policy_from_string(const std::string &str, LatchPolicy &policy)
{
if (str == "info")
policy = LatchPolicy::Info;
else if (str == "warn")
policy = LatchPolicy::Warn;
else if (str == "error")
policy = LatchPolicy::Error;
else
return false;
return true;
}
inline const char *latch_policy_str(LatchPolicy policy)
{
switch (policy) {
case LatchPolicy::Info: return "info";
case LatchPolicy::Warn: return "warn";
default: return "error";
}
}
// shared -latches option handling for synth_* passes
struct SynthLatchesConfig {
LatchPolicy policy = LatchPolicy::Error;
bool parse(const std::vector<std::string> &args, size_t &idx)
{
if (args[idx] == "-latches" && idx+1 < args.size()) {
if (!latch_policy_from_string(args[++idx], policy))
log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", args[idx].c_str());
return true;
}
return false;
}
const char *str() const { return latch_policy_str(policy); }
static const char *help()
{
return
" -latches <info|warn|error>\n"
" select the behaviour for latches that cannot be mapped to a\n"
" dedicated hardware primitive and are implemented using LUTs\n"
" instead. 'error' (the default) aborts synthesis, 'warn' only\n"
" prints a warning, and 'info' permits them with an info-level message.\n"
" Latches explicitly requested with 'always_latch' are always permitted.\n";
}
};
YOSYS_NAMESPACE_END
#endif

1
techlibs/analogdevices/CMakeLists.txt
View File

@ -58,6 +58,7 @@ yosys_pass(synth_analogdevices
arith_map.v
ff_map.v
latches_map.v
lut_map.v
mux_map.v
dsp_map.v

11
techlibs/analogdevices/latches_map.v Normal file
View File

@ -0,0 +1,11 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

25
techlibs/analogdevices/synth_analogdevices.cc
View File

@ -22,6 +22,7 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -108,12 +109,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -121,7 +117,8 @@ struct SynthAnalogDevicesPass : public ScriptPass
log("\n");
}
std::string top_opt, edif_file, json_file, tech, tech_param, latches;
std::string top_opt, edif_file, json_file, tech, tech_param;
SynthLatchesConfig latches;
bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp;
bool abc9, dff;
bool flatten_before_abc;
@ -134,7 +131,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
edif_file.clear();
tech = "t16ffc";
tech_param = " -D IS_T16FFC";
latches = "error";
latches = SynthLatchesConfig();
flatten = true;
retime = false;
noiopad = false;
@ -252,17 +249,12 @@ struct SynthAnalogDevicesPass : public ScriptPass
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (!(tech == "t16ffc" || tech == "t40lp"))
log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech);
@ -291,7 +283,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
}
if (check_label("prepare")) {
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
if (flatten || help_mode) {
run("check");
run("flatten", "(with '-flatten')");
@ -454,8 +446,9 @@ struct SynthAnalogDevicesPass : public ScriptPass
}
if (check_label("map_ffs")) {
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/analogdevices/latches_map.v");
run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r");
if (abc9 || help_mode) {
if (dff || help_mode)

23
techlibs/efinix/synth_efinix.cc
View File

@ -22,6 +22,7 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -63,12 +64,7 @@ struct SynthEfinixPass : public ScriptPass
log(" -nobram\n");
log(" do not use EFX_RAM_5K cells in output netlist\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -76,7 +72,8 @@ struct SynthEfinixPass : public ScriptPass
log("\n");
}
string top_opt, edif_file, json_file, latches;
string top_opt, edif_file, json_file;
SynthLatchesConfig latches;
bool flatten, retime, nobram;
void clear_flags() override
@ -87,7 +84,7 @@ struct SynthEfinixPass : public ScriptPass
flatten = true;
retime = false;
nobram = false;
latches = "error";
latches = SynthLatchesConfig();
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -130,18 +127,14 @@ struct SynthEfinixPass : public ScriptPass
nobram = true;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_EFINIX pass.\n");
log_push();
@ -161,7 +154,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
run("check");
run("flatten");
run("tribuf -logic");
@ -204,7 +197,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_ffs"))
{
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef");

23
techlibs/fabulous/synth_fabulous.cc
View File

@ -21,6 +21,7 @@
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -110,12 +111,7 @@ struct SynthPass : public ScriptPass {
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -123,7 +119,8 @@ struct SynthPass : public ScriptPass {
log("\n");
}
string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map, latches;
string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map;
SynthLatchesConfig latches;
std::vector<string> extra_plib, extra_map, extra_mlibmap;
std::vector<std::pair<string, string>> extra_ffs;
@ -142,7 +139,7 @@ struct SynthPass : public ScriptPass {
carry_mode = "none";
flatten = true;
json_file = "";
latches = "error";
latches = SynthLatchesConfig();
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -252,18 +249,14 @@ struct SynthPass : public ScriptPass {
flatten = false;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_FABULOUS pass.\n");
log_push();
@ -290,7 +283,7 @@ struct SynthPass : public ScriptPass {
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module));
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
}
if (check_label("flatten", "(unless -noflatten)")) {
@ -399,7 +392,7 @@ struct SynthPass : public ScriptPass {
dff_str += stringf(" -cell %s %s", cell, init);
run(dff_str);
}
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("opt_merge");
}

23
techlibs/ice40/synth_ice40.cc
View File

@ -21,6 +21,7 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -114,12 +115,7 @@ struct SynthIce40Pass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -127,7 +123,8 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
}
string top_opt, blif_file, edif_file, json_file, device_opt, latches;
string top_opt, blif_file, edif_file, json_file, device_opt;
SynthLatchesConfig latches;
bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, no_rw_check;
int min_ce_use;
@ -151,7 +148,7 @@ struct SynthIce40Pass : public ScriptPass
abc9 = true;
device_opt = "hx";
no_rw_check = false;
latches = "error";
latches = SynthLatchesConfig();
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -258,10 +255,8 @@ struct SynthIce40Pass : public ScriptPass
no_rw_check = true;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
@ -270,8 +265,6 @@ struct SynthIce40Pass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n");
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n");
@ -305,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
}
if (check_label("flatten", "(unless -noflatten)"))
@ -408,7 +401,7 @@ struct SynthIce40Pass : public ScriptPass
run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)");
}
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/ice40/latches_map.v");
if (noabc || help_mode) {

1
techlibs/intel_alm/CMakeLists.txt
View File

@ -41,6 +41,7 @@ yosys_pass(synth_intel_alm
common/arith_alm_map.v
common/dff_map.v
common/dff_sim.v
common/latches_map.v
common/dsp_sim.v
common/dsp_map.v
common/mem_sim.v

11
techlibs/intel_alm/common/latches_map.v Normal file
View File

@ -0,0 +1,11 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

25
techlibs/intel_alm/synth_intel_alm.cc
View File

@ -22,6 +22,7 @@
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -72,19 +73,15 @@ struct SynthIntelALMPass : public ScriptPass {
log(" -noclkbuf\n");
log(" do not insert global clock buffers\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, family_opt, bram_type, latches;
string top_opt, family_opt, bram_type;
SynthLatchesConfig latches;
bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf;
void clear_flags() override
@ -92,7 +89,7 @@ struct SynthIntelALMPass : public ScriptPass {
top_opt = "-auto-top";
family_opt = "cyclonev";
bram_type = "m10k";
latches = "error";
latches = SynthLatchesConfig();
flatten = true;
nolutram = false;
nobram = false;
@ -153,17 +150,12 @@ struct SynthIntelALMPass : public ScriptPass {
noclkbuf = true;
continue;
}
if (args[argidx] == "-latches" && argidx + 1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
@ -198,7 +190,7 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("coarse")) {
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
@ -256,9 +248,10 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_ffs")) {
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap");
run("techmap -map +/intel_alm/common/latches_map.v");
run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0");
run("techmap -map +/intel_alm/common/dff_map.v");
run("opt -full -undriven -mux_undef");

24
techlibs/lattice/synth_lattice.cc
View File

@ -22,6 +22,7 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -156,12 +157,7 @@ struct SynthLatticePass : public ScriptPass
log(" implement constant comparisons in soft logic, do not involve\n");
log(" hard carry chains\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log(" (ignored with -asyncprld, which has a latch primitive)\n");
log("\n");
log("\n");
@ -170,7 +166,8 @@ struct SynthLatticePass : public ScriptPass
log("\n");
}
string top_opt, edif_file, json_file, family, latches;
string top_opt, edif_file, json_file, family;
SynthLatchesConfig latches;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
bool cmp2softlogic;
string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc;
@ -197,7 +194,7 @@ struct SynthLatticePass : public ScriptPass
iopad = false;
nodsp = false;
no_rw_check = false;
latches = "error";
latches = SynthLatchesConfig();
postfix = "";
arith_map = "";
brams_map = "";
@ -327,10 +324,8 @@ struct SynthLatticePass : public ScriptPass
cmp2softlogic = true;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
@ -338,9 +333,6 @@ struct SynthLatticePass : public ScriptPass
if (family.empty())
log_cmd_error("Lattice family parameter must be set.\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family == "ecp5") {
postfix = "_ecp5";
arith_map = "_ccu2c";
@ -417,7 +409,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + (asyncprld ? std::string("info") : latches));
run(stringf("proc -latches %s", asyncprld ? "info" : latches.str()));
if (flatten || help_mode) {
run("check");
run("flatten");
@ -548,7 +540,7 @@ struct SynthLatticePass : public ScriptPass
if (abc2 || help_mode)
run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) {
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}

24
techlibs/nanoxplore/synth_nanoxplore.cc
View File

@ -22,6 +22,7 @@
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -97,12 +98,7 @@ struct SynthNanoXplorePass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -110,7 +106,8 @@ struct SynthNanoXplorePass : public ScriptPass
log("\n");
}
string top_opt, json_file, family, latches;
string top_opt, json_file, family;
SynthLatchesConfig latches;
bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check;
std::string postfix;
int min_ce_use, min_srst_use;
@ -131,7 +128,7 @@ struct SynthNanoXplorePass : public ScriptPass
postfix = "";
min_ce_use = 8;
min_srst_use = 8;
latches = "error";
latches = SynthLatchesConfig();
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -210,17 +207,12 @@ struct SynthNanoXplorePass : public ScriptPass
no_rw_check = true;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family.empty()) {
//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
family = "ultra";
@ -264,7 +256,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse"))
{
run("proc -latches " + latches);
run(stringf("proc -latches %s", latches.str()));
if (flatten || help_mode) {
run("check");
run("flatten", "(skip if -noflatten)");
@ -340,7 +332,7 @@ struct SynthNanoXplorePass : public ScriptPass
dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge");
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v");

24
techlibs/quicklogic/synth_quicklogic.cc
View File

@ -21,6 +21,7 @@
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "passes/proc/proc_dlatch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -72,12 +73,7 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" use old ABC flow, which has generally worse mapping results but is less\n");
log(" likely to have bugs.\n");
log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" Latches explicitly requested with 'always_latch' are always permitted.\n");
log("%s", SynthLatchesConfig::help());
log(" (only applies to the pp3 family)\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
@ -85,7 +81,8 @@ struct SynthQuickLogicPass : public ScriptPass {
log("\n");
}
string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path, latches;
string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path;
SynthLatchesConfig latches;
bool abc9, inferAdder, nobram, bramTypes, dsp, ioff, flatten;
void clear_flags() override
@ -104,7 +101,7 @@ struct SynthQuickLogicPass : public ScriptPass {
dsp = true;
ioff = true;
flatten = true;
latches = "error";
latches = SynthLatchesConfig();
}
void set_scratchpad_defaults(RTLIL::Design *design) {
@ -177,10 +174,8 @@ struct SynthQuickLogicPass : public ScriptPass {
flatten = false;
continue;
}
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
if (latches.parse(args, argidx))
continue;
}
break;
}
extra_args(args, argidx, design);
@ -191,9 +186,6 @@ struct SynthQuickLogicPass : public ScriptPass {
if (family != "pp3" && family != "qlf_k6n10f")
log_cmd_error("Invalid family specified: '%s'\n", family);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
@ -227,7 +219,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("prepare")) {
run("proc -latches " + (family == "pp3" ? latches : std::string("info")));
run(stringf("proc -latches %s", family == "pp3" ? latches.str() : "info"));
if (flatten) {
run("check");
run("flatten", "(unless -noflatten)");
@ -331,7 +323,7 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (latches == "error" || help_mode)
if (latches.policy == LatchPolicy::Error || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) {