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18050 Commits

Author SHA1 Message Date
Akash Levy 0b0c19b271 fix: use SSH_PRIVATE_KEY secret for private submodule access 
Use the same SSH key approach as source-vendor.yml for cloning
private submodules (abc, verific).

Made-with: Cursor
 2026-02-28 12:09:28 -08:00
Akash Levy 708637f65a fix: use PAT for private submodule access (abc, verific) 
Deploy keys are repo-scoped and can't access multiple private repos.
Use a PAT (SUBMODULE_PAT) that has access to all required repos.

Made-with: Cursor
 2026-02-28 12:07:03 -08:00
Akash Levy 44beeb5213 fix: use SSH deploy key for private verific submodule checkout 
Made-with: Cursor
 2026-02-28 12:05:26 -08:00
Akash Levy 2c1d160930 fix: trigger release workflow on main branch, not master 
Made-with: Cursor
 2026-02-28 12:03:52 -08:00
Akash Levy fc4ff6ecd2 Add release workflow 2026-02-27 15:01:06 -08:00
Akash Levy 18c3a0b907 Remove old linefile loops stuff 2026-02-27 14:53:44 -08:00
Akash Levy 0c663bef4a
Merge pull request #110 from Silimate/negopt_log_flush 
Added log flushes after each negopt pass for clearer logging
 2026-02-26 16:09:34 -08:00
tondapusili 2f276d0723 Added log flushes after each negopt pass for clearer logging 2026-02-25 12:15:46 -08:00
Akash Levy 0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr 
Added is_clock_gated attr to flops created via clockgate.cc pass
 2026-02-20 17:02:02 -08:00
Akash Levy c47dd20140
Merge pull request #108 from Silimate/icg_builtin_sim 
Added built in  cell alongside sim support for cell
 2026-02-20 17:01:20 -08:00
AdvaySingh1 8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
AdvaySingh1 b29514fafc Added built in cell alongside sim support for cell 2026-02-19 11:48:35 -08:00
Akash Levy 723ddd74cf Improve wreduce runtime 2026-02-19 01:03:26 -08:00
Akash Levy bf4ce9d6f7 Import uniquify fix 2026-02-19 00:24:32 -08:00
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Akash Levy 9a30512cff
Merge pull request #107 from Silimate/clkgate_node_retention 
Added node retention
 2026-02-18 18:17:27 -08:00
AdvaySingh1 5769cdbea8 Added node retention 2026-02-18 16:05:56 -08:00
Akash Levy b7098e8383
Merge branch 'YosysHQ:main' into main 2026-02-18 09:44:25 -08:00
Gus Smith 29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Emil J 33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
Akash Levy 650c636d39 Fixups 2026-02-18 01:12:35 -08:00
Akash Levy 33c2c88fa4 Bump Yosys to latest from upstream 2026-02-17 23:41:39 -08:00
Akash Levy c04975b78c Remove custom mux opt_exprs 2026-02-17 20:41:29 -08:00
Akash Levy 5debd619e5 Add workaround for Liberty duplication 2026-02-13 06:51:42 -08:00
Miodrag Milanović ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Akash Levy 0485576632 Revert rtlil changes 2026-02-13 04:14:14 -08:00
Akash Levy 2b247d165b Merge from main 2026-02-13 04:14:08 -08:00
Akash Levy b8d83c1d5b Fix cell naming issues 2026-02-13 01:05:51 -08:00
Akash Levy e81b5b810d Lack of node retention should only be a warning 2026-02-13 01:04:59 -08:00
github-actions[bot] e2f0c4d9a0 Bump version 2026-02-13 00:35:27 +00:00
Miodrag Milanovic bb7aa7d208 Cleanup of yml files 2026-02-12 14:56:45 +01:00
Miodrag Milanović e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic e5b3e9fc1f This one should run only vanilla-tests 2026-02-12 14:08:49 +01:00
Miodrag Milanovic c6e48f4bea These are tests from other Makefile 2026-02-12 14:06:08 +01:00
Miodrag Milanovic cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Maxim Kudinov 5b94a97fb3 gowin: synth_gowin: Add -nodsp option 2026-02-12 13:58:47 +03:00
Maxim Kudinov 542b29fa6a gowin: synth_gowin: Merge flatten label with coarse 2026-02-12 13:58:47 +03:00
Maxim Kudinov 5ea073d45e gowin: format MULT instances 2026-02-12 13:35:49 +03:00
Miodrag Milanović 9b9e7b5ae3
Merge pull request #3389 from uwsampl/support-parameter-default-values-in-json-frontend-and-verilog-backend 
Support parameter default values in JSON frontend and Verilog backend
 2026-02-12 10:17:56 +01:00
Miodrag Milanović ce5321da8c
Merge pull request #5682 from YosysHQ/update_abc 
Update ABC as per 2026-02-11
 2026-02-12 08:05:23 +01:00
github-actions[bot] 1319112913 Bump version 2026-02-12 00:32:36 +00:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Emil J b890b1b43f
Merge pull request #5678 from YosysHQ/emil/remove-dockerfile 
Dockerfile: remove
 2026-02-11 17:32:21 +01:00
Miodrag Milanovic a13b5c4211 Update ABC as per 2026-02-11 2026-02-11 17:30:08 +01:00
Gus Smith be9c857e72 Fix ABC after merge 2026-02-11 08:12:38 -08:00
Gus Smith b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith 1ede98797f Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 9ad7aed4a5 Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 12ace45b89 Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00