Fix cell naming issues

kernel/ffmerge.cc

@@ -156,8 +156,8 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
 	return found;
 }
 
-bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
-	ff = FfData(module, initvals, NEW_ID);
+bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits, RTLIL::IdString name) {
+	ff = FfData(module, initvals, name);
 	sigmap->apply(sig);
 
 	bool found = false;

kernel/ffmerge.h

@@ -110,7 +110,7 @@ struct FfMergeHelper
 	// a constant-input FF bit (with matching initial value and reset value).
 	// However, this will not work if the input is all-constant — if the caller
 	// cares about this case, it needs to check for it explicitely.
-	bool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);
+	bool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits, RTLIL::IdString name);
 
 	// To be called on find_output_ff result that will be merged.  This
 	// marks the given FF bits as used up (and not to be considered for

kernel/rtlil.cc

@@ -3489,7 +3489,7 @@ DEF_METHOD(Shiftx,      sig_a.size(), ID($shiftx))
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
 		Module *module = this; \
-		RTLIL::SigSpec sig_y = addWire(!_pmux ? NEW_ID : NEW_ID4_SUFFIX("y"), sig_a.size());     \
+		RTLIL::SigSpec sig_y = addWire(NEW_ID4_SUFFIX("y"), sig_a.size());     \
 		add ## _func(name, sig_a, sig_b, sig_s, sig_y, src);      \
 		return sig_y;                                             \
 	} // SILIMATE: Improve the naming (NOT IMPROVED FOR MUX!)
@@ -3579,7 +3579,7 @@ DEF_METHOD(Bweqx,    ID($bweqx))
 	} \
 	RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
 		Module *module = this; \
-		RTLIL::SigBit sig4 = addWire(_mux ? NEW_ID : NEW_ID4_SUFFIX(#_P4));             \
+		RTLIL::SigBit sig4 = addWire(NEW_ID4_SUFFIX(#_P4));             \
 		add ## _func(name, sig1, sig2, sig3, sig4, src);  \
 		return sig4;                                      \
 	} // SILIMATE: Improve the naming (NOT IMPROVED AT ALL!)

passes/memory/memory_dff.cc

@@ -558,7 +558,7 @@ struct MemoryDffWorker
 
 		FfData ff;
 		pool<std::pair<Cell *, int>> bits;
-		if (!merger.find_input_ff(port.addr, ff, bits)) {
+		if (!merger.find_input_ff(port.addr, ff, bits, mem.memid)) {
 			log("no address FF found.\n");
 			return;
 		}