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1647 Commits

Author SHA1 Message Date
Miodrag Milanović 2fd290ad47
Merge pull request #6134 from SimonEbner/main 
Retry read operations interrupted by EINTR
 2026-08-20 16:24:26 +00:00
Lofty be69f88e55
Merge pull request #6135 from YosysHQ/lofty/abc-refactor-13 
abc: remove -sop
 2026-08-20 09:34:26 +00:00
nella 59a3826bbd
Merge pull request #6130 from DanielMBouyou/arith-tree-narrow-link 
arith_tree: do not flatten a chain link narrower than its consumer
 2026-08-20 08:40:25 +00:00
Lofty caceaaa2bb abc: remove -sop 2026-08-19 12:52:10 +01:00
Simon Bucher b98d7b6853 Gracefully handle EINTR during read. 
EINTR should be retried.
 2026-08-19 10:46:41 +00:00
Lofty edb411a622 synth_greenpak4, nlutmap: remove 2026-08-19 10:56:16 +01:00
Daniel M Bouyou e5c56c6400 arith_tree: do not flatten a chain link narrower than its consumer 
sole_chainable_consumer folded a cell into its consumer without ever
comparing widths. A link truncates its result at its own Y width, and that
truncation is invisible only when the consumer truncates at least as hard,
since (x % 2**link) % 2**parent == x % 2**parent holds only when
parent <= link. When the consumer is wider, the carry the link discards
becomes observable, and flattening the chain silently recovers it.

For

  module top(input [7:0] a, b, c, output [8:0] o);
    wire [7:0] t = a + b;
    assign o = t + c;
  endmodule

synth -arith_tree computes a + b + c where the design specifies
((a + b) % 256) + c. The two differ by 256 whenever a + b overflows,
for example at a=169 b=135 c=7.

alumacc already guards the structurally identical $macc merge using
macc_may_overflow(); arith_tree carried no equivalent check.

Add two cases to tests/arith_tree/arith_tree_equiv.ys: equiv_double_neg
widened to a 5 bit result, and a dedicated equiv_narrow_intermediate.
 2026-08-18 12:06:48 +02:00
nella 38b6e5e76c fix WASI, harden scl cache locking. 
Co-authored-by: Mike Inouye <mikeinouye@google.com>
 2026-08-18 11:31:57 +02:00
Mike Inouye 977e55315d fix macOS build 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2026-08-17 22:05:09 +00:00
Mike Inouye 7c3becfbcd add file lock on liberty scl cache 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2026-08-17 21:18:34 +00:00
Lofty 621d943ac8
Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10 
read_xaiger2: remove
 2026-08-17 17:42:25 +00:00
nella 027677d43b Move scl cache args to libcache, fix -disable. 2026-08-17 12:37:49 +02:00
nella 5efa8187ad Add control over scl cache. 2026-08-17 10:49:45 +02:00
Emin b564fa2e71 liberty_cache: key SCL cache on ABC executable mtime and size 
The SCL format is written/read by ABC and can change between ABC builds,
so a cache entry created with a different ABC binary must not be reused.
 2026-08-15 23:16:31 +04:00
nella b8959e70ba
Merge pull request #6072 from YosysHQ/nella/dlatchlibmap-cleanup 
Update to `dfflibmap` to be able to map LATCHes (clean up of #5976)
 2026-08-13 08:38:19 +00:00
Lofty 1dce7895e0 read_xaiger2: remove 2026-08-11 08:56:55 +01:00
Lofty fd6367405e
Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8 
abc_ops_reintegrate: xaiger2 compatibility
 2026-08-10 13:14:40 +00:00
nella a03e5ec2ca Style fixups. 2026-08-10 10:59:03 +02:00
nella e75e42c5d7 Pick first cell of smallest area. 
Co-authored-by: Iztok Jeras <iztok.jeras@gmail.com>
 2026-08-10 10:59:03 +02:00
nella 011c3fc8c3 Add latch mapping. 
Co-authored-by: Iztok Jeras <iztok.jeras@gmail.com>
 2026-08-10 10:59:03 +02:00
nella c590157cd3 Deduplicate FF cell finders. 
Co-authored-by: Iztok Jeras <iztok.jeras@gmail.com>
 2026-08-10 10:59:03 +02:00
Catherine 1277640bdf CMake: add missing dependency edges for `synth_*` passes. 2026-08-06 14:48:56 +00:00
Lofty 5e6fcf3b36 cleanup 2026-08-03 13:28:33 +01:00
Emil J. Tywoniak 89a5cbbaa6 abc_ops_reintegrate: xaiger2 compatibility 2026-08-03 12:34:01 +01:00
Lofty 6d9f5d1b0c wip 2026-08-03 12:34:01 +01:00
Krystine Sherwin 2f8cf84882
alumacc: cmp_mergeable function 
Replace all the existing mergeable checks with a call to a single function.
Fix remaining discrepencies (undersized output and mismatched signed inputs).
 2026-07-31 16:59:57 +12:00
Krystine Sherwin bb49b0be32
alumacc: Fix get_lt for oversized output 
Current behavior uses the output width to determine the MSb(s), however this is not correct if the output is larger than the inputs (which doesn't happen when creating an `$alu` for a compare op, but does when folding a compare op into an arithmetic `$alu`).

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2026-07-31 16:59:56 +12:00
Emil J c03bbc3309
Merge pull request #6069 from YosysHQ/emil/liberty-flop-fix-polarity 
read_liberty: fix set&reset polarity
 2026-07-30 15:34:24 +00:00
Emil J. Tywoniak 5f5f8b99b1 liberty: cleanup 2026-07-30 16:44:12 +02:00
Emil J. Tywoniak 82914a0204 dfflibmap: error on wide registers in design 2026-07-27 22:24:28 +02:00
Emil J. Tywoniak 6585661740 aigmap: remove unused and_cache 2026-07-27 16:50:38 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
Lofty 45e1de36b4 abc: remove -fast (again) 2026-07-21 09:50:14 +01:00
Emil J. Tywoniak 332ea782eb dfflibmap: fix resetval clobber 2026-07-14 15:01:31 +02:00
nella 68aaa34975 Reformat scl cache. 2026-07-10 14:51:58 +02:00
nella b678c238e4 Include build datetime in scl cache hash. 2026-07-10 12:44:34 +02:00
Lofty 75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Lofty 091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
nella a5bdb29d7f Recognise asynchronous set/reset. 2026-06-15 15:44:50 +02:00
nella 05805e8b93
Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements 
arith_tree improvements
 2026-06-12 14:23:10 +00:00
nella 135c2a4113 Get rid of normalize_to_width. 2026-06-11 01:12:35 +02:00
nella c47ed4bc31 Fix help. 2026-06-08 13:47:56 +02:00
nella 3c6900a570 Depth-schedule finar adder. 2026-06-08 13:47:56 +02:00
nella f8d2252735 Use ripple as default final adder, gate fma. 2026-06-08 13:47:56 +02:00
nella d40431f249 Remove black boxes for now. 2026-06-08 13:29:05 +02:00
nella 5e4e5a1d40 Arith tree - parallel prefix. 2026-06-08 13:29:05 +02:00
nella 862e9fc54e Remove elarith-fast for now. 2026-06-08 13:29:05 +02:00
nella 25eb394ad0 Collapse signed*signed or combined nodes via BW. 2026-06-08 13:29:05 +02:00