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Get rid of normalize_to_width.

This commit is contained in:
nella 2026-06-11 01:12:35 +02:00
parent c44d24d9fd
commit 135c2a4113
3 changed files with 8 additions and 27 deletions
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23
kernel/compressor_tree.cc
View File

@ -43,23 +43,6 @@ std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpe
return {sum, carry};
}
SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
{
// Zero/sign-extend to width
if (GetSize(sig) < width) {
SigBit pad;
if (is_signed && GetSize(sig) > 0)
pad = sig[GetSize(sig) - 1];
else
pad = State::S0;
sig.append(SigSpec(pad, width - GetSize(sig)));
}
// Truncate to width
if (GetSize(sig) > width)
sig = sig.extract(0, width);
return sig;
}
std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
int width_a = GetSize(a);
int width_b = GetSize(b);
@ -72,7 +55,7 @@ std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSp
// b_shifted = (0_i ## b)
SigSpec b_shifted = SigSpec(State::S0, i);
b_shifted.append(b);
b_shifted = normalize_to_width(b_shifted, false, width);
b_shifted.extend_u0(width, false);
// row = b_shifted & replicate(a[i], width)
SigSpec ai_rep = SigSpec(ai, width);
@ -333,8 +316,8 @@ FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
case FinalMode::AUTO:
default: {
bool wide = width >= RIPPLE_PREFIX_THRESHOLD;
bool deep = final_depth >= PREFIX_DEPTH_THRESHOLD;
bool wide = width >= RIPPLE_PREFIX_WIDTH_THRESHOLD;
bool deep = final_depth >= RIPPLE_PREFIX_DEPTH_THRESHOLD;
return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
}
}

6
kernel/compressor_tree.h
View File

@ -30,8 +30,8 @@ namespace CompressorTree
{
// Width and depth thresholds below which a ripple is preferred over parallel-prefix
constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
constexpr int PREFIX_DEPTH_THRESHOLD = 5;
constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;
enum class Strategy {
FA_ONLY, // 3:2 compressors
@ -59,8 +59,6 @@ enum class FinalMode {
std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
/**
* generate_partial_products() - Generate partial products for FMA concat
* @module:The Yosys module to which the compressors will be added

6
passes/techmap/arith_tree.cc
View File

@ -304,10 +304,10 @@ struct ArithTreeWorker {
for (auto &op : operands) {
if (GetSize(op.factor_b) == 0) {
// Additive operand
SigSpec s = CompressorTree::normalize_to_width(op.sig, op.is_signed, width);
op.sig.extend_u0(width, op.is_signed);
if (op.negate)
s = module->Not(NEW_ID, s);
pool.push_back({s, 0});
op.sig = module->Not(NEW_ID, op.sig);
pool.push_back({op.sig, 0});
} else {
// Multiplicative operand
auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);