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cleanup

This commit is contained in:
Lofty 2026-08-03 13:25:33 +01:00
parent 89a5cbbaa6
commit 5e6fcf3b36
5 changed files with 4 additions and 13 deletions
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6
passes/techmap/abc_new.cc
View File

@ -191,13 +191,11 @@ struct AbcNewPass : public ScriptPass {
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir));
run(stringf(" debug write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
run(stringf(" read_aiger -xaiger -module_name %s$abc9 %s/output.aig",
modname, tmpdir));
run(stringf(" debug abc_ops_reintegrate -map %s/input.map2", tmpdir));
//run(stringf(" debug read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
// modname, tmpdir, tmpdir));
run(stringf(" abc_ops_reintegrate -map %s/input.map2", tmpdir));
if (!help_mode && mod->has_attribute(ID(abc9_script))) {
if (script_save.empty())
active_design->scratchpad_unset("abc9.script");

5
passes/techmap/abc_ops_reintegrate.cc
View File

@ -551,11 +551,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
for (auto port : mapped_mod->ports) {
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
if (!wire) {
log_debug("looking for port %s\n", port);
continue;
}
log_assert(wire);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));

2
techlibs/gatemate/synth_gatemate.cc
View File

@ -332,7 +332,7 @@ struct SynthGateMatePass : public ScriptPass
abc_args += " -dff";
}
if (abc_new) {
run("abc_new -nocleanup " + abc_args, "(with -luttree and -abc_new)");
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}

2
tests/arch/ice40/fsm.ys
View File

@ -1,5 +1,3 @@
scratchpad -set abc9.nocleanup 1
read_verilog ../common/fsm.v
hierarchy -top fsm
proc

2
tests/techmap/xaiger2-5169.ys
View File

@ -56,5 +56,5 @@ endmodule
EOF
logger -expect error "Malformed design" 1
logger -expect error "Cannot find existing box cell" 1
abc_new -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib