[core] debug yosys version extraction
[core] debug
[core] now cache the cmake source dir
[core] debug
[core] debug kernel dependencies
[core] debug common include directories
[core] debug
[core] debug simlib_help.inc
[core] debug pmgen py path in cmake
[core] syntax
[core] debug flex source
[core] restore
[core] debug executable output as it now shows linking to .
[core] debug yosys-abc directory
[core] debug cmake share directory
[core] debug yosys abc
[core] restore shared directory location as yosys requires fixed location
[core] rework link target to yosys sub dir under build
[core] fixed the bug on yosys-config.install location for install
[core] cmake syntax
[core] correct the location for share directory
[core] debug
[core] debug
[core] debug
[core] enforce internal attributes; rename the YOSYS_ENABLE_UNIT_TESTS; use YOSYS_CMAKE_BINARY_DIR for all
[core] apply review comments
[core] rename
[core] change all the CMAKE_BINARY_DIR to YOSYS_CMAKE_BINARY_DIR
[core] replace CMAKE_SOURCE_DIR to YOSYS_CMAKE_SOURCE_DIR
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.
Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
Recurse over memory dimensions once, doing both our min/max address checking and parsing out the initval. This also avoids problems with negative numbers (if `a < b` and one or both are negative, `a` might be the intended `max_addr_chunk`).
Fix sub addressing, where we use some but not all of the current dimension's bits.
May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic.
Still needs to adjust ascii init val addresses, but should work fine for read/write accesses.