mirror of https://github.com/YosysHQ/yosys.git
May not be the best approach, insofar as it uses empty memory elements for padding out the alignment, but it does avoid costly address arithmetic. Still needs to adjust ascii init val addresses, but should work fine for read/write accesses. |
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| aiger | ||
| aiger2 | ||
| ast | ||
| blif | ||
| json | ||
| liberty | ||
| rpc | ||
| rtlil | ||
| verific | ||
| verilog | ||