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fix handling of multiple modules 

Co-authored-by: nella <nella@yosyshq.com>
This commit is contained in:
Lofty 2026-08-10 10:17:31 +01:00
parent 7c7bc0c617
commit d1357f171f
2 changed files with 22 additions and 6 deletions
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15
frontends/aiger/aigerparse.cc
View File

@ -480,19 +480,22 @@ void AigerReader::parse_xaiger()
mapping_cell.type = RTLIL::escape_id(cellName);
mapping_cell.out = RTLIL::escape_id(outPinName);
auto module = design->addModule(RTLIL::escape_id(cellName));
module->set_bool_attribute(ID::blackbox);
module->addWire(RTLIL::escape_id(outPinName))->port_output = true;
for (unsigned j = 0; j < inPinNum; ++j) {
auto inPinName = std::string{};
std::getline(f, inPinName, '\0');
log_debug2("M: inPinName=%s\n", inPinName);
mapping_cell.ins.push_back(RTLIL::escape_id(inPinName));
module->addWire(RTLIL::escape_id(inPinName))->port_input = true;
}
module->fixup_ports();
if (!design->module(mapping_cell.type)) {
auto module = design->addModule(mapping_cell.type);
module->set_bool_attribute(ID::blackbox);
module->addWire(mapping_cell.out)->port_output = true;
for (unsigned j = 0; j < inPinNum; ++j) {
module->addWire(mapping_cell.ins.at(j))->port_input = true;
}
module->fixup_ports();
}
mapping_cells.push_back(std::move(mapping_cell));
}

13
tests/techmap/abc_new.ys Normal file
View File

@ -0,0 +1,13 @@
read_verilog <<EOT
module sub(input a, b, c, output y);
assign y = (a & b) | c;
endmodule
module top(input a, b, c, d, output y, z);
assign z = (a ^ b) & d;
sub s_i (.a(a), .b(b), .c(c), .y(y));
endmodule
EOT
hierarchy -top top
techmap
abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib