mirror of https://github.com/YosysHQ/yosys.git
verific: Added sv2023 support, and cleanup
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17d51a3307
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92bdbafe82
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@ -3177,7 +3177,7 @@ struct VerificPass : public Pass {
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log("\n");
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|\n");
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log(" -sv2017|-sv} <verilog-file>..\n");
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log(" -sv2017|-sv2023|-sv} <verilog-file>..\n");
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log("\n");
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log("Load the specified Verilog/SystemVerilog files into Verific.\n");
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log("Note that -sv option will use latest supported SystemVerilog standard.\n");
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@ -3228,7 +3228,7 @@ struct VerificPass : public Pass {
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#ifdef VERIFIC_VHDL_SUPPORT
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log(" -vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl|\n");
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#endif
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log(" -sv2012|-sv2017|-sv|-formal] <command-file>\n");
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log(" -sv2012|-sv2017|-sv2023|-sv|-formal] <command-file>\n");
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log("\n");
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log("Load and execute the specified command file.\n");
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log("Override verilog parsing mode can be set.\n");
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@ -3790,6 +3790,9 @@ struct VerificPass : public Pass {
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} else if (args[argidx] == "-sv2017") {
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verilog_mode = veri_file::SYSTEM_VERILOG_2017;
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continue;
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} else if (args[argidx] == "-sv2023") {
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verilog_mode = veri_file::SYSTEM_VERILOG_2023;
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continue;
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} else if (args[argidx] == "-sv" || args[argidx] == "-formal") {
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verilog_mode = veri_file::SYSTEM_VERILOG;
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if (args[argidx] == "-formal") is_formal = true;
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@ -3877,8 +3880,8 @@ struct VerificPass : public Pass {
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}
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if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
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args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv2017" || args[argidx] == "-sv" ||
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args[argidx] == "-formal"))
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args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv2017" || args[argidx] == "-sv2023" ||
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args[argidx] == "-sv" || args[argidx] == "-formal"))
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{
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Array file_names;
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unsigned verilog_mode;
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@ -3895,6 +3898,8 @@ struct VerificPass : public Pass {
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verilog_mode = veri_file::SYSTEM_VERILOG_2012;
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else if (args[argidx] == "-sv2017")
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verilog_mode = veri_file::SYSTEM_VERILOG_2017;
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else if (args[argidx] == "-sv2023")
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verilog_mode = veri_file::SYSTEM_VERILOG_2023;
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else if (args[argidx] == "-sv" || args[argidx] == "-formal")
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verilog_mode = veri_file::SYSTEM_VERILOG;
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else
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@ -4473,7 +4478,8 @@ struct ReadPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
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log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|\n");
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log(" -sv2017|-sv2023|-sv|-formal} <verilog-file>..\n");
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log("\n");
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log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
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log("is only available via Verific.)\n");
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@ -4572,7 +4578,8 @@ struct ReadPass : public Pass {
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return;
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}
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if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv" || args[1] == "-formal") {
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if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" ||
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args[1] == "-sv2017" || args[1] == "-sv2023" || args[1] == "-sv" || args[1] == "-formal") {
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if (use_verific) {
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args[0] = "verific";
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} else {
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