mirror of https://github.com/YosysHQ/yosys.git
Clean up diagnostics.
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parent
dfa887637a
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2b5755178f
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@ -45,13 +45,17 @@ using namespace AST;
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using namespace VERILOG_FRONTEND;
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void ConstParser::log_maybe_loc_error(std::string msg) {
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log_file_error(loc.begin.filename ? loc.begin.filename->c_str() : "INTERNAL",
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loc.begin.line, "%s", msg);
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if (loc.begin.filename)
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log_file_error(*loc.begin.filename, loc.begin.line, "%s", msg);
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else
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log_error("Failed to parse constant `%s': %s", code_str, msg);
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}
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void ConstParser::log_maybe_loc_warn(std::string msg) {
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log_file_warning(loc.begin.filename ? loc.begin.filename->c_str() : "INTERNAL",
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loc.begin.line, "%s", msg);
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if (loc.begin.filename)
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log_file_warning(*loc.begin.filename, loc.begin.line, "%s", msg);
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else
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log_warning("While parsing constant `%s': %s", code_str, msg);
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}
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// divide an arbitrary length decimal number by two and return the rest
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@ -160,6 +164,8 @@ void ConstParser::my_strtobin(std::vector<RTLIL::State> &data, const char *str,
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// convert the Verilog code for a constant to an AST node
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std::unique_ptr<AstNode> ConstParser::const2ast(std::string code, char case_type, bool warn_z)
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{
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code_str = code;
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if (warn_z) {
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auto ret = const2ast(code, case_type);
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if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
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@ -42,6 +42,8 @@ namespace VERILOG_FRONTEND
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/* Ephemeral context class */
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struct ConstParser {
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AST::AstSrcLocType loc;
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// original constant text, used in diagnostics when loc has no source file
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std::string code_str = {};
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private:
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void log_maybe_loc_error(std::string msg);
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void log_maybe_loc_warn(std::string msg);
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@ -0,0 +1,15 @@
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# https://github.com/YosysHQ/yosys/issues/6009
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read_verilog <<EOT
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module top(output [7:0] o);
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assign o = 8'hAA;
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endmodule
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EOT
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prep -top top
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# width mismatch
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logger -expect warning "While parsing constant `2'd7'" 1
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setattr -set foo 2'd7 t:*
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# multi-bit unsized const
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logger -expect error "Failed to parse constant `8'00000101'" 1
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setattr -set foo 8'00000101 t:*
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