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2618 Commits

Author SHA1 Message Date
Emil J. Tywoniak 9d41958e6a coolrunner2: twines 2026-06-24 11:52:53 +02:00
Emil J. Tywoniak ecfced8f0d techlibs: fix twines 2026-06-23 16:00:19 +02:00
Emil J. Tywoniak 7c73fd62e4 twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
Emil J. Tywoniak 0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak dcc74755e7 WIP 2026-06-15 11:26:09 +02:00
Emil J. Tywoniak d22805bd47 WIP 2026-06-12 16:25:07 +02:00
Emil J. Tywoniak c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak afdae7b87e WIP 2026-06-11 20:02:02 +02:00
Emil J. Tywoniak 8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak 3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak c3457e2e5c WIP 2026-06-10 14:52:50 +02:00
Emil J. Tywoniak 19a4c29a0e Revert "intel: register bram celltypes" 
This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.
 2026-05-22 18:40:16 +02:00
Emil J. Tywoniak 41b3dbbc28 xilinx_dsp: signorm compatibility 2026-05-22 18:40:01 +02:00
Emil J. Tywoniak 6fd7f5c02d pmgen: hold sigmap pointer instead of owning it 2026-05-22 18:40:01 +02:00
Emil J. Tywoniak 9717a558cc intel: register bram celltypes 2026-05-22 18:39:42 +02:00
Emil J. Tywoniak 14eaedace4 gowin: replace positional arguments in cells_sim.v with named 2026-05-22 18:39:42 +02:00
Emil J. Tywoniak 68bb5c6b94 signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
Emil J. Tywoniak 07628a4042 synth_ice40: always read abc9 model to understand port direction 2026-05-22 18:37:13 +02:00
Miodrag Milanovic 75dcbe03c6 Convert RTLIL::unescape_id of IdString to unescape() 2026-05-16 19:49:45 +02:00
Miodrag Milanovic 8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
Miodrag Milanovic 965a3e67f0 Remove pmgen related users of log_id 2026-05-14 17:28:10 +02:00
Miodrag Milanovic 4a7878b17f Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
Miodrag Milanovic 58df27ce7c Refactor uses of log_id in pgm files 2026-05-14 12:21:32 +02:00
Codexplorer e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Lofty ab316c14d2
Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5 
abc_new: integration testing via synth_gatemate
 2026-05-06 13:40:15 +00:00
Lofty fecea911ff synth_gatemate: add -abc_new option 2026-05-06 14:02:48 +01:00
nella fff034d2f8 Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
nella 16b893bd88 Add check before flatten in synth. 2026-05-04 19:05:00 +02:00
Ethan Mahintorabi 805c302411
simplemap: Moves $pmux mapping from techmap.v to simple map 
This Fixes the slow downs I observed in techmap.v, which we
attempted to fix via the simplify ast.h route originally. This
turned out to be rather complex though.

By moving $pmux to simplemap we can just avoid that code. My
test case now runs in 310s which is 40s faster than the baseline
change.

B:507898959
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2026-04-29 21:20:39 +00:00
Lofty 5197b9c8ce
Merge pull request #5833 from ghaworth/fix-sdp-dipbdip-typo 
Fix RAMB36E1/E2 SDP parity port mapping typo
 2026-04-25 08:41:31 +00:00
Emil J 2dc69a7578
Merge pull request #5828 from YosysHQ/emil/bash-no-fhs 
Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash
 2026-04-23 15:47:57 +00:00
Emil J. Tywoniak 14d0138d0c Remove FHS dependency by replacing /bin/sh with /usr/bin/env sh 2026-04-23 15:55:11 +02:00
George Haworth aba5b279c6 Fix RAMB36E1/E2 SDP parity port mapping typo 
DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.

Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.
 2026-04-18 19:10:18 +03:00
Emil J. Tywoniak 3e45f9729e fix $specrule port naming 2026-04-13 22:34:46 +02:00
nella fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella 0f61ba5299 Move csa after alumacc. 2026-04-13 12:48:05 +02:00
nella b64b75db7a Add csa to synth. 2026-04-13 12:48:05 +02:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Miodrag Milanović cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J. Tywoniak 0e7f7c826d simcells: $dffsr and derivatives undefine S&R in logic tables 2026-03-19 19:27:30 +01:00
Lofty c4cc53a72e synth: fix after abc -fast removal 2026-03-18 17:59:58 +01:00
Marcel Jung 49ecb1ac11 fabulous: add frame_config_mux BEls 2026-03-12 16:05:21 +01:00
Lofty 53939bd3ba synth_quicklogic: fix small multiplier inference 2026-03-11 11:14:09 +00:00
Lofty 050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Justin Zaun d9737acc31 gowin: remove lib_whitebox from latch sim cells 
Latches are sequential elements and don't need lib_whitebox.
 2026-03-05 16:04:23 +01:00
Justin Zaun 9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
 2026-03-05 16:04:23 +01:00
Lofty da83c93673 analogdevices: fix SHIFTX name 2026-03-05 05:37:13 +00:00