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techlibs: fix twines

This commit is contained in:
Emil J. Tywoniak 2026-06-23 16:00:19 +02:00
parent ffde59d21e
commit ecfced8f0d
4 changed files with 9 additions and 9 deletions
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4
techlibs/coolrunner2/coolrunner2_sop.cc
View File

@ -63,13 +63,13 @@ struct Coolrunner2SopPass : public Pass {
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
{
if (cell->hasPort(TW(PRE)))
if (cell->hasPort(TW::PRE))
special_pterms_no_inv[sigmap(cell->getPort(TW::PRE)[0])].insert(
make_tuple(cell, ID(PRE)));
if (cell->hasPort(TW::CLR))
special_pterms_no_inv[sigmap(cell->getPort(TW::CLR)[0])].insert(
make_tuple(cell, ID::CLR));
if (cell->hasPort(TW(CE)))
if (cell->hasPort(TW::CE))
special_pterms_no_inv[sigmap(cell->getPort(TW::CE)[0])].insert(
make_tuple(cell, ID(CE)));

8
techlibs/nanoxplore/nx_carry.cc
View File

@ -39,7 +39,7 @@ static void nx_carry_chain(Module *module)
{
if (cell->type == ID(NX_CY_1BIT)) {
if (cell->getParam(ID(first)).as_int() == 1) continue;
if (!cell->hasPort(TW(CI)))
if (!cell->hasPort(TW::CI))
log_error("Not able to find connected carry.\n");
SigBit ci = sigmap(cell->getPort(TW::CI).as_bit());
carry[ci] = cell;
@ -65,7 +65,7 @@ static void nx_carry_chain(Module *module)
//log_error("Not able to find connected carry.\n");
current = carry[co];
chain.push_back(current);
if (!current->hasPort(TW(CO))) break;
if (!current->hasPort(TW::CO)) break;
co = sigmap(current->getPort(TW::CO).as_bit());
}
carry_chains[cell] = chain;
@ -117,7 +117,7 @@ static void nx_carry_chain(Module *module)
cell->setPort(TW::B1, State::S0);
j = 1;
} else {
if (c.second.at(i)->hasPort(TW(CO)))
if (c.second.at(i)->hasPort(TW::CO))
cell->setPort(TW::CO, c.second.at(i)->getPort(TW::CO));
}
cnt++;
@ -125,7 +125,7 @@ static void nx_carry_chain(Module *module)
cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(TW::A)));
cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(TW::B)));
if (c.second.at(i)->hasPort(TW(S)))
if (c.second.at(i)->hasPort(TW::S))
cell->setPort(names_S[j], c.second.at(i)->getPort(TW::S));
j = (j + 1) % 4;

2
techlibs/quicklogic/ql_dsp_io_regs.cc
View File

@ -88,7 +88,7 @@ struct QlDspIORegs : public Pass {
int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
// Get the feedback port
if (!cell->hasPort(TW(feedback)))
if (!cell->hasPort(TW::feedback))
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(TW::feedback));

4
techlibs/quicklogic/ql_dsp_macc.cc
View File

@ -113,7 +113,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
RTLIL::SigSpec rst;
RTLIL::SigSpec ena;
if (st.ff->hasPort(TW(ARST))) {
if (st.ff->hasPort(TW::ARST)) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST));
} else {
@ -123,7 +123,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
rst = RTLIL::SigSpec(RTLIL::S0);
}
if (st.ff->hasPort(TW(EN))) {
if (st.ff->hasPort(TW::EN)) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN));
} else {