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Fix RAMB36E1/E2 SDP parity port mapping typo 

DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.

Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.
This commit is contained in:
George Haworth 2026-04-17 02:10:05 +03:00
parent 413169663d
commit aba5b279c6
2 changed files with 2 additions and 2 deletions
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2
techlibs/xilinx/brams_xc6v_map.v
View File

@ -275,7 +275,7 @@ end else if (OPTION_MODE == "FULL") begin
.DIADI(DI[31:0]),
.DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
.DIPADIP(DIP[3:0]),
.DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
.DIPBDIP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]),
);
end

2
techlibs/xilinx/brams_xcu_map.v
View File

@ -215,7 +215,7 @@ end else if (OPTION_MODE == "FULL") begin
.DINADIN(DI[31:0]),
.DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]),
.DINPADINP(DIP[3:0]),
.DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]),
.DINPBDINP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]),
);
end