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simcells: $dffsr and derivatives undefine S&R in logic tables

This commit is contained in:
Emil J. Tywoniak 2026-03-19 19:27:30 +01:00
parent 498cb79abe
commit 0e7f7c826d
1 changed files with 24 additions and 0 deletions
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24
techlibs/common/simcells.v
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@ -1613,6 +1613,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 0 - | x
//- - - 0 - | 0
//- - 0 - - | 1
//- \ - - d | d
@ -1641,6 +1642,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 1 - | x
//- - - 1 - | 0
//- - 0 - - | 1
//- \ - - d | d
@ -1669,6 +1671,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 0 - | x
//- - - 0 - | 0
//- - 1 - - | 1
//- \ - - d | d
@ -1697,6 +1700,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 1 - | x
//- - - 1 - | 0
//- - 1 - - | 1
//- \ - - d | d
@ -1725,6 +1729,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 0 - | x
//- - - 0 - | 0
//- - 0 - - | 1
//- / - - d | d
@ -1753,6 +1758,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 0 1 - | x
//- - - 1 - | 0
//- - 0 - - | 1
//- / - - d | d
@ -1781,6 +1787,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 0 - | x
//- - - 0 - | 0
//- - 1 - - | 1
//- / - - d | d
@ -1809,6 +1816,7 @@ endmodule
//-
//- Truth table: C S R D | Q
//- ---------+---
//- - 1 1 - | x
//- - - 1 - | 0
//- - 1 - - | 1
//- / - - d | d
@ -1837,6 +1845,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
@ -1865,6 +1874,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
@ -1893,6 +1903,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 0 d | d
@ -1921,6 +1932,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- \ - - 1 d | d
@ -1949,6 +1961,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
@ -1977,6 +1990,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
@ -2005,6 +2019,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 0 d | d
@ -2033,6 +2048,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- \ - - 1 d | d
@ -2061,6 +2077,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
@ -2089,6 +2106,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 0 - - | x
//- - - 0 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
@ -2117,6 +2135,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 0 d | d
@ -2145,6 +2164,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 0 1 - - | x
//- - - 1 - - | 0
//- - 0 - - - | 1
//- / - - 1 d | d
@ -2173,6 +2193,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
@ -2201,6 +2222,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 0 - - | x
//- - - 0 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d
@ -2229,6 +2251,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 0 d | d
@ -2257,6 +2280,7 @@ endmodule
//-
//- Truth table: C S R E D | Q
//- -----------+---
//- - 1 1 - - | x
//- - - 1 - - | 0
//- - 1 - - - | 1
//- / - - 1 d | d