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WIP

This commit is contained in:
Emil J. Tywoniak 2026-06-15 11:26:09 +02:00
parent d22805bd47
commit dcc74755e7
18 changed files with 74 additions and 72 deletions
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4
backends/rtlil/rtlil_backend.cc
View File

@ -211,7 +211,7 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL
void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, bool resolve_src)
{
dump_attributes(f, indent, cell, design, resolve_src);
f << stringf("%s" "cell %s %s\n", indent, cell->type, cell->name);
f << stringf("%s" "cell %s %s\n", indent, cell->type.str(), cell->name.str());
for (const auto& [name, param] : reversed(cell->parameters)) {
f << stringf("%s parameter%s%s%s %s ", indent,
(param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "",
@ -222,7 +222,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::
f << stringf("\n");
}
for (const auto& [port, sig] : reversed(cell->connections_)) {
f << stringf("%s connect %s ", indent, port);
f << stringf("%s connect %s ", indent, design->twines.unescaped_str(port));
dump_sigspec(f, sig);
f << stringf("\n");
}

9
backends/smt2/smt2.cc
View File

@ -627,7 +627,7 @@ struct Smt2Worker
}
if (cell->attributes.count(ID::reg))
infostr += " " + cell->attributes.at(ID::reg).decode_string();
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr));
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.unescape(), get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr));
if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str());
@ -1142,10 +1142,10 @@ struct Smt2Worker
if (private_name && cell->has_attribute(ID::src)) {
string raw_src = cell->get_src_attribute();
decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), raw_src.c_str()));
decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.unescape(), id, get_id(cell), raw_src.c_str()));
}
else
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell)));
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.unescape(), id, get_id(cell)));
if (cell->type == TW($cover))
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
@ -1536,8 +1536,7 @@ struct Smt2Worker
std::string witness_signal(const char *type, int width, int offset, const std::string &smtname, int smtid, RTLIL::Wire *wire, int smtoffset = 0)
{
std::vector<std::string> hiername;
const char *wire_name = wire->name.c_str();
if (wire_name[0] == '\\') {
if (wire->meta_->name.is_public()) {
auto hdlname = wire->get_string_attribute(ID::hdlname);
for (auto token : split_tokens(hdlname))
hiername.push_back("\\" + token);

2
backends/verilog/verilog_backend.cc
View File

@ -1798,7 +1798,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*");
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") %s(", cell->type.c_str()+1);
f << stringf(") %s(", cell->type.unescape());
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(");\n");
return true;

2
frontends/ast/genrtlil.cc
View File

@ -502,7 +502,7 @@ struct AST_INTERNAL::ProcessGenerator
std::string wire_name;
do {
wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
chunk.wire->name, chunk.width+chunk.offset-1, chunk.offset);;
if (chunk.wire->name.str().find('$') != std::string::npos)
wire_name += stringf("$%d", autoidx++);
} while (current_module->wire(current_module->design->twines.lookup(wire_name)) != nullptr);

2
frontends/ast/simplify.cc
View File

@ -1517,7 +1517,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
// create the indirection wire
std::stringstream sstr;
sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
sstr << "$indirect$" << ref->name.str() << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
std::string tmp_str = sstr.str();
add_wire_for_ref(location, ref, tmp_str);

20
frontends/rtlil/rtlil_frontend.cc
View File

@ -366,8 +366,8 @@ struct RTLILFrontendWorker {
if (flag_legalize)
wire = legalize_wire(*id);
else {
// for (auto wire : current_module->wires())
// design->twines.dump(wire->meta_->name);
for (auto wire : current_module->wires())
design->twines.dump(wire->meta_->name);
error("Wire `%s' not found.", *id);
}
}
@ -613,20 +613,20 @@ struct RTLILFrontendWorker {
while (true)
{
std::optional<RTLIL::IdString> id = try_parse_id();
if (id.has_value()) {
TwineRef wire_name = design->twines.lookup(id->str());
std::optional<std::string> id = try_parse_id();
if (id) {
TwineRef wire_name = design->twines.lookup(*id);
if (wire_name == Twine::Null)
wire_name = design->twines.add(Twine{id->str()});
wire_name = design->twines.add(std::move(*id));
if (current_module->wire(wire_name) != nullptr) {
if (flag_legalize) {
if (flag_legalize) {
log("Legalizing redefinition of wire %s.\n", *id);
pool<RTLIL::Wire*> wires = {current_module->wire(wire_name)};
current_module->remove(wires);
} else
error("RTLIL error: redefinition of wire %s.", *id);
}
wire = current_module->addWire(Twine{id->str()});
wire = current_module->addWire(wire_name);
break;
}
if (try_parse_keyword("width"))
@ -779,9 +779,7 @@ struct RTLILFrontendWorker {
expect_eol();
} else if (try_parse_keyword("connect")) {
std::string port_name_str = parse_id();
TwineRef port_name = design->twines.lookup(port_name_str);
if (port_name == Twine::Null)
port_name = design->twines.add(Twine{port_name_str});
TwineRef port_name = design->twines.add(Twine{port_name_str});
if (cell->hasPort(port_name)) {
if (flag_legalize)
log("Legalizing redefinition of cell port %s.", port_name_str);

6
kernel/rtlil.cc
View File

@ -1988,8 +1988,8 @@ namespace {
std::string mod_name = module ? module->design->twines.str(module->meta_->name) : std::string();
std::string cell_name = cell->module->design->twines.str(cell->meta_->name);
log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
mod_name.c_str(), module ? "." : "",
cell_name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
mod_name, module ? "." : "",
cell_name, cell->type.str(), __FILE__, linenr, buf.str());
}
int param(IdString name)
@ -2066,7 +2066,7 @@ namespace {
cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
return;
if (cell->type == TW($buf)) {
if (cell->type_impl == TW($buf)) {
port(TW::A, param(ID::WIDTH));
port(TW::Y, param(ID::WIDTH));
check_expected();

20
kernel/rtlil.h
View File

@ -1353,19 +1353,22 @@ struct NameMasqBase {
if (s.empty()) return RTLIL::IdString{};
return RTLIL::IdString(s);
}
operator std::string() const {
return self().escaped();
}
bool isPublic() const { return twine_is_public(self().ref()); }
bool empty() const { return RTLIL::IdString(self()).empty(); }
std::string str() const { return self().escaped(); }
const char *c_str() const { return RTLIL::IdString(self()).c_str(); }
std::string unescape() const { return self().unescaped(); }
bool begins_with(const char *s) const { return RTLIL::IdString(self()).begins_with(s); }
bool ends_with(const char *s) const { return RTLIL::IdString(self()).ends_with(s); }
bool begins_with(const char *s) const { return str().starts_with(s); }
bool ends_with(const char *s) const { return str().ends_with(s); }
template <typename... Ts> bool in(Ts &&...args) const {
return RTLIL::IdString(self()).in(std::forward<Ts>(args)...);
}
std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
return RTLIL::IdString(self()).substr(pos, len);
}
// TODO less IdString construction in masquerades
size_t size() const { return RTLIL::IdString(self()).size(); }
bool contains(const char *p) const { return RTLIL::IdString(self()).contains(p); }
char operator[](int n) const { return RTLIL::IdString(self()).str()[n]; }
@ -1438,19 +1441,18 @@ struct RTLIL::CellTypeMasq {
bool isPublic() const { return twine_is_public(ref()); }
bool empty() const { return ref() == Twine::Null; }
std::string str() const { return escaped(); } // TODO deprecate
const char *c_str() const { return RTLIL::IdString(*this).c_str(); }
std::string unescape() const { return unescaped(); }
bool begins_with(const char *s) const { return RTLIL::IdString(*this).begins_with(s); }
bool ends_with(const char *s) const { return RTLIL::IdString(*this).ends_with(s); }
bool begins_with(const char *s) const { return str().starts_with(s); }
bool ends_with(const char *s) const { return str().ends_with(s); }
template <typename... Ts> bool in(Ts &&...args) const {
return ref().in(std::forward<Ts>(args)...);
}
std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
return RTLIL::IdString(*this).substr(pos, len);
}
size_t size() const { return RTLIL::IdString(*this).size(); }
bool contains(const char *p) const { return RTLIL::IdString(*this).contains(p); }
char operator[](int n) const { return RTLIL::IdString(*this).str()[n]; }
size_t size() const { return str().size(); }
// bool contains(const char *p) const { return str().contains(p); }
char operator[](int n) const { return str()[n]; }
bool operator==(RTLIL::IdString rhs) const { return RTLIL::IdString(*this) == rhs; }
bool operator!=(RTLIL::IdString rhs) const { return RTLIL::IdString(*this) != rhs; }
bool operator<(RTLIL::IdString rhs) const { return RTLIL::IdString(*this) < rhs; }

2
passes/cmds/design.cc
View File

@ -290,7 +290,7 @@ struct DesignPass : public Pass {
if (done.count(cell->type) == 0)
{
std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));
std::string trg_name = prefix + "." + (cell->type.unescape());
log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name));

4
passes/cmds/rename.cc
View File

@ -162,7 +162,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
for (auto chunk : sig_out.chunks()) {
if (chunk.is_wire() && !chunk.wire->name.isPublic()) {
std::string name = stringf("%s_%s", cell->type.c_str() + 1, cell->name.c_str() + 1);
std::string name = stringf("%s_%s", cell->type.unescape(), cell->name.unescape());
for (auto &c : name)
if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
c = '_';
@ -184,7 +184,7 @@ static bool rename_witness(RTLIL::Design *design, dict<RTLIL::Module *, int> &ca
has_witness_signals = true;
if (cell->name.isPublic())
continue;
std::string name = stringf("%s_%s", cell->type.c_str() + 1, cell->name.c_str() + 1);
std::string name = stringf("%s_%s", cell->type.unescape(), cell->name.unescape());
for (auto &c : name)
if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_')
c = '_';

2
passes/cmds/stat.cc
View File

@ -1019,7 +1019,7 @@ struct StatPass : public Pass {
top_mod = mod;
statdata_t data = mod_stat.at(mod->name);
if (json_mode) {
data.log_data_json(mod->name.c_str(), first_module, hierarchy_mode);
data.log_data_json(mod->name.str().c_str(), first_module, hierarchy_mode);
first_module = false;
} else {
log("\n");

6
passes/hierarchy/hierarchy.cc
View File

@ -428,7 +428,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
// We couldn't find the module anywhere. Complain if check is set.
if (check)
log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
cell_type.c_str(), parent.design->twines.str(parent.meta_->name).data(), cell.name.c_str());
cell_type.c_str(), parent.design->twines.str(parent.meta_->name).data(), cell.name);
return nullptr;
}
@ -547,7 +547,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
if (mod->get_blackbox_attribute()) {
if (flag_simcheck || (flag_smtcheck && !mod->get_bool_attribute(ID::smtlib2_module)))
log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n",
cell->type.c_str(), design->twines.str(module->meta_->name).data(), cell->name.c_str());
cell->type, design->twines.str(module->meta_->name).data(), cell->name);
continue;
}
@ -1278,7 +1278,7 @@ struct HierarchyPass : public Pass {
for (auto module : pos_mods)
for (auto wire : module->wires()) {
if (wire->port_id > 0)
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = IdString(wire->name);
}
for (auto &work : pos_work) {

34
passes/opt/opt_expr.cc
View File

@ -123,7 +123,7 @@ void log_replace_sig(RTLIL::Module *module, RTLIL::Cell *cell,
const std::string &info, RTLIL::SigSpec old_sig, RTLIL::SigSpec new_sig)
{
log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
cell->type.c_str(), cell->name.c_str(), info.c_str(),
cell->type, cell->name, info.c_str(),
module->design->twines.str(module->meta_->name).c_str(), log_signal(old_sig), log_signal(new_sig));
}
@ -887,7 +887,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (GetSize(new_sig_a) < GetSize(sig_a)) {
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(TW::A, new_sig_a);
cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true;
@ -909,7 +909,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (GetSize(new_sig_b) < GetSize(sig_b)) {
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(TW::B, new_sig_b);
cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true;
@ -934,7 +934,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a));
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(TW::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
@ -959,7 +959,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a));
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(TW::A, sig_a = new_a);
cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
@ -984,7 +984,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_b));
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(TW::B, sig_b = new_b);
cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true;
@ -1261,7 +1261,7 @@ skip_fine_alu:
ACTION_DO(TW::Y, cell->getPort(TW::A));
if (input == State::S0 && !a.is_fully_undef()) {
log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str());
cell->setPort(TW::A, SigSpec(State::Sx, GetSize(a)));
did_something = true;
goto next_cell;
@ -1470,7 +1470,7 @@ skip_fine_alu:
if (identity_wrt_a || identity_wrt_b)
{
log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), identity_wrt_a ? 'A' : 'B');
cell->type, cell->name, module->design->twines.str(module->meta_->name).c_str(), identity_wrt_a ? 'A' : 'B');
if (cell->type == TW($alu)) {
bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
@ -1796,14 +1796,14 @@ skip_identity:
// 2^B = 1<<B
if (bit_idx == 1) {
log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n",
cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
cell->name, module->design->twines.str(module->meta_->name).c_str());
cell->type_impl = TW::$shl;
cell->parameters[ID::A_WIDTH] = 1;
cell->setPort(TW::A, Const(State::S1, 1));
}
else {
log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n",
cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
cell->name, module->design->twines.str(module->meta_->name).c_str());
OptExprPatcher patcher(module, &assign_map);
int a_width = cell->parameters[ID::A_WIDTH].as_int();
@ -1846,7 +1846,7 @@ skip_identity:
if (sig_a.is_fully_zero())
{
log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
cell->name, module->design->twines.str(module->meta_->name).c_str());
OptExprPatcher patcher(module, &assign_map);
patcher.patch(cell, TW::Y, RTLIL::SigSpec(0, sig_y.size()), "mul_zero");
@ -1857,7 +1857,7 @@ skip_identity:
if (sig_a.is_onehot(&exp) && !(a_signed && exp == GetSize(sig_a) - 1))
{
log_debug("Replacing multiply-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
log_signal(sig_a), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp);
log_signal(sig_a), cell->name, module->design->twines.str(module->meta_->name).c_str(), exp);
if (!swapped_ab) {
cell->setPort(TW::A, cell->getPort(TW::B));
@ -1890,7 +1890,7 @@ skip_identity:
if (a_zeros || b_zeros) {
int y_zeros = a_zeros + b_zeros;
log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n",
a_zeros, b_zeros, cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
a_zeros, b_zeros, cell->name, module->design->twines.str(module->meta_->name).c_str());
if (y_zeros >= GetSize(sig_y)) {
OptExprPatcher patcher(module, &assign_map);
@ -1929,7 +1929,7 @@ skip_identity:
if (sig_b.is_fully_zero())
{
log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
cell->name, module->design->twines.str(module->meta_->name).c_str());
OptExprPatcher patcher(module, &assign_map);
patcher.patch(cell, TW::Y, RTLIL::SigSpec(State::Sx, sig_y.size()), "div_zero");
@ -1944,7 +1944,7 @@ skip_identity:
bool is_truncating = cell->type == TW($div);
log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n",
is_truncating ? "truncating" : "flooring",
log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp);
log_signal(sig_b), cell->name, module->design->twines.str(module->meta_->name).c_str(), exp);
Const new_b = exp;
@ -1972,7 +1972,7 @@ skip_identity:
bool is_truncating = cell->type == TW($mod);
log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n",
is_truncating ? "truncating" : "flooring",
log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str());
log_signal(sig_b), cell->name, module->design->twines.str(module->meta_->name).c_str());
// truncating modulo has the same masked bits as flooring modulo, but
// the sign bits are those of A (except when R=0)
@ -2057,7 +2057,7 @@ skip_identity:
for (auto &p : split_points)
log_debug("Splitting $alu cell `%s' in module `%s' at const-carry point %d.\n",
cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), p.first);
cell->name, module->design->twines.str(module->meta_->name).c_str(), p.first);
if (split_points.back().first != GetSize(sig_y))
split_points.push_back(std::make_pair(GetSize(sig_y), State::Sx));

2
passes/opt/opt_muxtree.cc
View File

@ -287,7 +287,7 @@ struct OptMuxtreeWorker
live_ports.push_back(port_idx);
} else {
log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports),
mi.cell->type.c_str(), mi.cell->name.c_str());
mi.cell->type, mi.cell->name);
removed_count++;
}
}

2
passes/opt/rmports.cc
View File

@ -76,7 +76,7 @@ struct RmportsPassPass : public Pass {
for(auto p : ports_to_remove)
{
log(" Removing port \"%s\" from instance \"%s\"\n",
p.c_str(), cell->type.c_str());
p.c_str(), cell->type);
cell->unsetPort(cell->module->design->twines.add(Twine{p.str()}));
}
}

2
passes/techmap/flowmap.cc
View File

@ -636,7 +636,7 @@ struct FlowmapWorker
if (fanin > order)
log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
cell->type.c_str(), module, cell, fanin, order);
cell->type, module, cell, fanin, order);
gate_count++;
gate_area += 1 << fanin;

15
passes/techmap/techmap.cc
View File

@ -612,7 +612,7 @@ struct TechmapWorker
}
for (auto &conn : cell->connections()) {
if (design->twines.str(conn.first).starts_with("$"))
if (!conn.first.is_public())
continue;
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
continue;
@ -757,9 +757,10 @@ struct TechmapWorker
techmap_wire_names.erase(it.first);
const char *p = data.wire->name.c_str();
const char *q = strrchr(p+1, '.');
q = q ? q+1 : p+1;
std::string final_id = data.wire->name.unescaped();
size_t start_idx = final_id.empty() ? 0 : 1;
size_t dot_pos = final_id.rfind('.', start_idx);
size_t split_idx = (dot_pos != std::string::npos) ? (dot_pos + 1) : start_idx;
std::string cmd_string = data.value.as_const().decode_string();
@ -864,8 +865,10 @@ struct TechmapWorker
Pass::call_on_module(map, tpl, cmd_string);
map->sigNormalize(false);
log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
// log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
std::string new_name = final_id.substr(0, split_idx)
+ "_TECHMAP_DONE_"
+ final_id.substr(split_idx + 12);
while (tpl->wire(tpl->design->twines.add(Twine{new_name})) != nullptr)
new_name += "_";
tpl->rename(data.wire->name.ref(), tpl->design->twines.add(Twine{new_name}));

12
techlibs/coolrunner2/coolrunner2_fixup.cc
View File

@ -267,9 +267,9 @@ struct Coolrunner2FixupPass : public Pass {
if (input == ibuf_out_wire)
{
log("Found IBUF %s that can be packed with FF %s (type %s)\n",
ibuf_out_wire.wire->name.c_str(),
maybe_ff_cell->name.c_str(),
maybe_ff_cell->type.c_str());
ibuf_out_wire.wire->name,
maybe_ff_cell->name,
maybe_ff_cell->type);
ibuf_out_to_packed_reg_cell[ibuf_out_wire] = maybe_ff_cell;
packed_reg_out.insert(output);
@ -448,9 +448,9 @@ struct Coolrunner2FixupPass : public Pass {
if (xor_fanout_once[wire_in])
{
log("Additional fanout found for %s into %s (type %s), duplicating\n",
xor_cell->name.c_str(),
cell->name.c_str(),
cell->type.c_str());
xor_cell->name,
cell->name,
cell->type);
auto new_xor_cell = module->addCell(
module->uniquify(xor_cell->name), xor_cell);