genrtlil records the case item as compare_src and the block as the case's
own src, so the actions inside a case point at the statements that wrote
them rather than at the selector. A $eq then stands for both sides of the
comparison it performs - the switch expression and the case value - the
$reduce_or over them for the case value, and the _CMP wire for the switch.
A mux passes its fused locations on to the wire it drives.
The gatemate fsm LUT counts go back to what they were before the source
work: the finer mapping restores the earlier covering.
Picks up the proc part of emil/twines-proc-srcloc-rebased:
b2d57e5d4 rtlil: add case_src to CaseRule
c74bc43cf proc_mux, genrtlil: make use of case_src
9bc771e05 proc_mux: copy switch src to _CMP wire
6182c7dd8 proc_mux: copy mux src to Y port
3d2e26815 kernel: add SwitchRule signal_src
cf3867bb1 proc_mux: include switch expression location in $eq src
A CaseRule's own src is where its body is; compare_src is where the case
is selected. A SwitchRule's own src is the whole statement; signal_src is
where its expression is. Both survive a clone and a cross-pool copy.
Also root the srcs a process holds outside its AttrObjects - one per
assignment, plus the two above - so garbage collection cannot free the
twines they point at.
roundtrip-src.sh checks that an `srcs` section survives write/read and a
design push/pop unchanged, and that -readable resolves the handles.
no-pipe-leaf.sh checks that fusing locations never bakes a '|'-joined
string into a twine leaf.
Source locations move off the attribute dict into a dedicated SrcRef on
AttrObject, interned in a per-design SrcPool that hash-conses sets of
location twines. Locations share their file prefix with each other through
the twine pool, and objects that fuse (opt_merge, share, ff/mem rewrites)
carry the union of their inputs' locations instead of a '|'-joined string.
write_rtlil emits an `srcs` section of location sets alongside `twines`;
read_rtlil resolves `\src "@N"` back to a handle and still accepts a plain
location string. -readable renders the locations as text.
Mixes input cells, signedness, input width, output width.
Within the things that are `random.choice`, they *should* always be equivalent, but add a seed arg anyway just in case one day they're not.
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.
Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
Emil J. Tywoniak
nella
Emil J
Catherine
Miodrag Milanovic
Krystine Sherwin
nella
drewbabel