dfflibmap: fix formal verilog test so that it actually maps all flops

2026-07-27 22:08:39 +02:00 · 2026-07-27 22:08:39 +02:00 · c50290fdab
parent 1a1d9494da
commit c50290fdab
1 changed files with 1 additions and 0 deletions
--- a/tests/techmap/dfflibmap_proc_formal.ys
+++ b/tests/techmap/dfflibmap_proc_formal.ys
@ -44,6 +44,7 @@ EOT

 proc
 opt
+techmap
 copy top top_unmapped
 design -save start