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hierarchy: regression test for keep cache
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@@ -0,0 +1,3 @@
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module top(input x, output y);
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top top_i(.x(x), .y(y));
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endmodule
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@@ -0,0 +1,25 @@
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read_verilog hierarchy_recursive.v
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hierarchy -auto-top
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select -assert-any top
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select -assert-none a:keep
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design -reset
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read_verilog <<EOT
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module top(input x, output y);
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top top_i(.x(x), .y(y));
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always @(x) $display("x=%d", x);
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endmodule
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EOT
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hierarchy -auto-top
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select -assert-any top %% a:keep
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design -reset
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read_verilog -formal <<EOT
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module a(input x); b b_i(.x(x)); endmodule
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module b(input x); a a_i(.x(x)); always @(x) assert (x == x); endmodule
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module top(input x); a a_i(.x(x)); endmodule
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EOT
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hierarchy -top top
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select -assert-any a %% a:keep
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select -assert-any b %% a:keep
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select -assert-any top %% a:keep
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