Emil J. Tywoniak dcb9c0d7af rtlil: track where a case is selected and where a switch reads ...

A CaseRule's own src is where its body is; compare_src is where the case
is selected. A SwitchRule's own src is the whole statement; signal_src is
where its expression is. Both survive a clone and a cross-pool copy.

Also root the srcs a process holds outside its AttrObjects - one per
assignment, plus the two above - so garbage collection cannot free the
twines they point at.

2026-08-25 13:09:07 +02:00

..

aiger

Move rename logic to abc_ops_reintegrate

2026-06-19 10:46:47 +01:00

alumacc

Code cleanup

2026-08-04 17:18:22 +02:00

arch

gowin: lower LUT count sensitivity

2026-08-25 12:41:46 +02:00

arith_tree

End of file fix

2026-06-23 07:23:41 +02:00

asicworld

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

bind

Use generic testing on few more places

2026-04-16 11:00:44 +02:00

blif

Cleanup

2026-04-16 11:00:44 +02:00

bram

Add initial codecov support

2026-07-10 12:19:59 +02:00

bugpoint

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

check_mem

tests/check_mem: Drop unused init check

2026-05-30 11:06:11 +12:00

cxxrtl

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

errors

End of file fix

2026-06-23 07:23:41 +02:00

fmt

Cleanup

2026-04-16 11:00:44 +02:00

fsm

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

functional

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

hana

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

liberty

Add scl caching test.

2026-07-10 14:52:06 +02:00

lut

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

memfile

Update CI scripts for CMake

2026-06-03 08:58:11 +00:00

memlib

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

memories

tests: trivial twine damage

2026-08-13 18:15:58 +02:00

opt

Add regression tests.

2026-08-06 09:14:44 +02:00

opt_share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

peepopt

Converted some more

2026-04-16 11:00:44 +02:00

proc

rtlil: track where a case is selected and where a switch reads

2026-08-25 13:09:07 +02:00

pyosys

pyosys: twines

2026-08-13 18:15:58 +02:00

realmath

Cleanup

2026-04-16 11:00:44 +02:00

rpc

Make out of tree build testing possible

2026-05-19 14:26:07 +02:00

rtlil

tests: cover source location pooling

2026-08-25 11:40:59 +02:00

sat

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

sdc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

select

Converted some more

2026-04-16 11:00:44 +02:00

share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

sim

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

simple

End of file fix

2026-06-23 07:23:41 +02:00

simple_abc9

Convert autotest script wrapper

2026-04-16 11:00:44 +02:00

smv

End of file fix

2026-06-23 07:23:41 +02:00

sva

End of file fix

2026-06-23 07:23:41 +02:00

svinterfaces

Cleanup

2026-04-16 11:00:44 +02:00

svtypes

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

symfpu

Code cleanup

2026-08-04 17:18:22 +02:00

techmap

Code cleanup

2026-08-04 17:18:22 +02:00

tools

End of file fix

2026-06-23 07:23:41 +02:00

unit

rtlil: intern source locations in a per-design SrcPool

2026-08-25 11:40:52 +02:00

various

rtlil: intern source locations in a per-design SrcPool

2026-08-25 11:40:52 +02:00

verific

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

verilog

Rm.

2026-07-07 04:03:17 +02:00

vloghtb

End of file fix

2026-06-23 07:23:41 +02:00

write_verilog

tests: Add mixed_upto write_verilog test

2026-06-19 11:20:01 +12:00

xprop

tests: trivial twine damage

2026-08-13 18:15:58 +02:00

.gitignore

Save results, and create summary and report

2026-04-16 11:00:44 +02:00

common.mk

Add VERBOSE (and V) option to Makefiles

2026-06-15 14:48:11 +02:00

gen_tests_makefile.py

Add VERBOSE (and V) option to Makefiles

2026-06-15 14:48:11 +02:00

Makefile

symfpu: Add flags

2026-07-15 14:50:25 +12:00

pass-fuzzing.md

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00