Merge pull request #6090 from YosysHQ/emil/hierarchy-fix-keep-cache-again

hierarchy: fix keep cache usage by caching false too 2

passes/hierarchy/hierarchy.cc

@@ -684,23 +684,31 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 
 bool set_keep_print(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 {
-	if (cache.count(mod) == 0)
+	if (cache.count(mod) == 0) {
+		cache[mod] = false;
 		for (auto c : mod->cells()) {
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print))
-				return cache[mod] = true;
+			if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) {
+				cache[mod] = true;
+				break;
+			}
 		}
+	}
 	return cache[mod];
 }
 
 bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 {
-	if (cache.count(mod) == 0)
+	if (cache.count(mod) == 0) {
+		cache[mod] = false;
 		for (auto c : mod->cells()) {
 			RTLIL::Module *m = mod->design->module(c->type);
-			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
-				return cache[mod] = true;
+			if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
+				cache[mod] = true;
+				break;
+			}
 		}
+	}
 	return cache[mod];
 }
 

tests/various/hierarchy_keep.ys

@@ -0,0 +1,48 @@
+read_verilog -noblackbox <<EOT
+	module top;
+		sub s0();
+		foo f0();
+	endmodule
+
+	module foo;
+		sub s0();
+		initial
+			$display("hello");
+	endmodule
+
+	module sub;
+	endmodule
+EOT
+design -save print
+hierarchy -top top
+select -assert-any top A:keep %i
+
+design -reset
+design -load print
+hierarchy -nokeep_prints -top top
+select -assert-none top A:keep %i
+
+design -reset
+read_verilog -sv -noblackbox <<EOT
+	module top;
+		sub s0();
+		foo f0();
+	endmodule
+
+	module foo;
+		sub s0();
+		initial
+			assert(false);
+	endmodule
+
+	module sub;
+	endmodule
+EOT
+design -save print
+hierarchy -top top
+select -assert-any top A:keep %i
+
+design -reset
+design -load print
+hierarchy -nokeep_asserts -top top
+select -assert-none top A:keep %i

tests/various/hierarchy_recursive.v

@@ -0,0 +1,3 @@
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+endmodule

tests/various/hierarchy_recursive.ys

@@ -0,0 +1,6 @@
+read_verilog <<EOT
+module top(input x, output y);
+top top_i(.x(x), .y(y));
+endmodule
+EOT
+hierarchy