Stefan Frederik e14c8b9a11 wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names		2022-10-12 16:36:56 +02:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names	2022-10-12 16:36:56 +02:00
examples	wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names	2022-10-12 16:36:56 +02:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins	2022-10-11 13:12:17 +02:00
ngspice	removed (now) duplicated inst_hash_lookup: use int_hash_lookup. Search function does not highlight nets if searching for something that is not "lab"	2022-10-12 13:14:48 +02:00
pcb	tedax example	2022-01-11 14:44:19 +01:00
rom8k	better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.	2022-09-21 17:24:16 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
viewdraw_import	add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing	2022-01-15 13:31:45 +01:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	added missing symbols	2021-12-19 01:32:19 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00