Stefan Frederik 95095e97d0 add delays in logic/test_mos_verilog.sch		2021-11-21 01:45:16 +01:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	fix depletion mos example	2021-11-21 01:18:12 +01:00
examples	added test_mos_verilog.sym example in top schematic page	2021-11-21 00:53:37 +01:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	add delays in logic/test_mos_verilog.sch	2021-11-21 01:45:16 +01:00
ngspice	auditing of static in-function variables, remove unnecessary, add notes for allowed ones	2021-11-20 02:37:56 +01:00
pcb	"propagate_to" attribute for pins renamed to "goto"	2020-12-30 21:26:58 +01:00
rom8k	added hierarchical ps/pdf export (File menu)	2021-06-13 23:55:17 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	Escape key (instead of Simulation menu entry, now removed) stops ongoing xschem internal simulator engine if running	2021-11-04 23:52:24 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00