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add delays in logic/test_mos_verilog.sch

This commit is contained in:
Stefan Frederik 2021-11-21 01:45:16 +01:00
parent 0e91351e4a
commit 95095e97d0
1 changed files with 2 additions and 2 deletions
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4
xschem_library/logic/test_mos_verilog.sch
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@ -21,8 +21,8 @@ N 390 -220 450 -220 { lab=IN}
N 490 -300 610 -300 { lab=OUT}
N 450 -380 450 -340 { lab=OUT}
N 450 -340 490 -340 { lab=OUT}
C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1}
C {nmos4_depl.sym} 470 -380 0 0 {name=M3 model=nmos w=5u l=0.18u m=1}
C {nmos4.sym} 470 -220 0 0 {name=M1 model=nmos w=5u l=0.18u m=1 del=10}
C {nmos4_depl.sym} 470 -380 0 0 {name=M3 model=nmos w=5u l=0.18u m=1 del=10}
C {gnd.sym} 550 -380 0 0 {name=l1 lab=GND}
C {gnd.sym} 550 -220 0 0 {name=l2 lab=GND}
C {gnd.sym} 490 -150 0 0 {name=l3 lab=GND value=0}