Stefan Frederik 4e8e4cea20 poweramp.sch fixes in sim commands		2021-07-13 18:37:01 +02:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	bus_connect_nolab.sym type set to "show_label" so it will be highlighted when net is highlighted, without needing to set "auto-highlight nets/pins".	2021-02-10 00:49:46 +01:00
examples	poweramp.sch fixes in sim commands	2021-07-13 18:37:01 +02:00
gschem_import	populating xschem git repo	2020-08-08 15:47:34 +02:00
logic	fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion	2020-12-23 18:16:53 +01:00
ngspice	Joanne fixes for potential crash in align_sch_pins_with_sym() if there is a sym/sch pin number mismatch. Moved box declaration to beginning of scope block for C89 compatibility	2021-03-07 00:15:16 +01:00
pcb	"propagate_to" attribute for pins renamed to "goto"	2020-12-30 21:26:58 +01:00
rom8k	added hierarchical ps/pdf export (File menu)	2021-06-13 23:55:17 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	new_wire(): update connecting bubbles when inserting new wires and no one is highlighted	2021-01-19 13:32:45 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00