Stefan Frederik 4f1d84054f update test schematic (better screen redraw if moving while simulating)		2022-10-27 10:09:19 +02:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)	2022-10-24 17:28:39 +02:00
examples	eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)	2022-10-24 17:28:39 +02:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates.	2022-10-20 20:25:49 +02:00
ngspice	example solar_panel.sch update	2022-10-19 23:59:11 +02:00
pcb	test schematics update	2022-10-21 11:28:17 +02:00
rom8k	better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.	2022-09-21 17:24:16 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
viewdraw_import	add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing	2022-01-15 13:31:45 +01:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	update test schematic (better screen redraw if moving while simulating)	2022-10-27 10:09:19 +02:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00