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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 5fb452f37f Further hardening of source_user_tcl_files against files containing strange characters including ". 2022-10-27 19:32:46 +02:00
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tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library update test schematic (better screen redraw if moving while simulating) 2022-10-27 10:09:19 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions