stefan schippers d56e3939d5 updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol		2023-06-08 01:08:05 +02:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting	2023-06-07 03:41:49 +02:00
examples	updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol	2023-06-08 01:08:05 +02:00
generators	update generators/res.tcl	2023-06-07 10:17:02 +02:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
inst_sch_select	fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net	2023-05-27 11:20:49 +02:00
logic	update test_ngspice.sch example circuit	2023-03-09 20:44:51 +01:00
ngspice	reverted solar_panel.sch (was changed for testing)	2023-06-07 03:44:42 +02:00
pcb	test schematics update	2022-10-21 11:28:17 +02:00
rom8k	fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net	2023-05-27 11:20:49 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
viewdraw_import	add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing	2022-01-15 13:31:45 +01:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	update test schematic (better screen redraw if moving while simulating)	2022-10-27 10:09:19 +02:00
Makefile	update xschem_library/Makefile to include generators in install	2023-05-06 09:04:06 +02:00