Stefan Frederik 551bbcec0c Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f		2021-11-26 13:16:52 +01:00
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binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.	2021-11-25 04:00:01 +01:00
examples	avoid force-saving changed schematic before doing netlist (use push/pop undo instead of load_schematic() to restore circuit after traversing hierarchy)	2021-11-21 23:04:48 +01:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	fix descend_symbol regression due to previous commit	2021-11-22 00:42:53 +01:00
ngspice	auditing of static in-function variables, remove unnecessary, add notes for allowed ones	2021-11-20 02:37:56 +01:00
pcb	Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f	2021-11-26 13:16:52 +01:00
rom8k	added hierarchical ps/pdf export (File menu)	2021-06-13 23:55:17 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	Escape key (instead of Simulation menu entry, now removed) stops ongoing xschem internal simulator engine if running	2021-11-04 23:52:24 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00