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xschem
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fix descend_symbol regression due to previous commit

This commit is contained in:
Stefan Frederik 2021-11-22 00:42:53 +01:00
parent 1c37e7eeee
commit 9bca5b3f5b
3 changed files with 17 additions and 2 deletions
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1
src/actions.c
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@ -1062,6 +1062,7 @@ void descend_schematic(int instnumber)
* -1 : user cancel
* 0 : file not saved due to errors or per user request
*/
dbg(0, "ret=%d\n", ret);
if(ret == 0) clear_all_hilights();
if(ret == -1) return; /* user cancel */
}

17
src/save.c
View File

@ -2341,8 +2341,21 @@ void descend_symbol(void)
rebuild_selected_array();
if(xctx->lastsel > 1) return;
if(xctx->lastsel==1 && xctx->sel_array[0].type==ELEMENT) {
if(xctx->modified) {
if(save(1)) return;
if(xctx->modified)
{
int ret;
ret = save(1);
/* if circuit is changed but not saved before descending
* state will be inconsistent when returning, can not propagare hilights
* save() return value:
* 1 : file saved
* -1 : user cancel
* 0 : file not saved due to errors or per user request
*/
dbg(0, "ret=%d\n", ret);
if(ret == 0) clear_all_hilights();
if(ret == -1) return; /* user cancel */
}
my_snprintf(name, S(name), "%s", xctx->inst[xctx->sel_array[0].n].name);
/* dont allow descend in the default missing symbol */

1
xschem_library/logic/test_mos_verilog.sch
View File

@ -66,3 +66,4 @@ C {lab_pin.sym} 550 -230 0 0 {name=l11 sig_type=std_logic lab=IN verilog_type=re
C {lab_pin.sym} 720 -310 0 1 {name=l12 sig_type=std_logic lab=OUT2}
C {pmos4.sym} 630 -390 0 0 {name=M4 model=pmos w=5u l=0.18u m=1}
C {vdd.sym} 710 -390 0 0 {name=l13 lab=VDD value=1}
C {noconn.sym} 300 -230 1 0 {name=l14}