stefan schippers
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f9610851e8
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cleanup exit procedures: tcl exit command will cleanly delete additional tabs/windows data structures before closing
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2023-06-03 11:37:37 +02:00 |
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stefan schippers
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6e2754020b
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added function swap_tabs() (wip)
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2023-06-03 09:37:43 +02:00 |
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stefan schippers
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0244dc5e69
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add command xschem tab_list, returns window pathname and associated filename loaded
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2023-06-03 00:21:55 +02:00 |
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stefan schippers
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1ea1e835ae
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@spice_get_voltage: do not process if net is a multiple bit bundle
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2023-06-02 08:10:47 +02:00 |
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stefan schippers
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0d44c0ce13
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fix wrong pin label net gathering in translate()
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2023-06-02 07:48:09 +02:00 |
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Stefan Schippers
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f5c592c889
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xschem resolved_net command: add [net] parameter; instcheck(): use inst[].lab instead of get_tok_value(inst[].prop_ptr, "lab",0)
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2023-06-01 18:00:47 +02:00 |
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Stefan Schippers
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f3f12da486
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updated test_extracted_netlist.sch example
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2023-06-01 16:02:40 +02:00 |
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stefan schippers
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60a6a76ac2
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update test_extracted_netlist.sch
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2023-06-01 11:36:47 +02:00 |
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stefan schippers
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d68e25016b
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fix long standing bug: redundant grammar rule in expandlabel.y causing it to fail recognizing nodes like GND*16
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2023-06-01 07:09:43 +02:00 |
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stefan schippers
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e948edbffa
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descend_schematic(): vectorize #netxxx nets if connected to bussed pins, before hashing, so resolved_net(...) will return the correct net portmapping
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2023-06-01 06:40:24 +02:00 |
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stefan schippers
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e9c8569800
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remove debug mesg
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2023-05-31 10:25:54 +02:00 |
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stefan schippers
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39f2747149
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fix some errors found by Joanne in test_bus_tap.sch
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2023-05-31 00:14:22 +02:00 |
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stefan schippers
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5085301cd7
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add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps
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2023-05-30 11:03:07 +02:00 |
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stefan schippers
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4a06176f0d
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comments, more test_bus_tap examples
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2023-05-29 16:48:13 +02:00 |
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stefan schippers
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487b1eb202
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more flexible bus_tap syntax
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2023-05-29 09:17:06 +02:00 |
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stefan schippers
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06d8a548d3
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fix expandlabel.y (remove excess rules)
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2023-05-29 07:41:53 +02:00 |
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stefan schippers
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6bbc60f8fb
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add more ".." bus notations: XX[4,2,8..1..3,12,23] and others. bus_tap.sym: if no "[n]" pattern is given assume it is the complete name of the slice (does not need bus basename)
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2023-05-28 15:30:40 +02:00 |
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stefan schippers
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620217788f
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do not process @#n:resolved_net attributes if net_name=true not set on symbol or instance and option "show netnames on symbol pins/floaters" is not enabled
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2023-05-28 08:13:01 +02:00 |
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stefan schippers
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5043b14921
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fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats
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2023-05-27 23:36:10 +02:00 |
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Stefan Schippers
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cff9f7d169
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some bug fixes in resolved_net hashing, use some @#n:resolved_net labels in examples
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2023-05-27 21:48:21 +02:00 |
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stefan schippers
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bb9ad82d80
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fix memory leak when using new resolved_net() fn
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2023-05-27 14:13:50 +02:00 |
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stefan schippers
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cf61c253c5
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fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net
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2023-05-27 11:20:49 +02:00 |
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stefan schippers
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09a373954f
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initial implementation of portmap feature: from sub-schematics resolve hierarchic name of schematic nets connected to I/O pins (go to the upper level recursively until resolved)
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2023-05-26 11:56:52 +02:00 |
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stefan schippers
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970c8597f6
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First version: create_alloc_ids_windows.awk can be used with Windows GNU GAWK by running Windows batch file create_alloc_ids_windows.bat. It`s the equivalent to linux version of create_alloc_ids.awk.
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2023-05-25 21:56:55 +02:00 |
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stefan schippers
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c3d7780150
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updated test_bus_tap.sch with more bus tapping cases
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2023-05-25 09:51:17 +02:00 |
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Stefan Schippers
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b5b1339653
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enable rainbow colored graphs also for double dc sweeps
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2023-05-24 19:31:47 +02:00 |
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Stefan Schippers
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ba402e65c0
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remove unneeded variable in create_new_tab()
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2023-05-24 18:20:18 +02:00 |
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stefan schippers
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d3b99d3a76
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update n and p jfets, added pjfet simulation
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2023-05-24 10:02:26 +02:00 |
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stefan schippers
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5e90f5c319
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use find_file_first instead of find_file in C code
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2023-05-24 09:12:29 +02:00 |
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stefan schippers
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694bc631a0
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redraw schematic when switching netlisting mode (Shift-V) to redraw disabled/enabled components for the new netlisting mode; The Properties->Toggle *_ignore... menu will do nothing if in symbol netlisting mode
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2023-05-24 09:08:57 +02:00 |
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stefan schippers
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608a144dd1
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fix tcl procedures using find_file to find a component: use find_file_first (return 1st match) , since find_file may return multiple matches; add njfet.sym, pjfet.sym and test_jfet.sch
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2023-05-24 08:43:05 +02:00 |
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stefan schippers
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d993292f0f
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fix unindented lines
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2023-05-23 10:16:38 +02:00 |
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stefan schippers
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e7366741ed
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allow @#n:pin_attr or @#pin_name:pin_attr in verilog and vhdl format string (print_vhdl_primitive, print_verilog_primitive), in addition to @#n (convergence to translate()
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2023-05-23 09:58:28 +02:00 |
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stefan schippers
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bd41fdadc7
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fix typo in docs
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2023-05-23 09:17:28 +02:00 |
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stefan schippers
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32460f33c9
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improved "xschem display_hilights [nets|instances]" that displays highlight nets or instaces or both,with full hierarchy path, not including uninteresting net/pin/net_show elements.
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2023-05-23 09:10:01 +02:00 |
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Stefan Schippers
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1774ff4e3a
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allow @#n:pin_attr or @#pin_name:pin_attr in spice format string (print_spice_element), in addition to @#n (convergence to translate()
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2023-05-22 21:50:14 +02:00 |
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stefan schippers
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0f1bbd24c8
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devices/bus_tap.sym: remove format attr in symbol
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2023-05-22 11:52:51 +02:00 |
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stefan schippers
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ade1aaf858
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(3) update examples/test_bus_tap.sch
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2023-05-22 08:51:23 +02:00 |
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stefan schippers
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6de12e5a0f
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(2) update examples/test_bus_tap.sch
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2023-05-22 08:09:42 +02:00 |
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stefan schippers
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8f63560737
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examples/test_bus_tap.sch: auto set show_pin_net_names=1
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2023-05-22 08:05:37 +02:00 |
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stefan schippers
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637ada331e
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remove dbg message
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2023-05-22 07:46:36 +02:00 |
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stefan schippers
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9715cf4a5c
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update examples/test_bus_tap.sch
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2023-05-22 07:45:23 +02:00 |
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stefan schippers
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b68dd8c099
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when a bus label is edited correctly propagate list of instances to be redrawn if show net names on components is enabled (ie: propagate thru bus taps)
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2023-05-22 07:28:12 +02:00 |
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stefan schippers
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a4d5ddb63f
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add examples/test_bus_tap.sch
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2023-05-22 00:49:54 +02:00 |
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stefan schippers
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5bd2c624a8
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fixed regression: editing global attributes did not trigger modified status
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2023-05-22 00:20:55 +02:00 |
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stefan schippers
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ea533bd9e3
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added bus_tap.sym
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2023-05-21 23:59:50 +02:00 |
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stefan schippers
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140aba3449
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added handling of bus_tap.sym (wip)
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2023-05-21 23:58:17 +02:00 |
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stefan schippers
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313f5898eb
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add guards against freee of null pointers in name_nodes_of_pins_labels_and_propagate()
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2023-05-21 13:47:05 +02:00 |
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stefan schippers
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5c22d26072
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update copyright info to 2023
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2023-05-21 12:52:19 +02:00 |
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stefan schippers
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893389b01d
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hier_psprint_mtime(): fix wrong mtime calculation for (non existent file) generators
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2023-05-21 09:25:19 +02:00 |