stefan schippers
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f110e817ef
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ammeter.sym type set to "ammeter" instead of "probe", so will be greyed out if *_ignore attr is set
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2023-05-11 00:47:59 +02:00 |
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stefan schippers
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339c523f0b
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align symbol types, reducing number of different types (remove ngprobe, current_probe, differential_probe, raw_data_show --> probe
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2023-05-10 17:46:16 +02:00 |
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stefan schippers
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0a4f942fb7
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symbol_ignore=true attribute can be set on all symbol elements (text, lines, rectangles, arcs, polys, instances, nets) such that these marked elements are not displayed when symbol is instantiated.
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2023-05-09 23:26:46 +02:00 |
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stefan schippers
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6b857f7b7d
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switch_ngspice.sym: show (in very small font) @device_model (if given)
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2023-04-30 10:37:45 +02:00 |
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stefan schippers
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fc18a69109
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ind.sym artwork
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2023-04-28 11:23:06 +02:00 |
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stefan schippers
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01bc76955e
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fix simulator_commands_shown.sym (wrong and incompete quoting)
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2023-02-13 19:15:35 +01:00 |
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stefan schippers
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e5227d6a31
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rename top_subckt to lvs_netlist (more appropriate), better tcp interface (redirect stdout to socket in addition to command return value)
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2023-02-09 11:30:27 +01:00 |
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stefan schippers
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af22c256b3
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default to unlocked state (lock=false) at title 1st placement
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2023-01-07 11:34:47 +01:00 |
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stefan schippers
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4c0d5023f5
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allow 0 width lines (faster device dependent implementation) if user defined line width is set (to 0), add devices/title-3.sym
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2023-01-07 11:28:28 +01:00 |
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stefan schippers
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19757ddd8a
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add menu properties -> Edit header/License text, to allow inserting header or license metadata into the sch/sym file.
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2023-01-02 03:04:35 +01:00 |
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stefan schippers
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609033e7ca
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fix regression (not allowing to change text size)
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2022-11-23 16:57:21 +01:00 |
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Stefan Schippers
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e7851d01db
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"xschem set format <fmt_attribute>" will change netlisting format attribute instead of default "format" (or verilog_format or vhdl_format), however fallback to default netlisting rule attribute if not defined in symbol. add tcl function "from_eng <n>" to convert spice formatted numbers to floating point
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2022-11-23 16:16:38 +01:00 |
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Stefan Frederik
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3d49ca63c9
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avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
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2022-11-04 13:35:06 +01:00 |
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Stefan Frederik
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b98d836be3
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devices/simulator_commands.sym: avoid recursive @param substitution in spice commands
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2022-11-03 11:00:15 +01:00 |
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Stefan Frederik
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b36cd99e01
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update simulator_commands.sym (missing close parenthesis at end, not causing any problem though)
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2022-11-02 23:11:23 +01:00 |
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Stefan Frederik
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666b0ebd5b
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show @path in title.sym
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2022-11-01 13:26:22 +01:00 |
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Stefan Frederik
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b1f011f933
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clean up testing @path in symbols
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2022-11-01 13:17:51 +01:00 |
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Stefan Frederik
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b0a88325e7
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"@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name
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2022-11-01 12:54:43 +01:00 |
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Stefan Frederik
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4c43e77818
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eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)
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2022-10-24 17:28:39 +02:00 |
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Stefan Frederik
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18044abb3e
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iopin.sym micro edit
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2022-10-24 17:06:54 +02:00 |
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Stefan Frederik
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b8732f2321
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ipin,iopin,opin reshaped to better show connection hotspot
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2022-10-19 10:37:43 +02:00 |
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Stefan Frederik
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e14c8b9a11
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wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names
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2022-10-12 16:36:56 +02:00 |
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Stefan Frederik
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314acbabda
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allow tabs and newlines in graph expressions in addition to spaces; updated example schematics
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2022-09-23 02:18:51 +02:00 |
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Stefan Frederik
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3e2bc9f95e
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added "Annotate operating point" into Simulation menu
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2022-09-22 19:47:25 +02:00 |
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Stefan Frederik
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e61ef2eabf
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fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes.
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2022-09-22 17:35:14 +02:00 |
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Stefan Frederik
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6f907b5430
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updated test schematics to use new xschem annotate_op instead of ngspice::annotate
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2022-09-21 18:38:53 +02:00 |
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Stefan Frederik
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9c89a08111
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better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.
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2022-09-21 17:24:16 +02:00 |
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Stefan Frederik
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931c1520e3
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make op backannotation in schematic work also if raw file loaded at hierarchy level > 0
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2022-09-21 13:58:01 +02:00 |
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Stefan Frederik
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b542186ebd
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updated example schematics to new annotate / raw file loading methods
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2022-09-20 18:25:31 +02:00 |
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Stefan Frederik
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8169196b35
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bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph
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2022-09-20 03:12:46 +02:00 |
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Stefan Frederik
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7abceb3344
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fix regression in ngspice::get_current, simplified voltage reporting in net label symbols
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2022-09-20 00:12:27 +02:00 |
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Stefan Frederik
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53dc7fe3bf
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add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model.
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2022-09-19 11:22:04 +02:00 |
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Stefan Frederik
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3a10b39299
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fixed current (also hierarchic) reporting in ammeter.sym and vsource.sym)
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2022-09-19 09:45:35 +02:00 |
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Stefan Frederik
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96f80d1d33
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Alt-a in graph annotates schematic with values at cursor b position. Simulation->Live annotate option to automatically update schematic probes if cursor moved. Some improvements and fixes in ngspice_annotate.tcl. Fix xschem setprobe command. Added missing housekeeping_ctx when a new tab is created. housekeeping_ctx: added more variables to sync.
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2022-09-18 05:29:16 +02:00 |
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Stefan Frederik
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d0b02724cf
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simpler ngspice_probe.sym
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2022-09-13 01:33:09 +02:00 |
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Stefan Frederik
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907315191d
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added "devices/simulator_commands*.sym" to conditionally include commands in the netlist depending on selected target simulator
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2022-09-09 13:06:11 +02:00 |
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Stefan Frederik
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5da8f777b2
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monospaced font in code_shown.sym
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2022-08-30 15:54:18 +02:00 |
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Stefan Frederik
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ce4bd4837a
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changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch)
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2022-08-10 08:38:49 +02:00 |
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Stefan Frederik
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aa63f0adab
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add devices/res3.sym for generic semiconductor resistance. User must provide a 3-terminal subcircuit for this
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2022-07-29 09:40:17 +02:00 |
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Stefan Frederik
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28cc187b56
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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Stefan Frederik
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eff273dd08
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fix in spice.awk: do not clobber user or device format generated .save lines (no ?n tag); add devices/device_param_probe.sym
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2022-04-30 10:58:15 +02:00 |
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Stefan Frederik
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a2b0718a7a
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added some symbols
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2022-04-10 09:05:17 +02:00 |
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Stefan Frederik
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77be19bc6a
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ind.sym artwork
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2022-02-21 00:20:21 +01:00 |
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Stefan Frederik
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2e8bd72faf
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reverted xcb since text quality is slightly better
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2022-01-18 03:37:54 +01:00 |
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Stefan Frederik
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19398e8162
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update window title/icon title when switching in tabbed interface
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2022-01-10 03:00:33 +01:00 |
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Stefan Frederik
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756a7ba06d
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swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .
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2021-12-01 15:53:14 +01:00 |
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Stefan Frederik
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dcb37ef295
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added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example
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2021-12-01 14:25:27 +01:00 |
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Stefan Frederik
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39a27e856e
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fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.
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2021-11-25 04:00:01 +01:00 |
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Stefan Frederik
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7f9ee9fc2a
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add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym
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2021-11-21 12:28:36 +01:00 |
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Stefan Frederik
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0e91351e4a
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fix depletion mos example
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2021-11-21 01:18:12 +01:00 |