schippes
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0d2738254a
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added verilogprefix symbol attribute: will be prefixed to symbol name references in verilog netlists
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2022-11-22 16:30:59 +01:00 |
Stefan Frederik
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3d49ca63c9
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avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
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2022-11-04 13:35:06 +01:00 |
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Stefan Frederik
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4bb321af68
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add @path attribute for spice/verilog/vhdl/tedax backends
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2022-11-02 00:47:59 +01:00 |
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Stefan Frederik
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fe0dc46c81
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remove debug msgs
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2022-11-01 12:57:29 +01:00 |
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Stefan Frederik
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b0a88325e7
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"@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name
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2022-11-01 12:54:43 +01:00 |
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Stefan Frederik
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cb652adb5f
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skip NULL or empty texts in draw_symbol, translate2() skip @@... and @#... tokens (return empty)
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2022-10-21 17:48:54 +02:00 |
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Stefan Frederik
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a6dc3d47c3
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cache embed attribute of instances for faster lookup
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2022-10-21 11:04:20 +02:00 |
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Stefan Frederik
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e34211368f
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translate2() fix recursive param substitution
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2022-10-20 23:31:02 +02:00 |
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Stefan Frederik
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0f25befe31
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recursive attribute substitution. use also template attribute of parents if not found in instance prop_ptr
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2022-10-20 10:30:48 +02:00 |
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Stefan Frederik
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f6207070d0
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translate() --> @spice_get_current(): find last hier.separator occurrentce with strrchr()
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2022-10-16 23:57:07 +02:00 |
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Stefan Frederik
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e8b2385f24
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update xschemtest hashes, uniquify allocation IDs
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2022-10-16 14:21:22 +02:00 |
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Stefan Frederik
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91ba5fd1d3
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annotation of voltage and currents in (nested) LCC instances
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2022-10-16 13:08:52 +02:00 |
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Stefan Frederik
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0e6c35f598
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translate2(): return @spice_get_voltage* strings unchanged; get rid of "@#..." tokens in translate2 (return empty)
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2022-10-15 22:50:18 +02:00 |
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Stefan Frederik
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3adb192936
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@spice_get_voltage(net) error checking
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2022-10-15 10:52:07 +02:00 |
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Stefan Frederik
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56b63df2fc
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added @spice_get_voltage(net) recognize in translate() for voltage value update inside LCC schematics
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2022-10-15 10:08:58 +02:00 |
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Stefan Frederik
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adf477fbcc
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optimization in translate(): @spice_get_voltage will use the "lab" attribute (if existing) to build up the net name to look up in raw file, before reverting to a call to net_name() to get the net from the attached net
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2022-10-15 08:55:32 +02:00 |
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Stefan Frederik
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a820cc2e3f
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removed (now) duplicated inst_hash_lookup: use int_hash_lookup. Search function does not highlight nets if searching for something that is not "lab"
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2022-10-12 13:14:48 +02:00 |
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Stefan Frederik
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7a1fbb4809
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better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed.
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2022-10-12 11:56:02 +02:00 |
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Stefan Frederik
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7d016eab28
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small netlist syntax fix in token.c (correctly skip VHDL time attributes), tedax backend: avoid printing mapping comments for duplicated pins
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2022-10-12 09:32:37 +02:00 |
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Stefan Frederik
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3f627123b2
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persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
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2022-10-11 13:12:17 +02:00 |
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Stefan Frederik
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150c2663b9
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added netlist_options as list of symbols not to load in schematics-as-symbol instances, load_file_dialog: make remember last dir work again
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2022-10-09 23:49:28 +02:00 |
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Stefan Frederik
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c5e91f209e
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allow to use @pinlist in format string even for symbols with duplicated ports. Duplicated entries will be skipped. Add component_browser_on_top tcl variable in xschemrc (default setting: enabled (1) to enable or disable component browser window always on top
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2022-10-05 16:47:34 +02:00 |
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Stefan Frederik
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5fe2f1586b
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refactor str_hash_* and int_hash_* functions
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2022-10-05 01:18:45 +02:00 |
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Stefan Frederik
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06fc742e60
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doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne)
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2022-10-04 00:37:09 +02:00 |
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Stefan Frederik
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64d947a9dd
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fix extra and verilog_extra handling in instance lines (verilog netlists)
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2022-10-03 09:10:58 +02:00 |
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Stefan Frederik
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d174306880
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added verilog_extra attribute for list of implicit node connections to symbol in verilog netlists. extra attribute still used in verilog as a list of attributes NOT use as component attributes / symbol parameters.
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2022-10-03 01:20:33 +02:00 |
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Stefan Frederik
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28c644fba7
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doc updates (new graph functions)
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2022-10-02 20:52:17 +02:00 |
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Stefan Frederik
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db94f9fb25
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@pinlist will be comma separated in verilog netlists
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2022-10-01 09:46:58 +02:00 |
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Stefan Frederik
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b7c7c336dd
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added vhdl_sym_def, spice_sym_def, verilog_sym_def attributes for symbols. If defined and not empty the corresponding netlister will insert the content of the attribute instead of the subcircuit schematic implementation. Typically used to include a definition file. Updated documentation
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2022-09-29 11:59:43 +02:00 |
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Stefan Frederik
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ae4b74f2d8
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graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form.
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2022-09-28 19:14:31 +02:00 |
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Stefan Frederik
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9dc1fde024
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remove dbg messages
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2022-09-22 17:40:36 +02:00 |
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Stefan Frederik
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e61ef2eabf
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fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes.
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2022-09-22 17:35:14 +02:00 |
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Stefan Frederik
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9c89a08111
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better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.
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2022-09-21 17:24:16 +02:00 |
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Stefan Frederik
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931c1520e3
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make op backannotation in schematic work also if raw file loaded at hierarchy level > 0
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2022-09-21 13:58:01 +02:00 |
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Stefan Frederik
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e67ff344c8
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cleanup/rename some xctx variables and graph-related functions, avoid drawing graphs using data file loaded from from schematics that are unmatched with current schematic or up in the hierarchy levels
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2022-09-21 11:25:45 +02:00 |
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Stefan Frederik
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8169196b35
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bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph
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2022-09-20 03:12:46 +02:00 |
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Stefan Frederik
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7abceb3344
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fix regression in ngspice::get_current, simplified voltage reporting in net label symbols
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2022-09-20 00:12:27 +02:00 |
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Stefan Frederik
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e2846daca5
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inst_hash_lookup() will insert and lookup only instance basename (x1[3:0] --> x1) so better and stronger uniquenes of instance names is ensured. ngspice_backannotate accepts a filename (if not given assume as before <circuit_name>.raw)
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2022-09-12 12:01:26 +02:00 |
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Stefan Frederik
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f78fc5494d
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set_text_custom_font xctx->cairo_ctx can be NULL when netlisting without X with 0_examples_top.sch; net_name(..) doesnt work on duplicate pin for test_doublepin.sch so added back the condition in rev 2243; added HAS_CAIRO directive to compile on Windows that dont have CAIRO turned on.
remove some old unused variables
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2022-09-08 20:58:12 +02:00 |
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Stefan Frederik
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ae1bed65f4
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added [t]rack bindkey in graph to display the wave closest to mouse in multiple dataset plots
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2022-09-02 17:11:50 +02:00 |
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Stefan Frederik
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e7c4111f8e
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simplified print_tedax_subckt, some optimizations in netlisting code (avoid some strdups)
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2022-09-01 17:25:25 +02:00 |
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Stefan Frederik
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77d76e1a8f
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add commands "xschem set format ..." and "xschem get format" to change format attribute used for netlisting, overriding defaults
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2022-08-31 10:47:16 +02:00 |
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Stefan Frederik
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adc4eb96c8
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fix net_name() crashing if inst[i].node==NULL. This may happen when pasting a component that contains a @@xxx token, that needs to be expanded to attached netname, however since we are moving the component no net name is defined --> .node==NULL.
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2022-08-30 02:44:28 +02:00 |
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Stefan Frederik
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5100803673
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translate() optimization
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2022-08-26 09:20:30 +02:00 |
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Stefan Frederik
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dffc266e0d
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improve test_backannotated_subckt.sch example, remove dbg messages
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2022-08-23 10:44:00 +02:00 |
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Stefan Frederik
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0f5881cd61
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print_spice_subckt(): check for tcl_hook2() errors, check for NULL in strtoupper/strtolower, fix unitialized local variable
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2022-08-23 10:01:32 +02:00 |
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Stefan Frederik
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20d1080171
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improve uniqueness name checking (do not consider non netlist elements, like pins, title, etc)
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2022-08-21 11:55:34 +02:00 |
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Stefan Frederik
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ef2e059c59
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instance names (refdes) are hashed as uppercase, so collision check will be case insensitive, if enabled
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2022-08-21 10:22:56 +02:00 |
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Stefan Frederik
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2502208671
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if a subcircuit has spiceprefix set in template string do not consider it as an attribute to dump in netlist as a subckt parameter (.subckt xxxx A B C spiceprefix=X)
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2022-08-20 11:23:18 +02:00 |
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Stefan Frederik
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c1d229b917
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better str_replace() implementation
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2022-08-18 10:21:14 +02:00 |