Version bump

VN_AS should be used over VN_CAST in code where the author knows up
front (i.e.: statically) what the true type of the node is. This has
multiple benefits over VN_CAST:
- In the debug build: Asserts node type is as expected
- In the optimized build: It is faster as no superfluous type test
- And (I would argue most importantly) it documents intent in the code

No current instances of VN_CAST changed in this patch

.clang-format

@@ -20,7 +20,7 @@ AlwaysBreakBeforeMultilineStrings: false
 AlwaysBreakTemplateDeclarations: false
 BinPackArguments: true
 BinPackParameters: true
-BraceWrapping:   
+BraceWrapping:
   AfterClass:      false
   AfterControlStatement: false
   AfterEnum:       false
@@ -55,12 +55,12 @@ DerivePointerAlignment: false
 DisableFormat:   false
 ExperimentalAutoDetectBinPacking: false
 FixNamespaceComments: true
-ForEachMacros:   
+ForEachMacros:
   - foreach
   - Q_FOREACH
   - BOOST_FOREACH
 IncludeBlocks:   Preserve
-IncludeCategories: 
+IncludeCategories:
   - Regex:           '^"(llvm|llvm-c|clang|clang-c)/'
     Priority:        2
   - Regex:           '^(<|"(gtest|gmock|isl|json)/)'
@@ -104,8 +104,7 @@ SpacesInContainerLiterals: true
 SpacesInCStyleCastParentheses: false
 SpacesInParentheses: false
 SpacesInSquareBrackets: false
-Standard:        Cpp03
+Standard:        Cpp11
 TabWidth:        8
 UseTab:          Never
 ...
-

.clang-tidy

@@ -1,4 +1,4 @@
-Checks:          'clang-diagnostic-*,clang-analyzer-*,*,-modernize*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-default-arguments,-fuchsia-overloaded-operator,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance'
+Checks:          '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance'
 WarningsAsErrors: ''
 HeaderFilterRegex: ''
 FormatStyle:     none

.gitattributes

@@ -1,4 +1,5 @@
 *.v linguist-language=SystemVerilog
 *.vh linguist-language=SystemVerilog
 *.sv linguist-language=SystemVerilog
+Changes linguist-language=reStructuredText
 nodist linguist-detectable=false

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,6 +1,6 @@
 ---
 name: Bug report
-about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''

.github/ISSUE_TEMPLATE/feature.md

@@ -1,6 +1,6 @@
 ---
 name: Feature Request
-about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''

.github/ISSUE_TEMPLATE/questions.md

@@ -1,6 +1,6 @@
 ---
 name: Q and A, or Other
-about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''

.github/PULL_REQUEST_TEMPLATE.md

@@ -1 +1 @@
-We appreciate your contributing to Verilator.  If this is your first commit, please add your name to docs/CONTRIBUTORS, and read our contributing guidelines in docs/CONTRIBUTING.adoc.
+We appreciate your contributing to Verilator.  If this is your first commit, please add your name to docs/CONTRIBUTORS, and read our contributing guidelines in docs/CONTRIBUTING.rst.

.github/workflows/build.yml

@@ -0,0 +1,144 @@
+# DESCRIPTION: Github actions config
+# This name is key to badges in README.rst, so we use the name build
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: build
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+  - cron: '0 0 * * 0' # weekly
+
+env:
+  CI_OS_NAME: linux
+  CI_COMMIT: ${{ github.sha }}
+  CCACHE_COMPRESS: 1
+  CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CCACHE_LIMIT_MULTIPLE: 0.95
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
+
+jobs:
+
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [ubuntu-20.04, ubuntu-18.04]
+        compiler:
+          - { cc: clang, cxx: clang++ }
+          - { cc: gcc,   cxx: g++     }
+        m32: [0, 1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
+    runs-on: ${{ matrix.os }}
+    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
+    env:
+      CI_BUILD_STAGE_NAME: build
+      CI_RUNS_ON: ${{ matrix.os }}
+      CI_M32: ${{ matrix.m32 }}
+      CC: ${{ matrix.compiler.cc }}
+      CXX: ${{ matrix.compiler.cxx }}
+      CACHE_BASE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}
+      CCACHE_MAXSIZE: 250M # Per build matrix entry (2000M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
+    steps:
+
+    - name: Checkout
+      uses: actions/checkout@v2
+      with:
+        path: repo
+
+    - name: Cache $CCACHE_DIR
+      uses: actions/cache@v2
+      env:
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
+      with:
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
+
+    - name: Install packages for build
+      run: ./ci/ci-install.bash
+
+    - name: Build
+      run: ./ci/ci-script.bash
+
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
+      with:
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
+
+
+  test:
+    needs: build
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [ubuntu-20.04, ubuntu-18.04]
+        compiler:
+          - { cc: clang, cxx: clang++ }
+          - { cc: gcc,   cxx: g++     }
+        m32: [0, 1]
+        suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
+    runs-on: ${{ matrix.os }}
+    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
+    env:
+      CI_BUILD_STAGE_NAME: test
+      CI_RUNS_ON: ${{ matrix.os }}
+      CI_M32: ${{ matrix.m32 }}
+      CC: ${{ matrix.compiler.cc }}
+      CXX: ${{ matrix.compiler.cxx }}
+      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${ matrix.suite }}
+      CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
+    steps:
+
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
+      with:
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
+
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+
+    - name: Cache $CCACHE_DIR
+      uses: actions/cache@v2
+      env:
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
+      with:
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
+
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
+
+    - name: Test
+      env:
+        TESTS: ${{ matrix.suite }}
+      run: ./ci/ci-script.bash

.github/workflows/contributor.yml

@@ -0,0 +1,17 @@
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: Contributor Agreement
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  Test:
+    name: "'docs/CONTRIBUTORS' was signed"
+    runs-on: ubuntu-20.04
+    steps:
+    - uses: actions/checkout@v2
+    - run: test_regress/t/t_dist_contributors.pl

.github/workflows/coverage.yml

@@ -0,0 +1,99 @@
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: coverage
+
+on:
+  workflow_dispatch:
+  schedule:
+  - cron: '0 0 * * 0' # weekly
+
+env:
+  CI_OS_NAME: linux
+  CI_COMMIT: ${{ github.sha }}
+  CI_M32: 0
+  COVERAGE: 1
+  VERILATOR_ARCHIVE: verilator-coverage-${{ github.sha }}.tar.gz
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
+
+jobs:
+
+
+  Build:
+    runs-on: ubuntu-20.04
+    env:
+      CI_BUILD_STAGE_NAME: build
+      CI_RUNS_ON: ubuntu-20.04
+    steps:
+
+    - name: Checkout
+      uses: actions/checkout@v2
+      with:
+        path: repo
+
+    - name: Install packages for build
+      run: ./ci/ci-install.bash
+
+    - name: Build
+      run: ./ci/ci-script.bash
+
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
+      with:
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
+
+
+  Test:
+    needs: Build
+    strategy:
+      fail-fast: false
+      matrix:
+        test:
+        - vlt-
+        - vltmt-
+        num:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+        - 5
+        - 6
+        - 7
+        - 8
+        - 9
+        include:
+        - { test: dist, num: '' }
+    runs-on: ubuntu-20.04
+    name: test-${{ matrix.test }}${{ matrix.num }}
+    env:
+      CI_BUILD_STAGE_NAME: test
+      CI_RUNS_ON: ubuntu-20.04
+    steps:
+
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
+      with:
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
+
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
+
+    - name: Test
+      env:
+        TESTS: coverage-${{ matrix.test }}${{ matrix.num }}
+      run: ./ci/ci-script.bash

.github/workflows/format.yml

@@ -0,0 +1,44 @@
+# DESCRIPTION: Github actions config
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: format
+
+on:
+  push:
+  pull_request_target:
+  workflow_dispatch:
+
+jobs:
+  format:
+    runs-on: ubuntu-20.04
+    name: Ubuntu 20.04 | format
+    env:
+      CI_OS_NAME: linux
+      CI_RUNS_ON: ubuntu-20.04
+      CI_COMMIT: ${{ github.sha }}
+      CI_M32: 0
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v2
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+      - name: Install packages for build
+        env:
+          CI_BUILD_STAGE_NAME: build
+        run: |
+          bash ci/ci-install.bash &&
+          sudo apt-get install clang-format-11 yapf3 &&
+          git config --global user.email "[email protected]" &&
+          git config --global user.name "github action"
+      - name: Format code
+        run: |
+          autoconf &&
+          ./configure &&
+          make -j 2 format CLANGFORMAT=clang-format-11 &&
+          git status
+      - name: Push
+        run: |
+          if [ -n "$(git status --porcelain)" ]; then
+            git commit . -m "Apply 'make format'" &&
+            git push origin
+          fi

.gitignore

@@ -15,6 +15,8 @@
 *.tex
 *.pdf
 /Makefile
+/.ccache
+/artifact/
 README
 TAGS
 autom4te.cache
@@ -34,4 +36,6 @@ verilator_coverage_bin*
 verilator.pc
 verilator-config.cmake
 verilator-config-version.cmake
+**/__pycache__/*
+**/_build/*
 **/obj_dir/*

.travis.yml

@@ -1,148 +0,0 @@
-# DESCRIPTION: Travis-CI config
-#
-# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-version: ~> 1.0
-
-language: cpp
-
-cache:
-  directories:
-    - $HOME/.ccache
-
-env:
-  global:
-    - VERILATOR_ROOT=$TRAVIS_BUILD_DIR
-
-# The list and order of build stages
-stages:
-  - build # Build Verilator
-  - test  # Run tests
-
-# Dump info about the environment for debugging
-before_install:
-  # To dump the script that Travis itself is executing, add 'cat $0' here
-  - cd "$TRAVIS_BUILD_DIR" # Skipping the git clone in later stages requires this
-  - export CCACHE_MAXSIZE=$(ci/travis-ccache-size.bash) # Set here after the 'cd'
-  - env | sort
-  - ls -lA .
-  - ls -lA bin
-  - g++ -E -dM -c -x c++ /dev/null | sort
-  - clang++ -E -dM -c -x c++ /dev/null | sort
-
-# Install all dependencies
-install:
-  - ./ci/travis-install.bash
-
-before_script:
-  # ccache maintenance
-  - ./ci/travis-ccache-maint.bash
-  # Don't produce core dumps (esp. on FreeBSD)
-  - ulimit -c 0
-  # On Focal, set the SystemC installation location
-  - |
-    if [ "$TRAVIS_DIST" = "focal" ] && [ "$M32" != "1" ]; then
-      export SYSTEMC_INCLUDE=/usr/include
-      export SYSTEMC_LIBDIR=/usr/lib/x86_64-linux-gnu
-    fi
-  # Override compiler for M32
-  - |
-    if [ "$M32" = "1" ]; then
-      export CC="$CC -m32"
-      export CXX="$CXX -m32"
-      unset M32 # verilated.mk actually references $(M32) so unset
-    fi
-
-before_cache:
-  - ccache -s -z
-
-# All jobs run the same script
-script: ./ci/travis-script.bash
-
-# Enumerate all the jobs
-jobs:
-  include:
-    ############################################################################
-    # Jobs in the 'build' stage
-    ############################################################################
-    # GCC builds
-    - {stage: build, if: type  = cron, os: linux, dist: trusty, compiler: gcc,   workspaces: {create: {name: trusty-gcc,   paths: .}}}
-    - {stage: build, if: type  = cron, os: linux, dist: xenial, compiler: gcc,   workspaces: {create: {name: xenial-gcc,   paths: .}}}
-    - {stage: build, if: type  = cron, os: linux, dist: bionic, compiler: gcc,   workspaces: {create: {name: bionic-gcc,   paths: .}}}
-    - {stage: build,                   os: linux, dist: focal,  compiler: gcc,   workspaces: {create: {name: focal-gcc,    paths: .}}}
-    # Clang builds
-    - {stage: build, if: type  = cron, os: linux, dist: xenial, compiler: clang, workspaces: {create: {name: xenial-clang, paths: .}}}
-    - {stage: build,                   os: linux, dist: focal,  compiler: clang, workspaces: {create: {name: focal-clang,  paths: .}}}
-    # Coverage build
-    - {stage: build, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {create: {name: coverage,     paths: .}}, env: COVERAGE=1}
-    # 32-bit build
-    - {stage: build, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {create: {name: focal-gcc-m32, paths: .}}, env: M32=1}
-    # OS X build
-    - {stage: build, if: type  = cron, os: osx, osx_image: xcode11.6, compiler: clang, workspaces: {create: {name: osx-xcode11.6, paths: .}}}
-    # FreeBSD build
-    - {stage: build, if: type  = cron, os: freebsd, compiler: clang, workspaces: {create: {name: freebsd, paths: .}}}
-    ############################################################################
-    # Jobs in the 'test' stage
-    ############################################################################
-    # GCC tests
-    - {stage: test, if: type  = cron, os: linux, dist: trusty, compiler: gcc,   workspaces: {use: trusty-gcc},   git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: trusty, compiler: gcc,   workspaces: {use: trusty-gcc},   git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: trusty, compiler: gcc,   workspaces: {use: trusty-gcc},   git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: trusty, compiler: gcc,   workspaces: {use: trusty-gcc},   git: {clone: false}, env: TESTS=vltmt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: gcc,   workspaces: {use: xenial-gcc},   git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: gcc,   workspaces: {use: xenial-gcc},   git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: gcc,   workspaces: {use: xenial-gcc},   git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: gcc,   workspaces: {use: xenial-gcc},   git: {clone: false}, env: TESTS=vltmt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: bionic, compiler: gcc,   workspaces: {use: bionic-gcc},   git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: bionic, compiler: gcc,   workspaces: {use: bionic-gcc},   git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: bionic, compiler: gcc,   workspaces: {use: bionic-gcc},   git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: bionic, compiler: gcc,   workspaces: {use: bionic-gcc},   git: {clone: false}, env: TESTS=vltmt-1}
-    - {stage: test, if: type != cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc},    git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type != cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc},    git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc},    git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc},    git: {clone: false}, env: TESTS=vltmt-1}
-    # Clang tests
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: clang, workspaces: {use: xenial-clang}, git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: clang, workspaces: {use: xenial-clang}, git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: clang, workspaces: {use: xenial-clang}, git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: xenial, compiler: clang, workspaces: {use: xenial-clang}, git: {clone: false}, env: TESTS=vltmt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: clang, workspaces: {use: focal-clang},  git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: clang, workspaces: {use: focal-clang},  git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type != cron, os: linux, dist: focal,  compiler: clang, workspaces: {use: focal-clang},  git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type != cron, os: linux, dist: focal,  compiler: clang, workspaces: {use: focal-clang},  git: {clone: false}, env: TESTS=vltmt-1}
-    # Coverage tests
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-dist}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vlt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vlt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vlt-2}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vlt-3}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vltmt-0}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vltmt-1}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vltmt-2}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: coverage},     git: {clone: false}, env: TESTS=coverage-vltmt-3}
-    # 32-bit tests
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc-m32}, git: {clone: false}, env: [M32=1, TESTS=dist-vlt-0]}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc-m32}, git: {clone: false}, env: [M32=1, TESTS=dist-vlt-1]}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc-m32}, git: {clone: false}, env: [M32=1, TESTS=vltmt-0]}
-    - {stage: test, if: type  = cron, os: linux, dist: focal,  compiler: gcc,   workspaces: {use: focal-gcc-m32}, git: {clone: false}, env: [M32=1, TESTS=vltmt-1]}
-    # OS X tests
-    - {stage: test, if: type  = cron, os: osx, osx_image: xcode11.6, compiler: clang, workspaces: {use: osx-xcode11.6},  git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: osx, osx_image: xcode11.6, compiler: clang, workspaces: {use: osx-xcode11.6},  git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: osx, osx_image: xcode11.6, compiler: clang, workspaces: {use: osx-xcode11.6},  git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: osx, osx_image: xcode11.6, compiler: clang, workspaces: {use: osx-xcode11.6},  git: {clone: false}, env: TESTS=vltmt-1}
-    # FreeBSD tests
-    - {stage: test, if: type  = cron, os: freebsd, compiler: clang, workspaces: {use: freebsd}, git: {clone: false}, env: TESTS=dist-vlt-0}
-    - {stage: test, if: type  = cron, os: freebsd, compiler: clang, workspaces: {use: freebsd}, git: {clone: false}, env: TESTS=dist-vlt-1}
-    - {stage: test, if: type  = cron, os: freebsd, compiler: clang, workspaces: {use: freebsd}, git: {clone: false}, env: TESTS=vltmt-0}
-    - {stage: test, if: type  = cron, os: freebsd, compiler: clang, workspaces: {use: freebsd}, git: {clone: false}, env: TESTS=vltmt-1}
-
-notifications:
-  email:
-    if: repo = verilator/verilator
-    recipients:
-      - [email protected]
-      - [email protected]

MANIFEST.SKIP

@@ -1,69 +0,0 @@
-\.clang-format
-\.clang-tidy
-\.git/
-\.git$
-\.github/
-\.svn/
-\.(bak|old)/
-\.(bak|old)$
-\.tar\.
-.*\.tgz
-.*\.log
-\..*\.swp
-.*\.tmp
-.*\.tidy
-.*\.tex
-.*\.key
-.*\.vcd
-.*\.1
-\.codacy\.yml
-\.travis\.yml
-/build/
-/obj_dbg/
-/obj_dir/
-/obj_dist/
-/obj_iv/
-/obj_nc/
-/obj_opt/
-/obj_vcs/
-/obj_vlt/
-/obj_vltmt/
-INCA_libs/
-/cov_work/
-/logs/
-^Makefile$
-README.html
-bin/verilator_bin.*
-bin/verilator_coverage_bin.*
-docs/.*\.html$
-docs/Makefile$
-docs/clang-format.txt$
-docs/doxygen-doc/.*
-examples/xml_py/copied/
-examples/xml_py/graph.*
-src/Makefile$
-src/Makefile_obj$
-include/verilated.mk$
-test_regress/.gdbinit$
-codecov.yml
-config.cache$
-config.status$
-verilator\.log
-verilator\.tex
-verilator-config.cmake$
-verilator-config-version.cmake$
-verilator.pc$
-verilator_bin.*
-verilator_coverage_bin.*
-.vcsmx_rebuild$
-ncverilog.history
-autom4te\.cache/
-nodist/
-ci/
-/simv$
-/simv.daidir/
-/vc_hdrs.h$
-/csrc/
-obj_dir.*
-TAGS
-.*~

Makefile.in

@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -44,6 +44,7 @@
 srcdir = @srcdir@
 VPATH = @srcdir@
 HOST = @HOST@
+EXEEXT = @EXEEXT@
 
 DOXYGEN = doxygen
 INSTALL = @INSTALL@
@@ -51,10 +52,12 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@
 MAKEINFO = makeinfo
 POD2TEXT = pod2text
-POD2LATEXFIX = $(srcdir)/src/pod2latexfix
 MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs
 PERL = @PERL@
 
+# Version (for docs/guide/conf.py)
+PACKAGE_VERSION_NUMBER = @PACKAGE_VERSION_NUMBER@
+
 # Destination prefix for RPMs
 DESTDIR =
 
@@ -89,7 +92,6 @@ datarootdir = @datarootdir@
 CFG_WITH_CCWARN = @CFG_WITH_CCWARN@
 CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
 CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@
-CFG_WITH_THREADED = @CFG_WITH_THREADED@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 
 #### End of system configuration section. ####
@@ -112,92 +114,10 @@ SUBDIRS = docs src test_regress \
 	examples/make_protect_lib \
 	examples/xml_py \
 
-INFOS = verilator.txt verilator.html verilator.pdf
+INFOS = verilator.html verilator.pdf
 
 INFOS_OLD = README README.html README.pdf
 
-# Files that can be generated, but should be up to date for a distribution.
-DISTDEP = info Makefile
-
-DISTFILES_INC = $(INFOS) .gitignore \
-	*.in *.ac \
-	Artistic \
-	Changes \
-	LICENSE \
-	MANIFEST.SKIP \
-	README.adoc \
-	verilator-config.cmake.in \
-	verilator-config-version.cmake.in \
-	bin/verilator \
-	bin/verilator_coverage \
-	bin/verilator_difftree \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	docs/.gitignore \
-	docs/CONTRIBUTING.adoc \
-	docs/CONTRIBUTORS \
-	docs/Makefile.in \
-	docs/TODO \
-	docs/doxygen-mainpage \
-	docs/doxygen.config \
-	docs/install.adoc \
-	docs/internals.adoc \
-	docs/verilator_logo.png \
-	docs/xml.adoc \
-	install-sh configure *.pod \
-	include/*.[chv]* \
-	include/*.in \
-	include/.*ignore \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-	.*attributes */.*attributes  */*/.*attributes \
-	src/.*ignore src/*.in src/*.cpp src/*.[chly] \
-	src/astgen src/bisonpre src/*fix src/cppcheck_filtered \
-	src/vlcovgen src/mkinstalldirs \
-	src/.gdbinit \
-	src/*.pl src/*.pod \
-	examples/*/.*ignore examples/*/Makefile* \
-	examples/*/*.[chv]* examples/*/vl_* \
-	examples/*/CMakeLists.txt \
-	test_*/.*ignore test_*/Makefile* test_*/*.cpp \
-	test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \
-	test_regress/*.pl \
-	test_regress/Makefile \
-	test_regress/Makefile_obj \
-	test_regress/input.vc \
-	test_regress/CMakeLists.txt \
-	test_regress/t/t*/*.sv* \
-	test_regress/t/t*/*.v* \
-	test_regress/t/t*/*/*.sv* \
-	test_regress/t/t*/*/*.v* \
-	test_regress/t/*.cpp \
-	test_regress/t/*.h \
-	test_regress/t/*.dat \
-	test_regress/t/*.mem \
-	test_regress/t/*.out \
-	test_regress/t/*.pl \
-	test_regress/t/*.pf \
-	test_regress/t/*.v* \
-
-INST_PROJ_FILES = \
-	bin/verilator \
-	bin/verilator_coverage \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	include/verilated.mk \
-	include/*.[chv]* \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-
-INST_PROJ_BIN_FILES = \
-	bin/verilator_bin \
-	bin/verilator_bin_dbg \
-	bin/verilator_coverage_bin_dbg \
-
-DISTFILES := $(DISTFILES_INC)
-
 EXAMPLES_FIRST = \
 	examples/make_hello_c \
 	examples/make_hello_sc \
@@ -205,17 +125,17 @@ EXAMPLES_FIRST = \
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_gantt.1 verilator_profcfunc.1
+VL_INST_MAN_FILES = verilator.1 verilator_coverage.1
 
 default: all
 all: all_nomsg msg_test
 all_nomsg: verilator_exe $(VL_INST_MAN_FILES)
 
 .PHONY:verilator_exe
-.PHONY:verilator_bin
-.PHONY:verilator_bin_dbg
-.PHONY:verilator_coverage_bin_dbg
-verilator_exe verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg:
+.PHONY:verilator_bin$(EXEEXT)
+.PHONY:verilator_bin_dbg$(EXEEXT)
+.PHONY:verilator_coverage_bin_dbg$(EXEEXT)
+verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT):
 	@echo ------------------------------------------------------------
 	@echo "making verilator in src"
 	$(MAKE) -C src $(OBJCACHE_JOBS)
@@ -261,24 +181,18 @@ info: $(INFOS)
 %.1: ${srcdir}/bin/%
 	pod2man $< $@
 
-verilator.txt: ${srcdir}/bin/verilator
-	$(POD2TEXT) $< $@
-
-verilator.html: ${srcdir}/bin/verilator
-	pod2html $< >$@
+.PHONY: verilator.html
+verilator.html:
+	$(MAKE) -C docs html
 
 # PDF needs DIST variables; but having configure.ac as dependency isn't detected
-verilator.pdf: ${srcdir}/bin/verilator Makefile $(POD2LATEXFIX)
-	pod2latex --full --out verilator.tex $<
-	$(PERL) $(POD2LATEXFIX) "$(DISTTITLE)" "${DISTDATE}" < verilator.tex > verilator2.tex
-	mv verilator2.tex verilator.tex
-	pdflatex verilator.tex
-	pdflatex verilator.tex
-	-rm -f verilator.toc verilator.aux verilator.idx verilator.out
+.PHONY: verilator.pdf
+verilator.pdf: Makefile
+	$(MAKE) -C docs verilator.pdf
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg \
-	verilator_coverage verilator_gantt verilator_includer verilator_profcfunc
+VL_INST_BIN_FILES = verilator verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT) \
+	verilator_ccache_report verilator_coverage verilator_gantt verilator_includer verilator_profcfunc
 # Some scripts go into both the search path and pkgdatadir,
 # so they can be found by the user, and under $VERILATOR_ROOT.
 
@@ -293,8 +207,10 @@ VL_INST_INC_SRCDIR_FILES = \
 	include/vltstd/*.[chv]* \
 
 VL_INST_DATA_SRCDIR_FILES = \
-	examples/*/*.[chv]*  examples/*/Makefile* \
-	examples/*/CMakeLists.txt
+	examples/*/*.[chv]* \
+	examples/*/CMakeLists.txt \
+	examples/*/Makefile* \
+	examples/*/vl_* \
 
 installbin:
 	$(MKINSTALLDIRS) $(DESTDIR)$(bindir)
@@ -302,11 +218,12 @@ installbin:
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage )
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt )
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_bin$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin$(EXEEXT) )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin_dbg$(EXEEXT) )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg$(EXEEXT) )
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer )
+	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_ccache_report $(DESTDIR)$(pkgdatadir)/bin/verilator_ccache_report )
 
 # Man files can either be part of the original kit, or built in current directory
 # So important we use $^ so VPATH is searched
@@ -379,47 +296,11 @@ uninstall:
 install: all_nomsg install-all
 install-all: installbin installman installdata install-msg
 
-install-here: installman ftp
-
-ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
-DISTNAMEREV = $(shell sed -e '/DTVERSION/!d' -e 's/.*verilator_\([^"]*\).*/\1/' -e q ${srcdir}/src/config_rev.h)
-
-VERILATOR_CAD_DIR = $(CAD_DIR)/verilator/$(DISTNAMEREV)/$(DIRPROJECT_ARCH)
-INST_PROJ_CVS = cp_if_cvs_diff
-
-install-cadtools: dist
-	@echo "Install-project to $(CAD_DIR)"
-	strip bin/verilator_bin*
-	strip bin/verilator_coverage_bin*
-	$(MAKE) install-cadtools-quick
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/man/man1
-	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_DATA) $$p $(VERILATOR_CAD_DIR)/man/man1/$$p; \
-	done
-	$(INST_PROJ_CVS) $(DISTNAME).tgz $(VERILATOR_CAD_DIR)/verilator.tgz
-	rm $(DISTNAME).tgz
-
-install-cadtools-quick:
-ifeq ($(CFG_WITH_DEFENV),yes)
-	@echo "%Error: Reconfigure with './configure --disable-defenv' to avoid hardcoded paths."
-	false
-endif
-	@echo "Install-cadtools-quick (no strip) to $(VERILATOR_CAD_DIR)"
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/gtkwave
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/vltstd
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/bin
-	for p in $(INST_PROJ_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-	for p in $(INST_PROJ_BIN_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-
-# VERILATOR_AUTHOR_SITE
-endif
+install-here: installman info
 
 # Use --xml flag to see the cppcheck code to use for suppression
 CPPCHECK_CPP = $(wildcard \
+	$(srcdir)/examples/*/*.cpp \
 	$(srcdir)/include/*.cpp \
 	$(srcdir)/src/*.cpp )
 CPPCHECK_H = $(wildcard \
@@ -428,7 +309,7 @@ CPPCHECK_H = $(wildcard \
 CPPCHECK_YL = $(wildcard \
 	$(srcdir)/src/*.y \
 	$(srcdir)/src/*.l )
-CPPCHECK = src/cppcheck_filtered
+CPPCHECK = src/cppcheck_filtered cppcheck
 CPPCHECK_FLAGS = --enable=all --inline-suppr \
 	--suppress=unusedScopedObject --suppress=cstyleCast --suppress=useInitializationList \
 	--suppress=nullPointerRedundantCheck
@@ -438,36 +319,86 @@ CPPCHECK_INC = -I$(srcdir)/include -I$(srcdir)/src/obj_dbg -I$(srcdir)/src
 
 cppcheck: $(CPPCHECK_DEP)
 %.cppcheck: %.cpp
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $<
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 -DVL_THREADED=1 $(CPPCHECK_INC) $<
 
 CLANGTIDY = clang-tidy
-CLANGTIDY_FLAGS = -config=''
+CLANGTIDY_FLAGS = -config='' -checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables'
 CLANGTIDY_DEP = $(subst .h,.h.tidy,$(CPPCHECK_H)) \
 	$(subst .cpp,.cpp.tidy,$(CPPCHECK_CPP))
+CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_THREADED=1 -DVL_CPPCHECK=1
 
-clangtidy: $(CLANGTIDY_DEP)
+clang-tidy: $(CLANGTIDY_DEP)
 %.cpp.tidy: %.cpp
-	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) | 2>&1 tee $@
+	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) | 2>&1 tee $@
 %.h.tidy: %.h
-	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) | 2>&1 tee $@
+	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) | 2>&1 tee $@
 
 analyzer-src:
 	-rm -rf src/obj_dbg
-	scan-build $(MAKE) -k verilator_coverage_bin_dbg verilator_bin_dbg
+	scan-build $(MAKE) -k verilator_coverage_bin_dbg$(EXEEXT) verilator_bin_dbg$(EXEEXT)
 
 analyzer-include:
 	-rm -rf examples/*/obj*
 	scan-build $(MAKE) -k examples
 
-CLANGFORMAT = clang-format
+format: clang-format yapf format-pl-exec
+
+CLANGFORMAT = clang-format-11
 CLANGFORMAT_FLAGS = -i
+CLANGFORMAT_FILES = $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL) test_regress/t/*.c* test_regress/t/*.h
 
 clang-format:
-	@$(CLANGFORMAT) --version | egrep 10.0 > /dev/null \
-		|| echo "*** You are not using clang-format 10.0, indents may differ from master's ***"
-	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL)
+	@$(CLANGFORMAT) --version | egrep 11.0 > /dev/null \
+		|| echo "*** You are not using clang-format 11.0, indents may differ from master's ***"
+	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
 
-ftp: info
+PY_PROGRAMS = \
+	bin/verilator_ccache_report \
+	bin/verilator_difftree \
+	bin/verilator_gantt \
+	bin/verilator_profcfunc \
+	examples/xml_py/vl_file_copy \
+	examples/xml_py/vl_hier_graph \
+	docs/guide/conf.py \
+	docs/bin/vl_sphinx_extract \
+	docs/bin/vl_sphinx_fix \
+	src/astgen \
+	src/bisonpre \
+	src/config_rev \
+	src/cppcheck_filtered \
+	src/flexfix \
+	src/vlcovgen \
+	test_regress/t/*.pf \
+	nodist/code_coverage \
+	nodist/dot_importer \
+	nodist/fuzzer/actual_fail \
+	nodist/fuzzer/generate_dictionary \
+	nodist/install_test \
+
+PY_FILES = \
+	$(PY_PROGRAMS) \
+	nodist/code_coverage.dat \
+
+YAPF = yapf3
+YAPF_FLAGS = -i
+
+yapf:
+	$(YAPF) $(YAPF_FLAGS) $(PY_FILES)
+
+FLAKE8 = flake8
+FLAKE8_FLAGS = \
+	--extend-exclude=fastcov.py \
+	--ignore=E123,E129,E251,E501,W503,W504,E701
+
+PYLINT = pylint
+PYLINT_FLAGS = --disable=R0801
+
+lint-py:
+	-$(FLAKE8) $(FLAKE8_FLAGS) $(PY_PROGRAMS)
+	-$(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS)
+
+format-pl-exec:
+	-chmod a+x test_regress/t/*.pl
 
 install-msg:
 	@echo
@@ -519,6 +450,7 @@ clean mostlyclean distclean maintainer-clean::
 	rm -rf test_*/obj_dir
 	rm -rf nodist/fuzzer/dictionary
 	rm -rf nodist/obj_dir
+	rm -rf verilator.txt
 
 distclean maintainer-clean::
 	rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES)
@@ -538,17 +470,6 @@ TAGS:	$(TAGFILES)
 doxygen:
 	$(MAKE) -C docs doxygen
 
-######################################################################
-# Test targets
-
-dist-file-list:
-	@echo "begin-dist-file-list:";  # Scripts look for this
-	@echo $(wildcard $(DISTFILES))
-	@echo "end-dist-file-list:";  # Scripts look for this
-
-print-cfg-with-threaded:
-	@echo $(CFG_WITH_THREADED)
-
 ######################################################################
 # Distributions
 
@@ -556,31 +477,16 @@ DISTTITLE := Verilator $(word 1,$(PACKAGE_VERSION))
 DISTNAME := verilator-$(word 1,$(PACKAGE_VERSION))
 DISTDATEPRE := $(word 2,$(PACKAGE_VERSION))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
-
 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 
 tag:
 	svnorcvs tag $(DISTTAGNAME)
 
-# Don't depend on DISTFILES because there's no rule for "standards.info*".
-dist: $(DISTDEP) maintainer-copy
-	-rm -fr $(DISTNAME)
-	for file in $(DISTFILES); do \
-	  mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \
-	  ln $$file $(DISTNAME)/$$file \
-	  || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \
-	done; true;
-	chmod -R a+r $(DISTNAME)
-	tar chf $(DISTNAME).tar $(DISTNAME)
-	gzip --force --best $(DISTNAME).tar
-	mv $(DISTNAME).tar.gz $(DISTNAME).tgz
-	rm -fr $(DISTNAME)
-
 maintainer-diff:
 	svnorcvs diff $(DISTTAGNAME)
 
 preexist:
 	svnorcvs nexists $(DISTTAGNAME)
 
-maintainer-dist: preexist dist tag
-	svnorcvs release $(DISTNAME).tgz
+maintainer-dist: preexist tag
+	svnorcvs release $(DISTTAGNAME)

README.adoc

@@ -1,154 +0,0 @@
-// Github doesn't render images unless absolute URL
-:!toc:
-
-ifdef::env-github[]
-image:https://img.shields.io/badge/License-LGPL%20v3-blue.svg[license LGPLv3,link=https://www.gnu.org/licenses/lgpl-3.0]
-image:https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg[license Artistic-2.0,link=https://opensource.org/licenses/Artistic-2.0]
-image:https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f[Code Quality,link=https://www.codacy.com/gh/verilator/verilator]
-image:https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg[Coverage,link=https://codecov.io/gh/verilator/verilator]
-image:https://travis-ci.com/verilator/verilator.svg?branch=master[Build Status (Travis CI),link=https://travis-ci.com/verilator/verilator]
-endif::[]
-
-ifdef::env-github[]
-:link_verilator_contributing: link:docs/CONTRIBUTING.adoc
-:link_verilator_install: link:docs/install.adoc
-endif::[]
-ifndef::env-github[]
-:link_verilator_contributing: https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.adoc
-:link_verilator_install: https://verilator.org/install
-endif::[]
-:link_verilator_commercial_support: https://verilator.org/verilator_commercial_support
-
-== Welcome to Verilator
-
-[cols="a,a",indent=0,frame="none",grid="rows"]
-|===
-^.^| *Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.*
-+++ <br/> +++ &bullet; Accepts synthesizable Verilog or SystemVerilog
-+++ <br/> +++ &bullet; Performs lint code-quality checks
-+++ <br/> +++ &bullet; Compiles into multithreaded {cpp}, or SystemC
-+++ <br/> +++ &bullet; Creates XML to front-end your own tools
-<.^|image:https://www.veripool.org/img/verilator_256_200_min.png[Logo,256,200]
-
->.^|image:https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png[,388,178]
-^.^| *Fast*
-+++ <br/> +++ &bullet; Outperforms many commercial simulators
-+++ <br/> +++ &bullet; Single- and multi-threaded output models
-
-^.^| *Widely Used*
-+++ <br/> +++ &bullet; Wide industry and academic deployment
-+++ <br/> +++ &bullet; Out-of-the-box support from Arm, and RISC-V vendor IP
-<.^|image:https://www.veripool.org/img/verilator_usage_400x200-min.png[,400,200]
-
->.^|image:https://www.veripool.org/img/verilator_community_400x125-min.png[,400,125]
-^.^| *Community Driven & Openly Licensed*
-+++ <br/> +++ &bullet; Guided by the https://chipsalliance.org/[CHIPS Alliance] and https://www.linuxfoundation.org/[Linux Foundation]
-+++ <br/> +++ &bullet; Open, and free as in both speech and beer
-+++ <br/> +++ &bullet; More simulation for your verification budget
-
-^.^| *Commercial Support Available*
-+++ <br/> +++ &bullet; Commercial support contracts
-+++ <br/> +++ &bullet; Design support contracts
-+++ <br/> +++ &bullet; Enhancement contracts
-<.^|image:https://www.veripool.org/img/verilator_support_400x125-min.png[,400,125]
-
-|===
-
-== What Verilator Does
-
-Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
-"Verilates" the specified Verilog or SystemVerilog code by
-reading it, performing lint checks, and optionally inserting assertion
-checks and coverage-analysis points.  It outputs single- or multi-threaded
-.cpp and .h files, the "Verilated" code.
-
-The user writes a little {cpp}/SystemC wrapper file, which instantiates the
-"Verilated" model of the user's top level module.  These {cpp}/SystemC
-files are then compiled by a {cpp} compiler (gcc/clang/MSVC++).  The
-resulting executable performs the design simulation.  Verilator also
-supports linking its generated libraries, optionally encrypted, into other
-simulators.
-
-Verilator may not be the best choice if you are expecting a full featured
-replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
-if you are looking for a behavioral Verilog simulator e.g. for a quick
-class project (we recommend http://iverilog.icarus.com[Icarus Verilog] for
-this.)  However, if you are looking for a path to migrate SystemVerilog to
-{cpp} or SystemC, or your team is comfortable writing just a touch of {cpp}
-code, Verilator is the tool for you.
-
-== Performance
-
-Verilator does not simply convert Verilog HDL to {cpp} or SystemC.  Rather,
-Verilator compiles your code into a much faster optimized and optionally
-thread-partitioned model, which is in turn wrapped inside a
-{cpp}/SystemC module.  The results are a compiled
-Verilog model that executes even on a single-thread over 10x faster than
-standalone SystemC, and on a single thread is about 100 times faster than
-interpreted Verilog simulators such as http://iverilog.icarus.com[Icarus
-Verilog]. Another 2-10x speedup might be gained from multithreading
-(yielding 200-1000x total over interpreted simulators).
-
-Verilator has typically similar or better performance versus the
-closed-source Verilog simulators (Carbon Design Systems Carbonator,
-Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic
-CVer/CVC). But, Verilator is open-sourced, so you can spend on computes
-rather than licenses. Thus Verilator gives you the best cycles/dollar.
-
-For more information on how Verilator stacks up to some of the other
-closed-sourced and open-sourced Verilog simulators, see the
-https://www.veripool.org/verilog_sim_benchmarks.html[Verilog Simulator
-Benchmarks].  (If you benchmark Verilator, please see the notes in the
-https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)], and also
-if possible post on the forums the results; there may be additional tweaks
-possible.)
-
-== Installation & Documentation
-
-For more information:
-
-* {link_verilator_install}[Verilator installation and package directory
-  structure]
-
-* https://verilator.org/verilator_doc.html[Verilator manual (HTML)],
-or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)]
-
-* https://github.com/verilator/verilator-announce[Subscribe to verilator announcements]
-
-* https://verilator.org/forum[Verilator forum]
-
-* https://verilator.org/issues[Verilator issues]
-
-== Support
-
-Verilator is a community project, guided by the
-https://chipsalliance.org/[CHIPS Alliance] under the
-https://www.linuxfoundation.org/[Linux Foundation].
-
-We appreciate and welcome your contributions in whatever form; please see
-{link_verilator_contributing}[Contributing to Verilator].  Thanks to our
-https://verilator.org/verilator_doc.html#CONTRIBUTORS[Contributors and
-Sponsors].
-
-Verilator also supports and encourages commercial support models and
-organizations; please see {link_verilator_commercial_support}[Verilator
-Commercial Support].
-
-== Related Projects
-
-* http://gtkwave.sourceforge.net/[GTKwave] - Waveform viewer for Verilator
-traces.
-
-* http://iverilog.icarus.com[Icarus Verilog] - Icarus is a full featured
-interpreted Verilog simulator. If Verilator does not support your needs,
-perhaps Icarus may.
-
-== Open License
-
-Verilator is Copyright 2003-2020 by Wilson Snyder.  (Report bugs to
-https://verilator.org/issues[Verilator Issues].)
-
-Verilator is free software; you can redistribute it and/or modify it under
-the terms of either the GNU Lesser General Public License Version 3 or the
-Perl Artistic License Version 2.0.  See the documentation for more
-details.

README.rst

@@ -0,0 +1,154 @@
+.. Github doesn't render images unless absolute URL
+.. Do not know of a conditional tag, "only: github" nor "github display" works
+
+.. image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg
+    :target: https://www.gnu.org/licenses/lgpl-3.0]
+.. image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
+    :target: https://opensource.org/licenses/Artistic-2.0
+.. image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
+    :target: https://repology.org/project/verilator/versions
+.. image:: https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f
+    :target: https://www.codacy.com/gh/verilator/verilator
+.. image:: https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg
+    :target: https://codecov.io/gh/verilator/verilator
+.. image:: https://github.com/verilator/verilator/workflows/build/badge.svg
+    :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
+
+
+Welcome to Verilator
+====================
+
+.. list-table::
+
+   * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
+        * Accepts synthesizable Verilog or SystemVerilog
+        * Performs lint code-quality checks
+        * Compiles into multithreaded C++, or SystemC
+        * Creates XML to front-end your own tools
+     - |Logo|
+   * - |verilator multithreaded performance|
+     - **Fast**
+        * Outperforms many commercial simulators
+        * Single- and multi-threaded output models
+   * - **Widely Used**
+        * Wide industry and academic deployment
+        * Out-of-the-box support from Arm, and RISC-V vendor IP
+     - |verilator usage|
+   * - |verilator community|
+     - **Community Driven & Openly Licensed**
+        * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_
+        * Open, and free as in both speech and beer
+        * More simulation for your verification budget
+   * - **Commercial Support Available**
+        * Commercial support contracts
+        * Design support contracts
+        * Enhancement contracts
+     - |verilator support|
+
+
+What Verilator Does
+===================
+
+Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
+"Verilates" the specified Verilog or SystemVerilog code by reading it,
+performing lint checks, and optionally inserting assertion checks and
+coverage-analysis points. It outputs single- or multi-threaded .cpp and .h
+files, the "Verilated" code.
+
+The user writes a little C++/SystemC wrapper file, which instantiates the
+"Verilated" model of the user's top level module. These C++/SystemC files
+are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting
+executable performs the design simulation. Verilator also supports linking
+its generated libraries, optionally encrypted, into other simulators.
+
+Verilator may not be the best choice if you are expecting a full featured
+replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
+if you are looking for a behavioral Verilog simulator e.g. for a quick
+class project (we recommend `Icarus Verilog`_ for this.) However, if you
+are looking for a path to migrate SystemVerilog to C++ or SystemC, or your
+team is comfortable writing just a touch of C++ code, Verilator is the tool
+for you.
+
+
+Performance
+===========
+
+Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather,
+Verilator compiles your code into a much faster optimized and optionally
+thread-partitioned model, which is in turn wrapped inside a C++/SystemC
+module. The results are a compiled Verilog model that executes even on a
+single-thread over 10x faster than standalone SystemC, and on a single
+thread is about 100 times faster than interpreted Verilog simulators such
+as `Icarus Verilog`_. Another 2-10x speedup might be gained from
+multithreading (yielding 200-1000x total over interpreted simulators).
+
+Verilator has typically similar or better performance versus the
+closed-source Verilog simulators (Carbon Design Systems Carbonator,
+Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic
+CVer/CVC). But, Verilator is open-sourced, so you can spend on computes
+rather than licenses. Thus Verilator gives you the best cycles/dollar.
+
+Installation & Documentation
+============================
+
+For more information:
+
+- `Verilator installation and package directory structure
+  <https://verilator.org/install>`_
+
+- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
+  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
+
+- `Subscribe to verilator announcements
+  <https://github.com/verilator/verilator-announce>`_
+
+- `Verilator forum <https://verilator.org/forum>`_
+
+- `Verilator issues <https://verilator.org/issues>`_
+
+
+Support
+=======
+
+Verilator is a community project, guided by the `CHIPS Alliance`_ under the
+`Linux Foundation`_.
+
+We appreciate and welcome your contributions in whatever form; please see
+`Contributing to Verilator
+<https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst>`_.
+Thanks to our `Contributors and Sponsors
+<https://verilator.org/guide/latest/contributors.html>`_.
+
+Verilator also supports and encourages commercial support models and
+organizations; please see `Verilator Commercial Support
+<https://verilator.org/verilator_commercial_support>`_.
+
+
+Related Projects
+================
+
+- `GTKwave <http://gtkwave.sourceforge.net/>`_ - Waveform viewer for
+  Verilator traces.
+
+- `Icarus Verilog`_ - Icarus is a full featured interpreted Verilog
+  simulator. If Verilator does not support your needs, perhaps Icarus may.
+
+
+Open License
+============
+
+Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to
+`Verilator Issues <https://verilator.org/issues>`_.)
+
+Verilator is free software; you can redistribute it and/or modify it under
+the terms of either the GNU Lesser General Public License Version 3 or the
+Perl Artistic License Version 2.0. See the documentation for more details.
+
+.. _CHIPS Alliance: https://chipsalliance.org
+.. _Icarus Verilog: http://iverilog.icarus.com
+.. _Linux Foundation: https://www.linuxfoundation.org
+.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
+.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
+.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png
+.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png
+.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png

bin/verilator_ccache_report

@@ -0,0 +1,94 @@
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0301,R0902,R0913,R0914,R0912,R0915,W0621
+######################################################################
+
+import argparse
+import collections
+import pathlib
+import re
+
+from datetime import datetime
+
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Report ccache behavior of a Verilated model build.""",
+    epilog=
+    """Copyright 2002-2021 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+
+parser.add_argument('-o',
+                    type=argparse.FileType('w'),
+                    metavar="OUTFILE",
+                    required=True,
+                    help='output file')
+parser.add_argument('logdir', type=pathlib.Path, help='log directory')
+
+args = parser.parse_args()
+
+results = {}
+elapsed = {}
+
+
+def toDateTime(s):
+    return datetime.strptime(s, "%Y-%m-%dT%H:%M:%S.%f")
+
+
+for logfile in args.logdir.iterdir():
+    with logfile.open() as fh:
+        start = None
+        obj = None
+        for line in fh:
+            line = line.strip()
+            match = re.match(r'\[(\S+)\s.*Object file: (.*)$', line)
+            if match:
+                start = toDateTime(match.group(1))
+                obj = match.group(2)
+            match = re.match(r'\[(\S+)\s.*Result: (.*)$', line)
+            if match:
+                assert obj is not None
+                elapsed[obj] = toDateTime(match.group(1)) - start
+                results[obj] = match.group(2)
+
+args.o.write("#" * 80 + "\n")
+args.o.write("ccache report (from verilator_ccache_report) :\n")
+
+if not results:
+    args.o.write("\nAll object files up to date\n")
+else:
+    args.o.write("\nCompiled object files:\n")
+    wnames = max(len(_) for _ in results) + 1
+    wresults = max(len(_) for _ in results.values()) + 1
+    for k in sorted(results.keys()):
+        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(
+            k,
+            results[k],
+            elapsed[k].total_seconds(),
+            wnames=wnames,
+            wresults=wresults))
+
+    args.o.write("\nSummary:\n")
+    counts = collections.Counter(_ for _ in results.values())
+    total = sum(counts.values())
+    for k in sorted(counts.keys()):
+        c = counts[k]
+        args.o.write("{:{width}}| {} ({:.2%})\n".format(k,
+                                                        c,
+                                                        c / total,
+                                                        width=wresults))
+
+    args.o.write("\nLongest:\n")
+    longest = sorted(list(elapsed.items()),
+                     key=lambda kv: -kv[1].total_seconds())
+    for i, (k, v) in enumerate(longest):
+        args.o.write("{:{width}}| {}s\n".format(k,
+                                                v.total_seconds(),
+                                                width=wnames))
+        if i > 4:
+            break
+
+args.o.write("#" * 80 + "\n")

bin/verilator_coverage

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -30,7 +30,7 @@ $Debug = 0;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # We sneak a look at the flags so we can do some pre-environment checks
@@ -40,7 +40,7 @@ foreach my $sw (@ARGV) {
     push @Opt_Verilator_Sw, $sw;
 }
 
-Getopt::Long::config("no_auto_abbrev","pass_through");
+Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions (
           # Major operating modes
           "help"        => \&usage,
@@ -49,23 +49,23 @@ if (! GetOptions (
           # Additional parameters
           "<>"          => sub {},      # Ignored
     )) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # Normal, non gdb
 run(verilator_coverage_bin()
-    ." ".join(' ',@Opt_Verilator_Sw));
+    . " " . join(' ', @Opt_Verilator_Sw));
 
 #----------------------------------------------------------------------
 
 sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
+    pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
 }
 
 sub debug {
     shift;
     my $level = shift;
-    $Debug = $level||3;
+    $Debug = $level || 3;
 }
 
 #######################################################################
@@ -107,7 +107,7 @@ sub run {
     # Run command, check errors
     my $command = shift;
     $! = undef;  # Cleanup -x
-    print "\t$command\n" if $Debug>=3;
+    print "\t$command\n" if $Debug >= 3;
     system($command);
     my $status = $?;
     if ($status) {
@@ -115,11 +115,11 @@ sub run {
             warn "%Error: verilator_coverage: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
         }
         if ($Debug) {  # For easy rerunning
-            warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
+            warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
             warn "%Error: $command\n";
         }
         if ($status & 127) {
-            if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV
+            if (($status & 127) == 8 || ($status & 127) == 11) {  # SIGFPA or SIGSEGV
                 warn "%Error: Verilator_coverage internal fault, sorry.\n" if !$Debug;
             } elsif (($status & 127) == 6) {  # SIGABRT
                 warn "%Error: Verilator_coverage aborted.\n" if !$Debug;
@@ -158,143 +158,51 @@ verilator_coverage - Verilator coverage analyzer
 
     verilator_coverage  -write-info merged.info -read <datafiles>...
 
-Verilator_coverage processes Verilator coverage reports.
+Verilator_coverage processes Verilated model-generated coverage reports.
 
-With --anotate, it reads the specified data file and generates annotated
-source code with coverage metrics annotated.  If multiple coverage points
-exist on the same line, additional lines will be inserted to report the
-additional points.
+For documentation see
+L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
 
-Additional Verilog-standard arguments specify the search paths necessary to
-find the source code that the coverage analysis was performed on.
+=head1 ARGUMENT SUMMARY
 
-To get correct coverage percentages, you may wish to read logs/coverage.dat
-into Emacs and do a M-x keep-lines to include only those statistics of
-interest.
+    <filename>    Specify input data filename, default "coverage.dat"
+    --annotate <output_dir>       Directory name for source annotation.
+    --annotate-all                All files should be shown.
+    --annotate-min <count>        Minimum occurrence count for uncovered.
+    --help                        Displays this message and version and exits.
+    --rank                        Compute relative importance of tests.
+    --unlink                      With --write, unlink all inputs
+    --version                     Displays program version and exits.
+    --write <filename>            Write aggregate coverage results.
+    --write-info <filename.info>  Write lcov .info.
 
-For Verilog conditions that should never occur, you should add a $stop
-statement.  This will remove the coverage during the next build.
-
-=head1 ARGUMENTS
-
-=over 4
-
-=item I<filename>
-
-Specify input data file, may be repeated to read multiple inputs.  If no
-data file is specified, by default coverage.dat is read.
-
-=item --annotate I<output_directory>
-
-Sprcifies the directory name that source files with annotated coverage data
-should be written to.
-
-=item --annotate-all
-
-Specifies all files should be shown.  By default, only those source files
-which have low coverage are written to the output directory.
-
-=item --annotate-min I<count>
-
-Specifies the minimum occurrence count that should be flagged if the
-coverage point does not include a specified threshold.  Defaults to 10.
-
-=item --help
-
-Displays this message and program version and exits.
-
-=item --rank
-
-Print an experimental report listing the relative importance of each test
-in covering all of the coverage points.  The report shows "Covered" which
-indicates the number of points that test covers; a test is considered to
-cover a point if it has a bucket count of at least 1. The "rank" column has
-a higher number t indicate the test is more important, and rank 0 means the
-test does not need to be run to cover the points.  "RankPts" indicates the
-number of coverage points this test will contribute to overall coverage if
-all tests are run in the order of highest to lowest rank.
-
-=item --unlink
-
-When using --write to combine coverage data, unlink all input files after
-the output has been created.
-
-=item --version
-
-Displays program version and exits.
-
-=item --write I<filename>
-
-Specifies the aggregate coverage results, summed across all the files,
-should be written to the given filename in verilator_coverage data format.
-This is useful in scripts to combine many sequential runs into one master
-coverage file.
-
-=item --write-info I<filename.info>
-
-Specifies the aggregate coverage results, summed across all the files,
-should be written to the given filename in C<lcov> .info format.
-This may be used to use C<lcov> to aggregate or generate reports.
-
-The info format loses data compared to the Verilator coverage data format;
-the info will all forms of coverage converted to line style coverage, and
-if there are multiple coverage points on a single line, the minimum
-coverage across those points will be used to report coverage of the line.
-
-=back
-
-=head1 VERILOG ARGUMENTS
-
-The following arguments are compatible with GCC, VCS and most Verilog
-programs.
-
-=over 4
-
-=item +libext+I<ext>+I<ext>...
-
-Defines the extensions for Verilog files.
-
-=item +define+I<var>+I<value>
-=item -DI<var>=I<value>
-
-Defines the given variable.
-
-=item +incdir+I<dir>
-=item -II<dir>
-
-Specifies a directory for finding include files.
-
-=item -f I<file>
-
-Specifies a file containing additional command line arguments.
-
-=item -y I<dir>
-
-Specifies a module search directory.
-
-=back
+    +libext+I<ext>+I<ext>...      Extensions for Verilog files.
+    +define+I<var>+I<value>       Defines the given variable.
+    -DI<var>=I<value>             Defines the given variable.
+    +incdir+I<dir>                Add directory for finding include files.
+    -II<dir>                      Add directory for finding include files.
+    -y I<dir>                     Specifies module search directory.
 
 =head1 DISTRIBUTION
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+Copyright 2003-2021 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.
 
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-=head1 AUTHORS
-
-Wilson Snyder <[email protected]>
-
 =head1 SEE ALSO
 
 C<verilator>, C<lcov>
 
 L<verilator_coverage --help> which is the source for this document.
 
+and L<https://verilator.org/guide/latest/exe_verilator_coverage.html> for
+detailed documentation.
+
 =cut
 
 ######################################################################

bin/verilator_difftree

@@ -1,256 +1,139 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116
 ######################################################################
 
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import glob
+import os.path
+import re
+import sys
 
-#======================================================================
 
-# Old version 1 dump nodes with no dtypep's
-our %Ver1_Non_Dtyped = map {$_ => 1} qw(
-  ACTIVE ALWAYS ALWAYSPOST ALWAYSPUBLIC ATTROF BEGIN BREAK CASE CASEITEM
-  CCALL CELL CELLINLINE CFILE CFUNC CHANGEDET CLOCKING COMMENT CONTINUE
-  COVERDECL COVERINC COVERTOGGLE CRETURN CSTMT DEFPARAM DISABLE DISPLAY DOT
-  DPIEXPORT FCLOSE FFLUSH FINAL FINISH FOPEN GENCASE GENERATE GENFOR GENIF
-  IF IMPLICIT INITARRAY INITIAL JUMPGO JUMPLABEL MODULE NETLIST
-  NOTFOUNDMODULE PACKAGE PACKAGEIMPORT PARSEREF PIN PORT PRAGMA PRIMITIVE
-  PSLASSERT PSLCOVER PSLDEFCLOCK PULL RANGE READMEM REPEAT RETURN SCCTOR
-  SCDTOR SCHDR SCIMP SCIMPHDR SCINT SCOPE SELBIT SELEXTRACT SELMINUS
-  SELPLUS SENGATE SENITEM SENTREE SFORMAT SFORMATF STOP SYSIGNORE SYSTEMT
-  TASK TASKREF TEXT TOPSCOPE TYPEDEFFWD TYPETABLE UCSTMT UDPTABLE
-  UDPTABLELINE UNTILSTABLE VASSERT WHILE );
+def diff(a, b):
 
-#======================================================================
-# main
+    if not os.path.exists(a):
+        sys.exit("%Error: No old diff filename found: " + a)
+    if not os.path.exists(b):
+        sys.exit("%Error: No new diff filename found: " + b)
 
-$Debug = 0;
-my $Opt_A;
-my $Opt_B;
-my $Opt_Lineno = 1;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-          "lineno!"     => \$Opt_Lineno,
-    )) {
-    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
-}
+    if os.path.isdir(a) and os.path.isdir(b):
+        diff_dir(a, b)
+    elif os.path.isfile(a) and os.path.isfile(b):
+        diff_file(a, b)
+    else:
+        sys.exit("%Error: Mix of files and dirs")
 
-defined $Opt_A or die "%Error: No old diff filename\n";
-defined $Opt_B or die "%Error: No new diff filename\n";
 
--e $Opt_A or die "%Error: No old diff filename found: $Opt_A\n";
--e $Opt_B or die "%Error: No new diff filename found: $Opt_B\n";
-
-if (-d $Opt_A && -d $Opt_B) {
-    diff_dir($Opt_A, $Opt_B);
-} elsif (-f $Opt_A && -f $Opt_B) {
-    diff_file($Opt_A, $Opt_B);
-} else {
-    die "%Error: Mix of files and dirs\n";
-}
-
-sub diff_dir {
-    my $a = shift;
-    my $b = shift;
+def diff_dir(a, b):
     # Diff all files under two directories
-    my %files;
+    files = collections.defaultdict(lambda: {})
 
-    foreach my $fn (glob("$a/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{a} = $fn;
-    }
-    foreach my $fn (glob("$b/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{b} = $fn;
-    }
-    my $any;
-    foreach my $base (sort (keys %files)) {
-        my $a = $files{$base}{a};
-        my $b = $files{$base}{b};
-        next if !$a || !$b;
-        print "="x70,"\n";
-        print "= $a <-> $b\n";
-        diff_file($a,$b);
-        $any = 1;
-    }
-    $any or warn("%Warning: No .tree files found that have similar base names:\n    "
-                 .join("\n    ", sort keys %files),"\n");
-}
+    for fn in glob.glob(a + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['a'] = fn
+    for fn in glob.glob(b + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['b'] = fn
 
-sub diff_file {
-    my $a = shift;
-    my $b = shift;
+    anyfile = False
+    for base in sorted(files.keys()):
+        a = files[base]['a']
+        b = files[base]['b']
+        if not a or not b:
+            continue
+        print("=" * 70)
+        print("= %s <-> %s" % (a, b))
+        diff_file(a, b)
+        anyfile = True
+    if not anyfile:
+        sys.stderr.write(
+            "%Warning: No .tree files found that have similar base names\n")
+
+
+def diff_file(a, b):
     # Compare the two tree files
-    (my $short_a = $a) =~ s/[^a-zA-Z0-9.]+/_/g;
-    (my $short_b = $b) =~ s/[^a-zA-Z0-9.]+/_/g;
-    my $tmp_a = "/tmp/${$}_${short_a}.a";
-    my $tmp_b = "/tmp/${$}_${short_b}.b";
+    short_a = re.sub(r'[^a-zA-Z0-9.]+', '_', a)
+    short_b = re.sub(r'[^a-zA-Z0-9.]+', '_', b)
+    tmp_a = "/tmp/%s_%s.a" % (os.getpid(), short_a)
+    tmp_b = "/tmp/%s_%s.b" % (os.getpid(), short_b)
 
-    my $vera = version_from($a);
-    my $verb = version_from($b);
-    my $verCvt = (($vera < 0x3900 && $verb >= 0x3900)
-                  || ($vera >= 0x3900 && $verb < 0x3900));
+    # Version conversion deprecated, but for future...
+    # vera = version_from(a)
+    # verb = version_from(b)
+    # verCvt = ((vera < 0x3900 and verb >= 0x3900)
+    #            or (vera >= 0x3900 and verb < 0x3900))
 
-    filter($a, $tmp_a, $verCvt);
-    filter($b, $tmp_b, $verCvt);
-    system("diff -u $tmp_a $tmp_b");
-    unlink $tmp_a;
-    unlink $tmp_b;
-}
+    filterf(a, tmp_a)
+    filterf(b, tmp_b)
+    os.system("diff -u " + tmp_a + " " + tmp_b)
+    os.unlink(tmp_a)
+    os.unlink(tmp_b)
 
-sub version_from {
-    my $fn = shift;
+
+def version_from(filename):
     # Return dump format
-    my $f1 = IO::File->new ($fn) or die "%Error: $! $fn,";
-    while (defined (my $line=$f1->getline())) {
-        last if $. > 10;
-        return hex $1 if $line =~ /\(format (0x[0-9.]+)\)/;
-    }
-    return 1.0;
-}
+    with open(filename) as fh:
+        lineno = 0
+        for line in fh:
+            if lineno > 10:
+                break
+            match = re.search(r'format (0x[0-9.]+)', line)
+            if match:
+                return hex(match.group(1))
+    return 1.0
 
-sub filter {
-    my $fn1 = shift;
-    my $fn2 = shift;
-    my $verCvt = shift;
+
+def filterf(fn1, fn2):
     # Remove hex numbers before diffing
-    my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,";
-    my $f2 = IO::File->new ($fn2,"w") or die "%Error: $! $fn2,";
-    while (defined (my $line=$f1->getline())) {
-      same_line:
-        next if $line =~ / This=/;
-        $line =~ s/0x[a-f0-9]+/0x/g;
-        $line =~ s/<e[0-9]+\#?>/<e>/g;
-        $line =~ s/{[a-z]*\d+}/{}/g if !$Opt_Lineno;
-        if ($verCvt) {
-            next if $line =~ /^     NETLIST/;
-            $line =~ s!\@dt=0x\(G?/?([^)]+)\)!$1!g;  # NEW: @dt -> OLD: non @dt format
-            #                                        # Below Ver1_Non_Dtyped may replace above further
-            if ($line =~ /: ([A-Z]+) /) {
-                my $type = $1;
-                next if $type =~ 'DTYPE';
-                if ($type eq 'TYPETABLE' || $type eq 'RANGE') {
-                    $line =~ /^(\s+\S+:) /; my $prefix = $1;
-                    while (defined ($line=$f1->getline())) {
-                        next if $line =~ /^\s+[a-z]/;  # Table body
-                        next if $line =~ /^${prefix}[0-9]:/;
-                        goto same_line;
-                    }
-                    next;
-                }
-                if ($Ver1_Non_Dtyped{$type}) {
-                    $line =~ s! w[0-9]+!!g;
-                }
-            }
-            $line =~ s!\@dt=0$!NoW!g;   # NEW: dt=null -> common format
-            $line =~ s!\@dt=0 !NoW !g;  # NEW: dt=null -> common format
-            $line =~ s! s?w0$! NoW!g;   # OLD: no width -> common format
-            $line =~ s! s?w0 ! NoW !g;  # OLD: no width -> common format
-        }
-        print $f2 $line;
-    }
-    $f1->close;
-    $f2->close;
-}
+    with open(fn1) as fh1:
+        with open(fn2, "w") as fh2:
+            for line in fh1:
+                if re.search(r' This=', line):
+                    continue
+                line = re.sub(r'0x[a-f0-9]+', '0x', line)
+                line = re.sub(r'<e[0-9]+\#?>', '<e>', line)
+                if not Args.no_lineno:
+                    line = re.sub(r'{[a-z]*\d+}', '{}', line)
+                fh2.write(line)
 
-#----------------------------------------------------------------------
 
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
+######################################################################
+######################################################################
 
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_A) {
-        $Opt_A = $param;
-    } elsif (!defined $Opt_B) {
-        $Opt_B = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub run {
-    # Run a system command, check errors
-    my $command = shift;
-    print "\t$command\n";
-    system "$command";
-    my $status = $?;
-    ($status == 0) or die "%Error: Command Failed $command, $status, stopped";
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_difftree - Compare two Verilator debugging trees
-
-=head1 SYNOPSIS
-
-  verilator_difftree .../a/a.tree  .../b/a.tree
-  verilator_difftree .../a         .../b
-
-=head1 DESCRIPTION
-
-Verilator_difftree is used for debugging Verilator tree output files.  It
-performs a diff between two files, or all files common between two
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Compare two Verilator debugging trees""",
+    epilog=
+    """Verilator_difftree is used for debugging Verilator tree output files.
+It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.
 
-=head1 ARGUMENTS
+For documentation see
+https://verilator.org/guide/latest/exe_verilator_difftree.html
 
-=over 4
-
-=item --help
-
-Displays this message and program version and exits.
-
-=item --nolineno
-
-Do not show differences in line numbering.
-
-=back
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2005-2020 by Wilson Snyder. This program is free software; you
+Copyright 2005-2021 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 AUTHORS
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('--no-lineno',
+                    action='store_false',
+                    help='do not show differences in line numbering')
+parser.add_argument('filea', help='input file a to diff')
+parser.add_argument('fileb', help='input file b to diff')
 
-Wilson Snyder <[email protected]>
-
-=head1 SEE ALSO
-
-C<verilator>
-
-=cut
+Args = parser.parse_args()
+diff(Args.filea, Args.fileb)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_difftree  {$V4D,$V4}/test_regress/obj_dir/t_EXAMPLE/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_difftree ../test_regress/t/t_difftree.{a,b}.tree"
+# End:

bin/verilator_gantt

@@ -1,149 +1,162 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116,C0301,R0914,R0912,R0915,W0511,eval-used
 ######################################################################
 
-use warnings;
-use strict;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-use vars qw($Debug);
+import argparse
+import collections
+import math
+import re
+import statistics
+# from pprint import pprint
 
-$Debug = 0;
-my $Opt_File;
-my $Opt_Time_Per_Char = 0;  # rdtsc ticks per char in gantt chart, 0=auto
-my $opt_vcd = "profile_threads.vcd";
-
-our %Threads;
-our %Mtasks;
-our %Global;
-
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "scale=i"     => \$Opt_Time_Per_Char,
-          "debug"       => sub { $Debug = 1; },
-          "vcd=s"       => \$opt_vcd,
-          "no-vcd!"     => sub { $opt_vcd = undef; },
-          "<>"          => \&parameter,
-    )) {
-    die "%Error: Bad usage, try 'verilator_gantt --help'\n";
+Threads = collections.defaultdict(lambda: {})
+Mtasks = collections.defaultdict(lambda: {})
+Evals = collections.defaultdict(lambda: {})
+EvalLoops = collections.defaultdict(lambda: {})
+Global = {
+    'args': {},
+    'cpuinfo': collections.defaultdict(lambda: {}),
+    'rdtsc_cycle_time': 0,
+    'stats': {}
 }
 
-$Opt_File = "profile_threads.dat" if !defined $Opt_File;
+######################################################################
 
-process($Opt_File);
-write_vcd($opt_vcd) if defined $opt_vcd;
-exit(0);
 
-#######################################################################
+def process(filename):
+    read_data(filename)
+    report()
 
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
 
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_File) {
-        $Opt_File = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
+def read_data(filename):
+    with open(filename) as fh:
+        re_prof = re.compile(
+            r'^VLPROF mtask\s(\d+)\sstart\s(\d+)\selapsed\s(\d+)\spredict_start\s(\d+)\spredict_cost\s(\d+)\scpu\s(\d+)\son thread (\d+)'
+        )
+        re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)')
+        re_loop = re.compile(
+            r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)')
+        re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*')
+        re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$')
+        re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)')
+        re_time = re.compile(r'rdtsc time = (\d+) ticks')
+        re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$')
+        re_proc_dat = re.compile(r'VLPROFPROC ([a-z_ ]+)\s*:\s*(.*)$')
+        cpu = None
 
-#######################################################################
+        for line in fh:
+            if re_prof.match(line):
+                match = re_prof.match(line)
+                mtask = int(match.group(1))
+                start = int(match.group(2))
+                elapsed_time = int(match.group(3))
+                end = start + elapsed_time
+                predict_start = int(match.group(4))
+                predict_cost = int(match.group(5))
+                cpu = int(match.group(6))
+                thread = int(match.group(7))
+                if start not in Threads[thread]:
+                    Threads[thread][start] = {}
+                Threads[thread][start]['mtask'] = mtask
+                Threads[thread][start]['end'] = end
+                Threads[thread][start]['cpu'] = cpu
+                Threads[thread][start]['predict_start'] = predict_start
+                Threads[thread][start]['predict_cost'] = predict_cost
 
-sub process {
-    my $filename = shift;
+                if 'elapsed' not in Mtasks[mtask]:
+                    Mtasks[mtask] = {'end': 0, 'elapsed': 0}
+                Mtasks[mtask]['thread'] = thread
+                Mtasks[mtask]['elapsed'] += elapsed_time
+                Mtasks[mtask]['predict_start'] = predict_start
+                Mtasks[mtask]['predict_cost'] = predict_cost
+                Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], end)
+            elif re_eval.match(line):
+                match = re_eval.match(line)
+                start = int(match.group(1))
+                elapsed_time = int(match.group(2))
+                Evals[start]['start'] = start
+                Evals[start]['end'] = start + elapsed_time
+            elif re_loop.match(line):
+                match = re_loop.match(line)
+                start = int(match.group(1))
+                elapsed_time = int(match.group(2))
+                EvalLoops[start]['start'] = start
+                EvalLoops[start]['end'] = start + elapsed_time
+            elif re.match(r'^VLPROFTHREAD', line):
+                None  # pylint: disable=pointless-statement
+            elif re_arg1.match(line):
+                match = re_arg1.match(line)
+                Global['args'][match.group(1)] = match.group(2)
+            elif re_arg2.match(line):
+                match = re_arg2.match(line)
+                Global['args'][match.group(1)] = match.group(2)
+            elif re_stat.match(line):
+                match = re_stat.match(line)
+                Global['stats'][match.group(1)] = match.group(2)
+            elif re_proc_cpu.match(line):
+                match = re_proc_cpu.match(line)
+                cpu = int(match.group(1))
+            elif cpu and re_proc_dat.match(line):
+                match = re_proc_dat.match(line)
+                term = match.group(1)
+                value = match.group(2)
+                term = re.sub(r'\s+$', '', term)
+                term = re.sub(r'\s+', '_', term)
+                value = re.sub(r'\s+$', '', value)
+                Global['cpuinfo'][cpu][term] = value
+            elif re.match(r'^#', line):
+                None  # pylint: disable=pointless-statement
+            elif Args.debug:
+                print("-Unk: %s" % line)
+            # TODO -- this is parsing text printed by a client.
+            # Really, verilator proper should generate this
+            # if it's useful...
+            if re_time.match(line):
+                Global['rdtsc_cycle_time'] = re_time.group(1)
 
-    read_data($filename);
-    report();
-}
 
-#######################################################################
+def re_match_result(regexp, line, result_to):
+    result_to = re.match(regexp, line)
+    return result_to
 
-sub read_data {
-    my $filename = shift;
 
-    %Global = (rdtsc_cycle_time => 0);
+######################################################################
 
-    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
-    while (my $line = $fh->getline) {
-        if ($line =~ m/VLPROF mtask\s(\d+)\sstart\s(\d+)\send\s(\d+)\selapsed\s(\d+)\spredict_time\s(\d+)\scpu\s(\d+)\son thread (\d+)/) {
-            my $mtask = $1;
-            my $start = $2;
-            my $end = $3;
-            my $elapsed_time = $4;
-            my $predict_time = $5;
-            my $cpu = $6;
-            my $thread = $7;
-            $Threads{$thread}{$start}{mtask} = $mtask;
-            $Threads{$thread}{$start}{end} = $end;
-            $Threads{$thread}{$start}{cpu} = $cpu;
 
-            if (!exists $Mtasks{$mtask}{elapsed}) {
-                $Mtasks{$mtask}{elapsed} = 0;
-            }
-            $Mtasks{$mtask}{elapsed} += $elapsed_time;
-            $Mtasks{$mtask}{predict} = $predict_time;
-            $Mtasks{$mtask}{end} = max($Mtasks{$mtask}{end}, $end);
-        }
-        elsif ($line =~ /^VLPROFTHREAD/) {}
-        elsif ($line =~ m/VLPROF arg\s+(\S+)\+([0-9.])\s*$/
-               || $line =~ m/VLPROF arg\s+(\S+)\s+([0-9.])\s*$/) {
-            $Global{args}{$1} = $2;
-        }
-        elsif ($line =~ m/VLPROF stat\s+(\S+)\s+([0-9.]+)/) {
-            $Global{stats}{$1} = $2;
-        }
-        elsif ($line =~ /^#/) {}
-        elsif ($Debug) {
-            chomp $line;
-            print "Unk: $line\n";
-        }
-        # TODO -- this is parsing text printed by a client.
-        # Really, verilator proper should generate this
-        # if it's useful...
-        if ($line =~ m/rdtsc time = (\d+) ticks/) {
-            $Global{rdtsc_cycle_time} = $1;
-        }
-    }
-}
+def report():
+    print("Verilator Gantt report")
 
-sub report {
-    print "Verilator Gantt report\n";
+    print("\nArgument settings:")
+    for arg in sorted(Global['args'].keys()):
+        plus = "+" if re.match(r'^\+', arg) else " "
+        print("  %s%s%s" % (arg, plus, Global['args'][arg]))
 
-    print "\nArgument settings:\n";
-    foreach my $arg (sort keys %{$Global{args}}) {
-        my $plus = ($arg =~ /^\+/) ? "+" : " ";
-        printf "  %s%s%d\n", $arg, $plus, $Global{args}{$arg};
-    }
-
-    my $nthreads = scalar keys %Threads;
-    $Global{cpus} = {};
-    foreach my $thread (keys %Threads) {
+    nthreads = len(Threads)
+    Global['cpus'] = {}
+    for thread in Threads:
         # Make potentially multiple characters per column
-        foreach my $start (keys %{$Threads{$thread}}) {
-            my $cpu = $Threads{$thread}{$start}{cpu};
-            my $elapsed = $Threads{$thread}{$start}{end} - $start;
-            $Global{cpus}{$cpu}{cpu_time} += $elapsed;
-        }
-    }
+        for start in Threads[thread]:
+            cpu = Threads[thread][start]['cpu']
+            elapsed = Threads[thread][start]['end'] - start
+            if cpu not in Global['cpus']:
+                Global['cpus'][cpu] = {'cpu_time': 0}
+            Global['cpus'][cpu]['cpu_time'] += elapsed
 
-    my $mt_mtask_time = 0;
-    my $long_mtask_time = 0;
-    my $last_end = 0;
-    foreach my $mtask (keys %Mtasks) {
-        $mt_mtask_time += $Mtasks{$mtask}{elapsed};
-        $last_end = max($last_end, $Mtasks{$mtask}{end});
-        $long_mtask_time = max($long_mtask_time, $Mtasks{$mtask}{elapsed});
-    }
-    $Global{last_end} = $last_end;
-
-    report_graph();
+    measured_mt_mtask_time = 0
+    predict_mt_mtask_time = 0
+    long_mtask_time = 0
+    measured_last_end = 0
+    predict_last_end = 0
+    for mtask in Mtasks:
+        measured_mt_mtask_time += Mtasks[mtask]['elapsed']
+        predict_mt_mtask_time += Mtasks[mtask]['predict_cost']
+        measured_last_end = max(measured_last_end, Mtasks[mtask]['end'])
+        predict_last_end = max(
+            predict_last_end,
+            Mtasks[mtask]['predict_start'] + Mtasks[mtask]['predict_cost'])
+        long_mtask_time = max(long_mtask_time, Mtasks[mtask]['elapsed'])
+    Global['measured_last_end'] = measured_last_end
+    Global['predict_last_end'] = predict_last_end
 
     # If we know cycle time in the same (rdtsc) units,
     # this will give us an actual utilization number,
@@ -153,409 +166,328 @@ sub report {
     # serial mode, to estimate the overhead of data sharing,
     # which will show up in the total elapsed time. (Overhead
     # of synchronization and scheduling should not.)
-    print "\nAnalysis:\n";
-    printf "  Total threads             = %d\n", $nthreads;
-    printf "  Total mtasks              = %d\n", scalar(keys %Mtasks);
-    printf "  Total cpus used           = %d\n", scalar(keys %{$Global{cpus}});
-    printf "  Total yields              = %d\n", $Global{stats}{yields};
-    printf "  Total eval time           = %d rdtsc ticks\n", $Global{last_end};
-    printf "  Longest mtask time        = %d rdtsc ticks\n", $long_mtask_time;
-    printf "  All-thread mtask time     = %d rdtsc ticks\n", $mt_mtask_time;
-    my $long_efficiency = $long_mtask_time/($Global{last_end});
-    printf "  Longest-thread efficiency = %0.1f%%\n", $long_efficiency*100;
-    my $mt_efficiency = $mt_mtask_time/($Global{last_end}*$nthreads);
-    printf "  All-thread efficiency     = %0.1f%%\n", $mt_efficiency*100;
-    printf "  All-thread speedup        = %0.1f\n", $mt_efficiency*$nthreads;
-    if ($Global{rdtsc_cycle_time} > 0) {
-        my $ut = $mt_mtask_time / $Global{rdtsc_cycle_time};
-        print "tot_mtask_cpu=$mt_mtask_time cyc=$Global{rdtsc_cycle_time} ut=$ut\n";
-    }
+    print("\nAnalysis:")
+    print("  Total threads             = %d" % nthreads)
+    print("  Total mtasks              = %d" % len(Mtasks))
+    ncpus = len(Global['cpus'])
+    print("  Total cpus used           = %d" % ncpus)
+    print("  Total yields              = %d" % int(Global['stats']['yields']))
+    print("  Total evals               = %d" % len(Evals))
+    print("  Total eval loops          = %d" % len(EvalLoops))
+    print("  Total eval time           = %d rdtsc ticks" %
+          Global['measured_last_end'])
+    print("  Longest mtask time        = %d rdtsc ticks" % long_mtask_time)
+    print("  All-thread mtask time     = %d rdtsc ticks" %
+          measured_mt_mtask_time)
+    long_efficiency = long_mtask_time / (Global.get('measured_last_end', 1)
+                                         or 1)
+    print("  Longest-thread efficiency = %0.1f%%" % (long_efficiency * 100.0))
+    mt_efficiency = measured_mt_mtask_time / (
+        Global.get('measured_last_end', 1) * nthreads or 1)
+    print("  All-thread efficiency     = %0.1f%%" % (mt_efficiency * 100.0))
+    print("  All-thread speedup        = %0.1f" % (mt_efficiency * nthreads))
+    if Global['rdtsc_cycle_time'] > 0:
+        ut = measured_mt_mtask_time / Global['rdtsc_cycle_time']
+        print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" +
+              Global['rdtsc_cycle_time'] + " ut=" + ut)
 
-    my @p2e_ratios;
-    my $min_p2e = 1000000;
-    my $min_mtask;
-    my $max_p2e = -1000000;
-    my $max_mtask;
-    foreach my $mtask (sort keys %Mtasks) {
-        if ($Mtasks{$mtask}{elapsed} > 0) {
-            if ($Mtasks{$mtask}{predict} == 0) {
-                $Mtasks{$mtask}{predict} = 1;  # don't log(0) below
-            }
-            my $p2e_ratio = log( $Mtasks{$mtask}{predict} / $Mtasks{$mtask}{elapsed} );
-            #print "log(p2e $mtask) = $p2e_ratio   (predict $Mtasks{$mtask}{predict}, elapsed $Mtasks{$mtask}{elapsed})\n";
-            push @p2e_ratios, $p2e_ratio;
+    predict_mt_efficiency = predict_mt_mtask_time / (
+        Global.get('predict_last_end', 1) * nthreads or 1)
+    print("\nPrediction (what Verilator used for scheduling):")
+    print("  All-thread efficiency     = %0.1f%%" %
+          (predict_mt_efficiency * 100.0))
+    print("  All-thread speedup        = %0.1f" %
+          (predict_mt_efficiency * nthreads))
 
-            if ($p2e_ratio > $max_p2e) {
-                $max_p2e = $p2e_ratio;
-                $max_mtask = $mtask;
-            }
-            if ($p2e_ratio < $min_p2e) {
-                $min_p2e = $p2e_ratio;
-                $min_mtask = $mtask;
-            }
+    p2e_ratios = []
+    min_p2e = 1000000
+    min_mtask = None
+    max_p2e = -1000000
+    max_mtask = None
+
+    for mtask in sorted(Mtasks.keys()):
+        if Mtasks[mtask]['elapsed'] > 0:
+            if Mtasks[mtask]['predict_cost'] == 0:
+                Mtasks[mtask]['predict_cost'] = 1  # don't log(0) below
+            p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] /
+                                 Mtasks[mtask]['elapsed'])
+            p2e_ratios.append(p2e_ratio)
+
+            if p2e_ratio > max_p2e:
+                max_p2e = p2e_ratio
+                max_mtask = mtask
+            if p2e_ratio < min_p2e:
+                min_p2e = p2e_ratio
+                min_mtask = mtask
+
+    print("\nStatistics:")
+    print("  min log(p2e) = %0.3f" % min_p2e, end="")
+    print("  from mtask %d (predict %d," %
+          (min_mtask, Mtasks[min_mtask]['predict_cost']),
+          end="")
+    print(" elapsed %d)" % Mtasks[min_mtask]['elapsed'])
+    print("  max log(p2e) = %0.3f" % max_p2e, end="")
+    print("  from mtask %d (predict %d," %
+          (max_mtask, Mtasks[max_mtask]['predict_cost']),
+          end="")
+    print(" elapsed %d)" % Mtasks[max_mtask]['elapsed'])
+
+    stddev = statistics.pstdev(p2e_ratios)
+    mean = statistics.mean(p2e_ratios)
+    print("  mean = %0.3f" % mean)
+    print("  stddev = %0.3f" % stddev)
+    print("  e ^ stddev = %0.3f" % math.exp(stddev))
+
+    report_cpus()
+
+    if nthreads > ncpus:
+        print()
+        print("%%Warning: There were fewer CPUs (%d) then threads (%d)." %
+              (ncpus, nthreads))
+        print("        : See docs on use of numactl.")
+    else:
+        if 'cpu_socket_cores_warning' in Global:
+            print()
+            print(
+                "%Warning: Multiple threads scheduled on same hyperthreaded core."
+            )
+            print("        : See docs on use of numactl.")
+        if 'cpu_sockets_warning' in Global:
+            print()
+            print("%Warning: Threads scheduled on multiple sockets.")
+            print("        : See docs on use of numactl.")
+    print()
+
+
+def report_cpus():
+    print("\nCPUs:")
+
+    Global['cpu_sockets'] = collections.defaultdict(lambda: 0)
+    Global['cpu_socket_cores'] = collections.defaultdict(lambda: 0)
+
+    for cpu in sorted(Global['cpus'].keys()):
+        print("  cpu %d: " % cpu, end='')
+        print("cpu_time=%d" % Global['cpus'][cpu]['cpu_time'], end='')
+
+        socket = None
+        if cpu in Global['cpuinfo']:
+            cpuinfo = Global['cpuinfo'][cpu]
+            if 'physical_id' in cpuinfo and 'core_id' in cpuinfo:
+                socket = int(cpuinfo['physical_id'])
+                Global['cpu_sockets'][socket] += 1
+                print(" socket=%d" % socket, end='')
+
+                core = int(cpuinfo['core_id'])
+                Global['cpu_socket_cores'][str(socket) + "__" + str(core)] += 1
+                print(" core=%d" % core, end='')
+
+            if 'model_name' in cpuinfo:
+                model = cpuinfo['model_name']
+                print("  %s" % model, end='')
+        print()
+
+    if len(Global['cpu_sockets']) > 1:
+        Global['cpu_sockets_warning'] = True
+        for scn in Global['cpu_socket_cores'].values():
+            if scn > 1:
+                Global['cpu_socket_cores_warning'] = True
+
+
+######################################################################
+
+
+def write_vcd(filename):
+    print("Writing %s" % filename)
+    with open(filename, "w") as fh:
+        vcd = {
+            'values':
+            collections.defaultdict(lambda: {}),  # {<time>}{<code>} = value
+            'sigs': {
+                'predicted_threads': {},
+                'measured_threads': {},
+                'cpus': {},
+                'evals': {},
+                'mtasks': {},
+                'Stats': {}
+            }  # {<module>}{<sig}} = code
         }
-    }
+        code = 0
 
-    print "\nStatistics:\n";
-    print "  min log(p2e) = $min_p2e  from mtask $min_mtask (predict $Mtasks{$min_mtask}{predict}, elapsed $Mtasks{$min_mtask}{elapsed})\n";
-    print "  max log(p2e) = $max_p2e  from mtask $max_mtask (predict $Mtasks{$max_mtask}{predict}, elapsed $Mtasks{$max_mtask}{elapsed})\n";
-
-    my $stddev = stddev(\@p2e_ratios);
-    my $mean = mean(\@p2e_ratios);
-    print "  mean = " . ($mean) . "\n";
-    print "  stddev = " . ($stddev) . "\n";
-    print "  e ^ stddev = " . exp($stddev). "\n";
-    print "\n";
-}
-
-sub report_graph {
-    my $time_per = $Opt_Time_Per_Char;
-    if ($time_per == 0) {
-        $time_per = ($Global{last_end} / 40);  # Start with 40 columns
-        while ($time_per > 10) {
-            my ($graph, $conflicts) = _make_graph($time_per);
-            last if !$conflicts;
-            $time_per = int($time_per/2);
+        parallelism = {
+            'measured': collections.defaultdict(lambda: 0),
+            'predicted': collections.defaultdict(lambda: 0)
         }
-        # One more step so we can fit more labels
-        $time_per = int($time_per/2);
-    }
+        parallelism['measured'][0] = 0
+        parallelism['predicted'][0] = 0
 
-    my ($graph, $conflicts) = _make_graph($time_per);
+        # Measured graph
+        for thread in sorted(Threads.keys()):
+            sig = "thread%d_mtask" % thread
+            if sig not in vcd['sigs']['measured_threads']:
+                vcd['sigs']['measured_threads'][sig] = code
+                code += 1
+            mcode = vcd['sigs']['measured_threads'][sig]
 
-    print "\nThread gantt graph:\n";
-    print "  Legend: One character width = $time_per rdtsc ticks\n";
-    print "  Legend: '&' = multiple mtasks in this period (character width)\n";
+            for start in sorted(Threads[thread]):
+                mtask = Threads[thread][start]['mtask']
+                end = Threads[thread][start]['end']
+                cpu = Threads[thread][start]['cpu']
+                vcd['values'][start][mcode] = mtask
+                vcd['values'][end][mcode] = None
+                parallelism['measured'][start] += 1
+                parallelism['measured'][end] -= 1
 
-    my $scale = "   <-".$Global{last_end}." rdtsc total";
-    for (my $col = length($scale);  # -2 for '->' below
-         $col < ($Global{last_end}/$time_per); ++$col) {
-        $scale .= "-";
-    }
-    print "  $scale->\n";
+                sig = "cpu%d_thread" % cpu
+                if sig not in vcd['sigs']['cpus']:
+                    vcd['sigs']['cpus'][sig] = code
+                    code += 1
+                ccode = vcd['sigs']['cpus'][sig]
+                vcd['values'][start][ccode] = thread
+                vcd['values'][end][ccode] = None
 
-    foreach my $thread (sort keys %{$graph}) {
-        print "  t: ";
-        _print_graph_line($graph->{$thread}, '');
-    }
-}
+                sig = "mtask%d_cpu" % mtask
+                if sig not in vcd['sigs']['mtasks']:
+                    vcd['sigs']['mtasks'][sig] = code
+                    code += 1
+                ccode = vcd['sigs']['mtasks'][sig]
+                vcd['values'][start][ccode] = cpu
+                vcd['values'][end][ccode] = None
 
-sub _make_graph {
-    my $time_per = shift;
+        # Eval graph
+        vcd['sigs']['evals']["eval"] = code
+        elcode = code
+        code += 1
+        n = 0
+        for eval_start in Evals:
+            eval_end = Evals[eval_start]['end']
+            n += 1
+            vcd['values'][eval_start][elcode] = n
+            vcd['values'][eval_end][elcode] = None
 
-    my $graph = {};  # {thread}{column}{char=>'x' or chars=>#}
-    my $conflicts = 0;
-    foreach my $thread (keys %Threads) {
-        # Make potentially multiple characters per column
-        foreach my $start (sort {$a <=> $b} keys %{$Threads{$thread}}) {
-            my $end = $Threads{$thread}{$start}{end};
-            my $mtask = $Threads{$thread}{$start}{mtask};
-            my $cpu = $Threads{$thread}{$start}{cpu};
+        # Eval_loop graph
+        vcd['sigs']['evals']["eval_loop"] = code
+        elcode = code
+        code += 1
+        n = 0
+        for eval_start in EvalLoops:
+            eval_end = EvalLoops[eval_start]['end']
+            n += 1
+            vcd['values'][eval_start][elcode] = n
+            vcd['values'][eval_end][elcode] = None
 
-            my $startcol = _time_col($time_per, $start);
-            my $endcol = _time_col($time_per, $end);
+        # Predicted graph
+        for eval_start in EvalLoops:
+            eval_end = EvalLoops[eval_start]['end']
+            # Compute scale so predicted graph is of same width as eval
+            measured_scaling = (eval_end -
+                                eval_start) / Global['predict_last_end']
+            # Predict mtasks that fill the time the eval occupied
+            for mtask in Mtasks:
+                thread = Mtasks[mtask]['thread']
+                pred_scaled_start = eval_start + int(
+                    Mtasks[mtask]['predict_start'] * measured_scaling)
+                pred_scaled_end = eval_start + int(
+                    (Mtasks[mtask]['predict_start'] +
+                     Mtasks[mtask]['predict_cost']) * measured_scaling)
+                if pred_scaled_start == pred_scaled_end:
+                    continue
 
-            my $label = "[";
-            $label .= "$cpu";  # Maybe make optional in future
-            my $width = $endcol - $startcol + 1;
-            while (length($label) < ($width-1)) {  # -1 for ']'
-                $label .= "-";
-            }
-            $label .= "]";
-            $graph->{$thread}[$startcol]{char} .= $label;
-        }
-        if ($Debug) {
-            print "# Multicol: "; _print_graph_line($graph->{$thread}, '|');
-        }
-        # Expand line to one char per column
-        for (my $col = 0; $col <= $#{$graph->{$thread}}; ++$col) {
-            if (my $chars = $graph->{$thread}[$col]{char}) {
-                my $ok = 1;
-                for (my $coladd = 1; $coladd<length($chars); ++$coladd) {
-                    if ($graph->{$thread}[$col + $coladd]{char}) {
-                        $ok = 0; last;
-                    }
-                }
-                if (!$ok) {
-                    if ($chars =~ /\[.*\[/) {  # Two begins or more
-                        $conflicts++;
-                        $graph->{$thread}[$col]{char} = "&";
-                    } else {
-                        $graph->{$thread}[$col]{char} = "[";
-                    }
-                    for (my $coladd = 1; $coladd<length($chars); ++$coladd) {
-                        if ($graph->{$thread}[$col + $coladd]{char}) {
-                            last;
-                        } else {
-                            $graph->{$thread}[$col + $coladd]{char} = 'x';
-                        }
-                    }
-                } else {
-                    my $coladd = 0;
-                    foreach my $char (split //, $chars) {
-                        $graph->{$thread}[$col+$coladd]{char} = $char;
-                        ++$coladd;
-                    }
-                }
-            }
-        }
-        if ($Debug) {
-            print "# Singlcol: "; _print_graph_line($graph->{$thread}, '|');
-        }
-    }
-    print "# Conflicts $conflicts\n" if $Debug;
-    return ($graph, $conflicts);
-}
+                sig = "predicted_thread%d_mtask" % thread
+                if sig not in vcd['sigs']['predicted_threads']:
+                    vcd['sigs']['predicted_threads'][sig] = code
+                    code += 1
+                mcode = vcd['sigs']['predicted_threads'][sig]
 
-sub _print_graph_line {
-    my $graph_thread = shift;
-    my $sep = shift;
-    for (my $col = 0; $col <= $#{$graph_thread}; ++$col) {
-        my $c = $graph_thread->[$col]{char}; $c=' ' if !defined $c;
-        print $c, $sep;
-    }
-    print "\n";
-}
+                vcd['values'][pred_scaled_start][mcode] = mtask
+                vcd['values'][pred_scaled_end][mcode] = None
 
-sub _time_col {
-    my $time_per = shift;
-    my $time = shift;
-    return int($time/$time_per);
-}
+                parallelism['predicted'][pred_scaled_start] += 1
+                parallelism['predicted'][pred_scaled_end] -= 1
 
-#######################################################################
+        # Parallelism graph
+        for measpred in ('measured', 'predicted'):
+            vcd['sigs']['Stats']["%s_parallelism" % measpred] = code
+            pcode = code
+            code += 1
+            value = 0
+            for time in sorted(parallelism[measpred].keys()):
+                value += parallelism[measpred][time]
+                vcd['values'][time][pcode] = value
 
-sub write_vcd {
-    my $filename = shift;
-    print "Writing $filename\n";
-    my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,";
-    my $vcd = {values => {},  # {<time>}{<code>} = value
-               sigs => {},  # {<module>}{<sig}} = code
-               code => 0,
-    };
+        # Create output file
+        fh.write("$version Generated by verilator_gantt $end\n")
+        fh.write("$timescale 1ns $end\n")
+        fh.write("\n")
 
-    my %parallelism;
-    foreach my $thread (keys %Threads) {
-        my $mcode = ($vcd->{sigs}{threads}{"thread${thread}_mtask"} ||= $vcd->{code}++);
-        foreach my $start (sort {$a <=> $b} keys %{$Threads{$thread}}) {
-            my $end = $Threads{$thread}{$start}{end};
-            my $mtask = $Threads{$thread}{$start}{mtask};
-            my $cpu = $Threads{$thread}{$start}{cpu};
-            $vcd->{values}{$start}{$mcode} = $mtask;
-            $vcd->{values}{$end}{$mcode} = undef;
-            $parallelism{$start}++;
-            $parallelism{$end}--;
+        all_codes = {}
+        fh.write(" $scope module gantt $end\n")
+        for module in sorted(vcd['sigs'].keys()):
+            fh.write("  $scope module %s $end\n" % module)
+            for sig in sorted(vcd['sigs'][module].keys()):
+                code = vcd['sigs'][module][sig]
+                fh.write("   $var wire 32 v%x %s [31:0] $end\n" % (code, sig))
+                all_codes[code] = 1
+            fh.write("  $upscope $end\n")
+        fh.write(" $upscope $end\n")
+        fh.write("$enddefinitions $end\n")
+        fh.write("\n")
 
-            my $ccode = $vcd->{sigs}{cpus}{"cpu${cpu}_thread"} ||= $vcd->{code}++;
-            $vcd->{values}{$start}{$ccode} = $thread;
-            $vcd->{values}{$end}{$ccode} = undef;
+        first = True
+        for time in sorted(vcd['values']):
+            if first:
+                first = False
+                # Start with Z for any signals without time zero data
+                for code in sorted(all_codes.keys()):
+                    if code not in vcd['values'][time]:
+                        vcd['values'][time][code] = None
+            fh.write("#%d\n" % time)
+            for code in sorted(vcd['values'][time].keys()):
+                value = vcd['values'][time][code]
+                if value is None:
+                    fh.write("bz v%x\n" % code)
+                else:
+                    fh.write("b%s v%x\n" % (format(value, 'b'), code))
 
-            my $mcode = $vcd->{sigs}{mtasks}{"mtask${mtask}_cpu"} ||= $vcd->{code}++;
-            $vcd->{values}{$start}{$mcode} = $cpu;
-            $vcd->{values}{$end}{$mcode} = undef;
-        }
-    }
-    {
-        my $pcode = ($vcd->{sigs}{Stats}{"parallelism"} ||= $vcd->{code}++);
-        my $value = 0;
-        foreach my $time (sort {$a<=>$b} keys %parallelism) {
-            $value += $parallelism{$time};
-            $vcd->{values}{$time}{$pcode} = $value;
-        }
-    }
 
-    $fh->print('$version Generated by verilator_gantt $end'."\n");
-    $fh->print('$timescale 1ns $end'."\n");
-    $fh->print("\n");
+######################################################################
 
-    my %all_codes;
-    $fh->print(' $scope module gantt $end'."\n");
-    foreach my $module (sort keys %{$vcd->{sigs}}) {
-        $fh->printf('  $scope module %s $end'."\n", $module);
-        foreach my $sig (sort keys %{$vcd->{sigs}{$module}}) {
-            my $code = $vcd->{sigs}{$module}{$sig};
-            $fh->printf('   $var wire 32 v%x %s [31:0] $end'."\n",
-                        $code, $sig);
-            $all_codes{$code} = 1;
-        }
-        $fh->print('  $upscope $end'."\n");
-    }
-    $fh->print(' $upscope $end'."\n");
-    $fh->print('$enddefinitions $end'."\n");
-    $fh->print("\n");
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Create Gantt chart of multi-threaded execution""",
+    epilog=
+    """Verilator_gantt creates a visual representation to help analyze Verilator
+#xmultithreaded simulation performance, by showing when each macro-task
+#xstarts and ends, and showing when each thread is busy or idle.
 
-    my $first = 1;
-    foreach my $time (sort {$a <=> $b} keys %{$vcd->{values}}) {
-        if ($first) {
-            $first = 0;
-            # Start with Z for any signals without time zero data
-            foreach my $code (keys %all_codes) {
-                if (!defined $vcd->{values}{$time}{$code}) {
-                    $vcd->{values}{$time}{$code} = undef;
-                }
-            }
-        }
-        $fh->printf("#%d\n", $time);
-        foreach my $code (sort keys %{$vcd->{values}{$time}}) {
-            my $value = $vcd->{values}{$time}{$code};
-            if (defined $value) {
-                $fh->printf("b%b v%x\n", $value, $code);
-            } else {
-                $fh->printf("bz v%x\n", $code);
-            }
-        }
-    }
-}
+For documentation see
+https://verilator.org/guide/latest/exe_verilator_gantt.html
 
-#######################################################################
-# Similar to Statistics::Basic functions, but avoid a package dependency
-
-sub max {
-    my $n = $_[0]; shift;
-    while (defined $_[0]) {
-        $n = $_[0] if !defined $n || $_[0] > $n;
-        shift;
-    }
-    return $n;
-}
-
-sub mean {
-    my $arrayref = shift;
-    my $n = 0;
-    my $sum = 0;
-    foreach my $v (@$arrayref) {
-        $sum += $v;
-        $n++;
-    }
-    return undef if !$n;
-    return $sum/$n;
-}
-
-sub stddev {
-    my $arrayref = shift;
-    my $n = 0;
-    my $sum = 0;
-    my $sumsq = 0;
-    foreach my $v (@$arrayref) {
-        $sum += $v;
-        $sumsq += $v**2;
-        $n++;
-    }
-    return undef if !$n;
-    return sqrt(($sumsq/$n) - ($sum/$n)**2);
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_gantt - Create Gantt chart of multi-threaded execution
-
-=head1 SYNOPSIS
-
-Creates a visual representation to help analyze Verilator multithreaded
-simulation performance, by showing when each macro-task starts and ends,
-and showing when each thread is busy or idle.
-
-The generated Gantt chart has time on the X-axis. Times shown are to the
-scale printed, i.e. a certain about of time for each character width.  The
-Y-axis shows threads, each thread's execution is shown on one line.  That
-line shows "[" at the position in time when it executes.
-
-Following the "[" is the cpu number the task executed on, followed by zero
-or more "-" to make the width of the characters match the scaled execution
-time, followed by a "]".  If the scale is too small, the cpu number and
-mtask number will not be printed.  If the scale is very small, a "&"
-indicates multiple mtasks started at that time position.
-
-Also creates a value change dump (VCD) format dump file which may be viewed
-in a waveform viewer (e.g. C<GTKWave>).  See below.
-
-=head1 USAGE
-
-  Build with --prof-threads.
-
-  Run a sim with +verilator+prof+threads+window 2.
-
-  This will create profile_threads.dat.
-
-  Then run:
-
-  verilator_gantt profile_threads.dat
-
-  The report will be printed on standard output, this also generates
-  profile_threads.vcd
-
-  View profile_threads.vcd in a waveform viewer.
-
-=head1 VCD SIGNALS
-
-In waveforms there are the following signals. Most signals the "decimal"
-format will remove the leading zeros and make the traces easier to read.
-
-parallelism: The number of mtasks active at this time, for best performance
-this will match the thread count. You may want to use an "analog step"
-format to view this signal.
-
-cpu#_thread: For the given CPU number, the thread number executing.
-
-mtask#_cpu; For the given mtask id, the CPU it is executing on.
-
-thread#_mtask: For the given thread number, the mtask id executing.
-
-=head1 ARGUMENTS
-
-=over 4
-
-=item I<filename>
-
-The filename to read data from, defaults to "profile_threads.dat".
-
-=item --help
-
-Displays this message and program version and exits.
-
-=item --scale I<n>
-
-On the X-axis of the generated Gantt chart, each character represents this
-many time units. (On x86, time units are rdtsc ticks.)  Defaults to 0,
-which will automatically compute a reasonable scale where no two mtasks
-need to fit into same character width's worth of scaled time.
-
-=item --no-vcd
-
-=item --vcd I<filename>
-
-Set output filename for vcd dump, or disable. Default is
-verilator_gantt.vcd.
-
-=back
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2018-2020 by Wilson Snyder. This program is free software; you
+Copyright 2018-2021 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 AUTHORS
+parser.add_argument('--debug', action='store_true', help='enable debug')
+parser.add_argument('--no-vcd',
+                    help='disable creating vcd',
+                    action='store_true')
+parser.add_argument('--vcd',
+                    help='filename for vcd outpue',
+                    default='profile_threads.vcd')
+parser.add_argument('filename',
+                    help='input profile_threads.dat filename to process',
+                    default='profile_threads.dat')
 
-Wilson Snyder <[email protected]>
+Args = parser.parse_args()
 
-=head1 SEE ALSO
-
-C<verilator>
-
-=cut
+process(Args.filename)
+if not Args.no_vcd:
+    write_vcd(Args.vcd)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_gantt $V4/test_regress/obj_vltmt/t_gantt/vlt_sim.log"
-### End:
+# Local Variables:
+# compile-command: "./verilator_gantt ../test_regress/t/t_gantt_io.dat"
+# End:

bin/verilator_includer

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 # DESCRIPTION: Print include statements for each ARGV
 #
-# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,11 +10,11 @@
 
 require 5.005;
 use warnings;
-print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n";
+print "// DESCR" . "IPTION: Generated by verilator_includer via makefile\n";
 foreach my $param (@ARGV) {
     if ($param =~ /^-D([^=]+)=(.*)/) {
-        print "#define $1 $2\n"
+        print "#define $1 $2\n";
     } else {
-        print "#include \"$param\"\n"
+        print "#include \"$param\"\n";
     }
 }

bin/verilator_profcfunc

@@ -1,251 +1,204 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116,R0914,R0912,R0915,eval-used
 ######################################################################
 
-require 5.006_001;
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-eval { use Data::Dumper;  $Data::Dumper::Indent = 1; }; # Debug, ok if missing
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import re
+# from pprint import pprint
 
-#======================================================================
+######################################################################
 
 
-#======================================================================
-# main
+def profcfunc(filename):
+    funcs = {}
 
-$Debug = 0;
-my $Opt_File;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-    )) {
-    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
-}
+    with open(filename) as fh:
 
-defined $Opt_File or die "%Error: No filename given\n";
+        for line in fh:
+            #                  %time      cumesec   selfsec     calls     {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = float(match.group(3))
+                func = match.group(4)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
-profcfunc($Opt_File);
-
-#----------------------------------------------------------------------
-
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
-
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_File) {
-        $Opt_File = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub profcfunc {
-    my $filename = shift;
-    # Remove hex numbers before diffing
-    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
-
-    my %funcs;
-
-    while (defined (my $line=$fh->getline())) {
-        #                  %time      cumesec   selfsec     calls     {stuff}   name
-        if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-        # Older gprofs have no call column for single-call functions
-        #                  %time      cumesec   selfsec      {stuff}   name
-        elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=1; my $func=$3;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-    }
-    $fh->close;
+            # Older gprofs have no call column for single-call functions
+            #                  %time      cumesec   selfsec      {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = 1
+                func = match.group(3)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
     # Find modules
-    my %pointer_mods;
-    my %verilated_mods;
-    foreach my $func (keys %funcs) {
-        if ($func =~ /(.*)::_eval\(([a-zA-Z_0-9]+__Syms).*\)$/) {
-            $verilated_mods{$1} = qr/^$1/;
-            $pointer_mods{$2} = $1;
-        }
-    }
-    #print Dumper(\%pointer_mods, \%verilated_mods);
+    verilated_mods = {}
+    for func in funcs:
+        match = re.search(r'(.*)::eval(_step)?\(', func)
+        if match:
+            prefix = match.group(1)
+            if Args.debug:
+                print("-got _eval %s   prefix=%s" % (func, prefix))
+            verilated_mods[prefix] = re.compile(r'^' + prefix)
+    # pprint(verilated_mods)
 
-    # Resort by Verilog name
-    my %vfuncs;
-    my %groups;
-    foreach my $func (keys %funcs) {
-        my $pct = $funcs{$func}{pct};
-        my $vfunc = $func;
-        my $design;
+    # Sort by Verilog name
+    vfuncs = {}
+    groups = {}
+    groups['type'] = collections.defaultdict(lambda: 0)
+    groups['design'] = collections.defaultdict(lambda: 0)
+    groups['module'] = collections.defaultdict(lambda: 0)
 
-        if ($func =~ /\(([a-zA-Z_0-9]+__Syms)/) {
-            $design = $pointer_mods{$1};
-        }
+    for func in funcs:
+        pct = funcs[func]['pct']
+        vfunc = func
 
-        foreach my $vde (keys %verilated_mods) {
-            last if $design;
-            if ($func =~ /$verilated_mods{$vde}/) {
-                $design=$vde;
-                last;
-            }
-        }
+        funcarg = re.sub(r'^.*\(', '', func)
 
-        if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(/) {
-            $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
-            $groups{type}{"Verilog Blocks under $design"} += $pct;
-            $groups{design}{$design} += $pct;
-            $groups{module}{$1} += $pct;
-        } else {
-            if ($design) {
-                $vfunc = sprintf("VCommon   %s", $func);
-                $groups{type}{"Common code under $design"} += $pct;
-                $groups{design}{$design} += $pct;
-                $groups{module}{$design." common code"} += $pct;
-            } elsif ($func =~ /^VL_[A-Z0-9_]+/
-                     || $func =~ /^_?vl_[a-zA-Z0-9_]+/
-                     || $func =~ /^verilated/i) {
-                $vfunc = sprintf("VLib      %s", $func);
-                $groups{type}{'VLib'} += $pct;
-                $groups{design}{'VLib'} += $pct;
-                $groups{module}{'VLib'} += $pct;
-            } elsif ($func =~ /^_mcount_private/) {
-                $vfunc = sprintf("Prof      %s", $func);
-                $groups{type}{'Prof'} += $pct;
-                $groups{design}{'Prof'} += $pct;
-                $groups{module}{'Prof'} += $pct;
-            } else {
-                $vfunc = sprintf("C++       %s", $func);
-                $groups{type}{'C++'} += $pct;
-                $groups{design}{'C++'} += $pct;
-                $groups{module}{'C++'} += $pct;
-            }
-        }
-        $vfuncs{$vfunc} = $funcs{$func};
-    }
+        design = None
+        for vde in verilated_mods:
+            if verilated_mods[vde].match(func) or verilated_mods[vde].match(
+                    funcarg):
+                design = vde
+                break
+
+        vdesign = "-"
+
+        prof_match = re.search(r'__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(', vfunc)
+        if design and prof_match:
+            linefunc = prof_match.group(1)
+            lineno = int(prof_match.group(2))
+            vfunc = "VBlock    %s:%d" % (linefunc, lineno)
+            vdesign = design
+            groups['type']["Verilog Blocks under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][linefunc] += pct
+        elif design:
+            vfunc = "VCommon   " + func
+            vdesign = design
+            groups['type']["Common code under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][design + " common code"] += pct
+        elif re.match(r'(VL_[A-Z0-9_]+|_?vl_[a-zA-Z0-9_]+|Verilated)', vfunc):
+            vfunc = "VLib      " + func
+            groups['type']['VLib'] += pct
+            groups['design']['VLib'] += pct
+            groups['module']['VLib'] += pct
+        elif re.match(r'^_mcount_private', vfunc):
+            vfunc = "Prof      " + func
+            groups['type']['Prof'] += pct
+            groups['design']['Prof'] += pct
+            groups['module']['Prof'] += pct
+        else:
+            vfunc = "C++       " + func
+            groups['type']['C++'] += pct
+            groups['design']['C++'] += pct
+            groups['module']['C++'] += pct
+
+        if vfunc not in vfuncs:
+            vfuncs[vfunc] = funcs[func]
+            vfuncs[vfunc]['design'] = vdesign
+        else:
+            vfuncs[vfunc]['pct'] += funcs[func]['pct']
+            vfuncs[vfunc]['calls'] += funcs[func]['calls']
+            vfuncs[vfunc]['sec'] += funcs[func]['sec']
+
+    for ftype in ['type', 'design', 'module']:
+        missing = 100
+        for item in groups[ftype].keys():
+            missing -= groups[ftype][item]
+        groups[ftype]["\377Unaccounted for/rounding error"] = missing
+
+        print("Overall summary by %s:" % ftype)
+        print("  %-6s  %s" % ("% time", ftype))
+        for what in sorted(groups[ftype].keys()):
+            # \377 used to establish sort order
+            pwhat = re.sub(r'^\377', '', what)
+            print("  %6.2f  %s" % (groups[ftype][what], pwhat))
+        print()
+
+    design_width = 1
+    for func in vfuncs:
+        if design_width < len(vfuncs[func]['design']):
+            design_width = len(vfuncs[func]['design'])
+
+    print("Verilog code profile:")
+    print("   These are split into three categories:")
+    print("      C++:     Time in non-Verilated C++ code")
+    print("      Prof:    Time in profile overhead")
+    print("      VBlock:  Time attributable to a block in a" +
+          " Verilog file and line")
+    print("      VCommon: Time in a Verilated module," +
+          " due to all parts of the design")
+    print("      VLib:    Time in Verilated common libraries," +
+          " called by the Verilated code")
+    print()
+
+    print("  %   cumulative   self              ")
+    print((" time   seconds   seconds      calls   %-" + str(design_width) +
+           "s  type      filename and line number") % "design")
+
+    cume = 0
+    for func in sorted(vfuncs.keys(),
+                       key=lambda f: vfuncs[f]['sec'],
+                       reverse=True):
+        cume += vfuncs[func]['sec']
+        print(("%6.2f %9.2f %8.2f %10d   %-" + str(design_width) + "s  %s") %
+              (vfuncs[func]['pct'], cume, vfuncs[func]['sec'],
+               vfuncs[func]['calls'], vfuncs[func]['design'], func))
 
 
-    foreach my $type (qw(type design module)) {
-        my $missing = 100;
-        foreach (sort (keys %{$groups{$type}})) {
-            $missing -= $groups{$type}{$_};
-        }
-        if ($missing) {
-            $groups{$type}{"\377Unaccounted for/rounding error"} = $missing;
-        }
+######################################################################
+######################################################################
 
-        print("Overall summary by $type:\n");
-        printf("  %-6s  %s\n","% time",$type);
-        foreach my $what (sort (keys %{$groups{$type}})) {
-            (my $pwhat = $what) =~ s/^\377//;  # Just used to establish sort order
-            printf("  %6.2f  %s\n", $groups{$type}{$what}, $pwhat);
-        }
-        print("\n");
-    }
-
-    print("Verilog code profile:\n");
-    print("   These are split into three categories:\n");
-    print("      C++:     Time in non-Verilated C++ code\n");
-    print("      Prof:    Time in profile overhead\n");
-    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
-    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
-    print("      VLib:    Time in Verilated common libraries, called by the Verilated code\n");
-    print("\n");
-
-    print("  %   cumulative   self              \n");
-    print(" time   seconds   seconds    calls   type      filename and line number\n");
-
-    my $cume = 0;
-    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
-                            || $a cmp $b}
-                      (keys %vfuncs)) {
-        $cume += $vfuncs{$func}{sec};
-        printf +("%6.2f %9.2f %8.2f %8d   %s\n",
-                 $vfuncs{$func}{pct},
-                 $cume, $vfuncs{$func}{sec},
-                 $vfuncs{$func}{calls},
-                 $func);
-    }
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_profcfunc - Read gprof report created with --prof-cfuncs
-
-=head1 SYNOPSIS
-
-  verilator --prof-cfuncs ....
-  gcc --ggdb -pg ....
-  {run executable}
-  gprof
-  verilator_profcfuncs gprof.out
-
-=head1 DESCRIPTION
-
-Verilator_profcfunc reads a profile report created by gprof.  The names of
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Read gprof report created with --prof-cfuncs""",
+    epilog=
+    """Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc,
 in each Verilog block.
 
-=head1 ARGUMENTS
+For documentation see
+https://verilator.org/guide/latest/exe_verilator_profcfunc.html
 
-=over 4
-
-=item --help
-
-Displays this message and program version and exits.
-
-=back
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2007-2020 by Wilson Snyder. This program is free software; you
+Copyright 2002-2021 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 AUTHORS
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('filename', help='input gprof output to process')
 
-Wilson Snyder <[email protected]>
-
-=head1 SEE ALSO
-
-C<verilator>
-
-=cut
+Args = parser.parse_args()
+profcfunc(Args.filename)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_profcfunc ../test_regress/t/t_profcfunc.gprof"
+# End:

ci/ci-ccache-maint.bash

@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
-# DESCRIPTION: Verilator: Travis CI ccache maintenance
+# DESCRIPTION: Verilator: CI ccache maintenance
 #
 # Copyright 2020 by Geza Lore. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
@@ -19,8 +19,8 @@ set -x
 ccache --version
 
 # Flush ccache if requested in commit message
-COMMIT="${TRAVIS_PULL_REQUEST_SHA:-$TRAVIS_COMMIT}"
-if git log --format=%B -n 1 "$COMMIT" | grep -q -i '\[travis\s\+ccache\s\+clear\]'; then
+COMMIT="${CI_PULL_REQUEST_SHA:-$CI_COMMIT}"
+if git log --format=%B -n 1 "$COMMIT" | grep -q -i '\[CI\s\+ccache\s\+clear\]'; then
   echo "Flushing ccache due to commit message"
   ccache -C
 fi

ci/ci-install.bash

@@ -1,5 +1,5 @@
 #!/usr/bin/env bash
-# DESCRIPTION: Verilator: Travis CI dependency install script
+# DESCRIPTION: Verilator: CI dependency install script
 #
 # Copyright 2020 by Geza Lore. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
@@ -14,91 +14,101 @@
 # required by the particular build stage.
 ################################################################################
 
-# Note that Travis runs "apt-get update" when "apt-get install" is used in the
-# .travis.yml file directly, but since we invoke it via this script, we need to
-# run it manually where requried, otherwise some packages cannot be found.
-
 set -e
 set -x
 
+cd $(dirname "$0")/..
+
 fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
-if [ "$TRAVIS_OS_NAME" = "linux" ]; then
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
+if [ "$CI_OS_NAME" = "linux" ]; then
   MAKE=make
-elif [ "$TRAVIS_OS_NAME" = "osx" ]; then
+elif [ "$CI_OS_NAME" = "osx" ]; then
   MAKE=make
-elif [ "$TRAVIS_OS_NAME" = "freebsd" ]; then
+elif [ "$CI_OS_NAME" = "freebsd" ]; then
   MAKE=gmake
 else
-  fatal "Unknown os: '$TRAVIS_OS_NAME'"
+  fatal "Unknown os: '$CI_OS_NAME'"
 fi
 
 install-vcddiff() {
   TMP_DIR="$(mktemp -d)"
   git clone https://github.com/veripool/vcddiff "$TMP_DIR"
-  git -C "${TMP_DIR}" checkout 5112f88b7ba8818dce9dfb72619e64a1fc19542c
+  git -C "${TMP_DIR}" checkout e5664be5fe39d353bf3fcb50aa05214ab7ed4ac4
   "$MAKE" -C "${TMP_DIR}"
   sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin
 }
 
-if [ "$TRAVIS_BUILD_STAGE_NAME" = "build" ]; then
+if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
   ##############################################################################
   # Dependencies of jobs in the 'build' stage, i.e.: packages required to
   # build Verilator
 
-  if [ "$TRAVIS_OS_NAME" = "linux" ]; then
+  if [ "$CI_OS_NAME" = "linux" ]; then
     sudo apt-get update
-    sudo apt-get install libfl-dev
-    sudo apt-get install libgoogle-perftools-dev
-    if [ "$COVERAGE" = 1 ]; then
-      yes yes | sudo cpan -fi Unix::Processors Parallel::Forker
+    sudo apt-get install libfl-dev libgoogle-perftools-dev ccache
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+      sudo apt-get install libsystemc libsystemc-dev
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$COVERAGE" = 1 ]; then
+      yes yes | sudo cpan -fi Parallel::Forker
+    fi
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install gcc-multilib g++-multilib
     fi
-  elif [ "$TRAVIS_OS_NAME" = "osx" ]; then
+  elif [ "$CI_OS_NAME" = "osx" ]; then
     brew update
     brew install ccache perl gperftools
-  elif [ "$TRAVIS_OS_NAME" = "freebsd" ]; then
+  elif [ "$CI_OS_NAME" = "freebsd" ]; then
     sudo pkg install -y autoconf bison ccache gmake perl5
   else
-    fatal "Unknown os: '$TRAVIS_OS_NAME'"
+    fatal "Unknown os: '$CI_OS_NAME'"
   fi
-elif [ "$TRAVIS_BUILD_STAGE_NAME" = "test" ]; then
+
+  if [ -n "$CCACHE_DIR" ]; then
+    mkdir -p "$CCACHE_DIR" && ./ci/ci-ccache-maint.bash
+  fi
+elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
   ##############################################################################
   # Dependencies of jobs in the 'test' stage, i.e.: packages required to
   # run the tests
 
-  if [ "$TRAVIS_OS_NAME" = "linux" ]; then
+  if [ "$CI_OS_NAME" = "linux" ]; then
     sudo apt-get update
-    sudo apt-get install gdb gtkwave lcov
-    if [ "$TRAVIS_DIST" = "focal" ]; then
+    # libfl-dev needed for internal coverage's test runs
+    sudo apt-get install gdb gtkwave lcov libfl-dev ccache
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
       sudo apt-get install libsystemc-dev
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install lib32z1-dev gcc-multilib g++-multilib
     fi
-  elif [ "$TRAVIS_OS_NAME" = "osx" ]; then
+  elif [ "$CI_OS_NAME" = "osx" ]; then
     brew update
     # brew cask install gtkwave # fst2vcd hangs at launch, so don't bother
     brew install ccache perl
-  elif [ "$TRAVIS_OS_NAME" = "freebsd" ]; then
+  elif [ "$CI_OS_NAME" = "freebsd" ]; then
     # fst2vcd fails with "Could not open '<input file>', exiting."
     sudo pkg install -y ccache gmake perl5 python3
   else
-    fatal "Unknown os: '$TRAVIS_OS_NAME'"
+    fatal "Unknown os: '$CI_OS_NAME'"
   fi
   # Common installs
-  if [ "$TRAVIS_DIST" != "trusty" ]; then
-    TRAVIS_CPAN_REPO=https://cpan.org
+  if [ "$CI_RUNS_ON" != "ubuntu-14.04" ]; then
+    CI_CPAN_REPO=https://cpan.org
   fi
-  # Not listing Bit::Vector as slow to install, and only skips one test
-  yes yes | sudo cpan -M $TRAVIS_CPAN_REPO -fi Unix::Processors Parallel::Forker
+  yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker
   install-vcddiff
 else
   ##############################################################################
   # Unknown build stage
-  fatal "Unknown build stage: '$TRAVIS_BUILD_STAGE_NAME'"
+  fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'"
 fi

ci/ci-script.bash

@@ -0,0 +1,193 @@
+#!/usr/bin/env bash
+# DESCRIPTION: Verilator: CI main job script
+#
+# Copyright 2020 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+################################################################################
+# This is the main script executed in the 'script' phase by all jobs. We use a
+# single script to keep the CI setting simple. We pass job parameters via
+# environment variables using 'env' keys.
+################################################################################
+
+set -e
+set -x
+
+fatal() {
+  echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
+}
+
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
+if [ "$CI_OS_NAME" = "linux" ]; then
+  export MAKE=make
+  NPROC=$(nproc)
+elif [ "$CI_OS_NAME" = "osx" ]; then
+  export MAKE=make
+  NPROC=$(sysctl -n hw.logicalcpu)
+elif [ "$CI_OS_NAME" = "freebsd" ]; then
+  export MAKE=gmake
+  NPROC=$(sysctl -n hw.ncpu)
+else
+  fatal "Unknown os: '$CI_OS_NAME'"
+fi
+
+if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
+  ##############################################################################
+  # Build verilator
+
+  if [ "$COVERAGE" != 1 ]; then
+    autoconf
+    ./configure --enable-longtests --enable-ccwarn ${CI_M32:+--enable-m32}
+    ccache -z
+    "$MAKE" -j "$NPROC" -k
+    ccache -s
+    if [ "$CI_OS_NAME" = "osx" ]; then
+      file bin/verilator_bin
+      file bin/verilator_bin_dbg
+      md5 bin/verilator_bin
+      md5 bin/verilator_bin_dbg
+      stat bin/verilator_bin
+      stat bin/verilator_bin_dbg
+    fi
+  else
+    nodist/code_coverage --stages 0-2
+  fi
+elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
+  ##############################################################################
+  # Run tests
+
+  export VERILATOR_TEST_NO_CONTRIBUTORS=1  # Separate workflow check
+
+  if [ "$CI_OS_NAME" = "osx" ]; then
+    export VERILATOR_TEST_NO_GDB=1  # Pain to get GDB to work on OS X
+    # TODO below may no longer be requried as configure checks for -pg
+    export VERILATOR_TEST_NO_GPROF=1  # Apple Clang has no -pg
+    # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd
+    file bin/verilator_bin
+    file bin/verilator_bin_dbg
+    md5 bin/verilator_bin
+    md5 bin/verilator_bin_dbg
+    stat bin/verilator_bin
+    stat bin/verilator_bin_dbg
+    # For some reason, the dbg exe is corrupted by this point ('file' reports
+    # it as data rather than a Mach-O). Unclear if this is an OS X issue or
+    # CI's. Remove the file and re-link...
+    rm bin/verilator_bin_dbg
+    "$MAKE" -j "$NPROC" -k
+  elif [ "$CI_OS_NAME" = "freebsd" ]; then
+    export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run
+    # TODO below may no longer be requried as configure checks for -pg
+    export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
+  fi
+
+  # Run sanitize on Ubuntu 20.04 only
+  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize=''
+
+  # Run the specified test
+  ccache -z
+  case $TESTS in
+    dist-vlt-0)
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=0/3
+      ;;
+    dist-vlt-1)
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=1/3
+      ;;
+    dist-vlt-2)
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=2/3
+      ;;
+    vltmt-0)
+      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=0/2
+      ;;
+    vltmt-1)
+      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=1/2
+      ;;
+    coverage-all)
+      nodist/code_coverage --stages 1-
+      ;;
+    coverage-dist)
+      nodist/code_coverage --stages 1- --scenarios=--dist
+      ;;
+    coverage-vlt-0)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=0/10
+      ;;
+    coverage-vlt-1)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=1/10
+      ;;
+    coverage-vlt-2)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=2/10
+      ;;
+    coverage-vlt-3)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=3/10
+      ;;
+    coverage-vlt-4)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=4/10
+      ;;
+    coverage-vlt-5)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=5/10
+      ;;
+    coverage-vlt-6)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=6/10
+      ;;
+    coverage-vlt-7)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=7/10
+      ;;
+    coverage-vlt-8)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=8/10
+      ;;
+    coverage-vlt-9)
+      nodist/code_coverage --stages 1- --scenarios=--vlt --hashset=9/10
+      ;;
+    coverage-vltmt-0)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=0/10
+      ;;
+    coverage-vltmt-1)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=1/10
+      ;;
+    coverage-vltmt-2)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=2/10
+      ;;
+    coverage-vltmt-3)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=3/10
+      ;;
+    coverage-vltmt-4)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=4/10
+      ;;
+    coverage-vltmt-5)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=5/10
+      ;;
+    coverage-vltmt-6)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=6/10
+      ;;
+    coverage-vltmt-7)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=7/10
+      ;;
+    coverage-vltmt-8)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=8/10
+      ;;
+    coverage-vltmt-9)
+      nodist/code_coverage --stages 1- --scenarios=--vltmt --hashset=9/10
+      ;;
+    *)
+      fatal "Unknown test: $TESTS"
+      ;;
+  esac
+  ccache -s
+
+  # Upload coverage data
+  if [[ $TESTS == coverage-* ]]; then
+    bash <(cat ci/coverage-upload.sh) -f nodist/obj_dir/coverage/app_total.info
+  fi
+else
+  ##############################################################################
+  # Unknown build stage
+  fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'"
+fi

ci/docker/buildenv/Dockerfile

@@ -40,7 +40,7 @@ RUN apt-get update \
 
 WORKDIR /tmp
 
-RUN cpan install -fi Unix::Processors Parallel::Forker Bit::Vector
+RUN cpan install -fi Parallel::Forker
 
 RUN git clone https://github.com/veripool/vcddiff.git && \
     make -C vcddiff && \

ci/docker/buildenv/README.adoc

@@ -1,49 +0,0 @@
-= Verilator Docker Build Environment
-
-This Verilator Build container is set up to compile and test a Verilator
-build. It uses the following parameters:
-
-* Source repository (default: https://github.com/verilator/verilator)
-* Source revision (default: master)
-* Compiler (GCC 9.3.0, clang 10.0.0, default: 9.3.0)
-
-The container is published as `verilator/verilator-buildenv` on
-https://hub.docker.com/repository/docker/verilator/verilator-buildenv[docker hub].
-
-To run the basic build using the current Verilator master:
-
-    docker run -ti verilator/verilator-buildenv
-
-To also run tests:
-
-    docker run -ti verilator/verilator-buildenv test
-
-To change the compiler:
-
-    docker run -ti -e CC=clang-10 -e CXX=clang++-10 verilator/verilator-buildenv test
-
-The tests that involve gdb are not working due to security restrictions.
-To run those too:
-
-....
-docker run -ti -e CC=clang-10 -e CXX=clang++-10 --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
-....
-
-Rather then building using a remote git repository you may prefer to use a
-working copy on the local filesystem. Mount the local working copy path as
-a volume and use that in place of git. When doing this be careful to have
-all changes committed to the local git area. To build the current HEAD from
-top of a repository:
-
-....
-docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
-....
-
-== Rebuilding
-
-To rebuild the Verilator-buildenv docker image, run:
-
-    docker build .
-
-This will also build SystemC under all supported compiler variants to
-reduce the SystemC testing time.

ci/docker/buildenv/README.rst

@@ -0,0 +1,63 @@
+Verilator Build Docker Container
+================================
+
+This Verilator Build Docker Container is set up to compile and test a
+Verilator build. It uses the following parameters:
+
+-  Source repository (default: https://github.com/verilator/verilator)
+
+-  Source revision (default: master)
+
+-  Compiler (GCC 9.3.0, clang 10.0.0, default: 9.3.0)
+
+The container is published as ``verilator/verilator-buildenv`` on `docker
+hub
+<https://hub.docker.com/repository/docker/verilator/verilator-buildenv>`__.
+
+To run the basic build using the current Verilator master:
+
+::
+
+   docker run -ti verilator/verilator-buildenv
+
+To also run tests:
+
+::
+
+   docker run -ti verilator/verilator-buildenv test
+
+To change the compiler:
+
+::
+
+   docker run -ti -e CC=clang-10 -e CXX=clang++-10 verilator/verilator-buildenv test
+
+The tests that involve gdb are not working due to security restrictions.
+To run those too:
+
+::
+
+   docker run -ti -e CC=clang-10 -e CXX=clang++-10 --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+
+Rather then building using a remote git repository you may prefer to use a
+working copy on the local filesystem. Mount the local working copy path as
+a volume and use that in place of git. When doing this be careful to have
+all changes committed to the local git area. To build the current HEAD from
+top of a repository:
+
+::
+
+   docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+
+
+Rebuilding
+----------
+
+To rebuild the Verilator-buildenv docker image, run:
+
+::
+
+   docker build .
+
+This will also build SystemC under all supported compiler variants to
+reduce the SystemC testing time.

ci/docker/run/README.adoc

@@ -1,59 +0,0 @@
-= Verilator Executable Docker Container
-
-The Verilator Executable Docker Container allows you to run Verilator
-easily as a docker image, e.g.:
-
-    docker run -ti verilator/verilator:latest --version
-
-This will install the container, run the latest Verilator and print
-Verilator's version.
-
-Containers are automatically built for all released versions, so you may
-easily compare results across versions, e.g.:
-
-    docker run -ti verilator/verilator:4.030 --version
-
-Verilator needs to read and write files on the local system.  To simplify
-this process, use the `verilator-docker` convenience script.  This script
-takes the version number, and all remaining arguments are passed through to
-Verilator. e.g.:
-
-    ./verilator-docker 4.030 --version
-
-or
-
-    ./verilator-docker 4.030 --cc test.v
-
-If you prefer not to use `verilator-docker` you must give the container
-access to your files as a volume with appropriate user rights.  For example
-to Verilate test.v:
-
-....
-docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v
-....
-
-This method can only access files below the current directory. An
-alternative is setup the volume `-workdir`.
-
-You can also work in the container by setting the entrypoint
-(don't forget to mount a volume if you want your work persistent):
-
-    docker run -ti --entrypoint /bin/bash verilator/verilator:latest
-
-You can also use the container to build Verilator at a specific
-commit:
-
-    docker build --build-arg SOURCE_COMMIT=<commit> .
-
-== Internals
-
-The Dockerfile builds Verilator and removes the tree when completed to
-reduce the image size. The entrypoint is set as a wrapper script
-(`verilator-wrap.sh`).  That script 1. calls Verilator, and 2. copies the
-Verilated runtime files to the `obj_dir` or the `-Mdir` respectively. This
-allows the user to have the files to they may later build the C++ output
-with the matching runtime files. The wrapper also patches the Verilated
-Makefile accordingly.
-
-There is also a hook defined that is run by docker hub via automated
-builds.

ci/docker/run/README.rst

@@ -0,0 +1,73 @@
+Verilator Executable Docker Container
+=====================================
+
+The Verilator Executable Docker Container allows you to run Verilator
+easily as a docker image, e.g.:
+
+::
+
+   docker run -ti verilator/verilator:latest --version
+
+This will install the container, run the latest Verilator and print
+Verilator's version.
+
+Containers are automatically built for all released versions, so you may
+easily compare results across versions, e.g.:
+
+::
+
+   docker run -ti verilator/verilator:4.030 --version
+
+Verilator needs to read and write files on the local system. To simplify
+this process, use the ``verilator-docker`` convenience script. This script
+takes the version number, and all remaining arguments are passed through to
+Verilator. e.g.:
+
+::
+
+   ./verilator-docker 4.030 --version
+
+or
+
+::
+
+   ./verilator-docker 4.030 --cc test.v
+
+If you prefer not to use ``verilator-docker`` you must give the container
+access to your files as a volume with appropriate user rights.  For example
+to Verilate test.v:
+
+::
+
+   docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v
+
+This method can only access files below the current directory. An
+alternative is setup the volume ``-workdir``.
+
+You can also work in the container by setting the entrypoint (don't forget
+to mount a volume if you want your work persistent):
+
+::
+
+   docker run -ti --entrypoint /bin/bash verilator/verilator:latest
+
+You can also use the container to build Verilator at a specific commit:
+
+::
+
+   docker build --build-arg SOURCE_COMMIT=<commit> .
+
+
+Internals
+---------
+
+The Dockerfile builds Verilator and removes the tree when completed to
+reduce the image size. The entrypoint is set as a wrapper script
+(``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
+Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
+respectively. This allows the user to have the files to they may later
+build the C++ output with the matching runtime files. The wrapper also
+patches the Verilated Makefile accordingly.
+
+There is also a hook defined that is run by docker hub via automated
+builds.

ci/docker/run/verilator-wrap.sh

@@ -27,5 +27,5 @@ if [ -e ${obj_dir} ]; then
     cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt
     cp -r /usr/local/share/verilator/include ${obj_dir}/vlt
     # Point Makefile to that folder
-    perl -i -pe 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk
+    sed -i 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk
 fi

ci/travis-ccache-size.bash

@@ -1,37 +0,0 @@
-#!/usr/bin/env bash
-# DESCRIPTION: Verilator: Travis CI ccache sizer
-#
-# Copyright 2020 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-################################################################################
-# This script computes the size of the ccache to be used for a job. We want the
-# ccache to be just big enough to be able to hold a whole build so a re-build
-# of the same does not miss in the cache due to capacity, but we don't want the
-# ccache too big as pulling it down from the network takes time, and it is
-# unlikely objects from much earlier builds would be useful.
-################################################################################
-
-fatal() {
-  echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
-}
-
-if [ "$TRAVIS_BUILD_STAGE_NAME" = "build" ]; then
-  if [ "$COVERAGE" == 1 ]; then
-    echo "1024M"
-  else
-    echo "768M"
-  fi
-elif [ "$TRAVIS_BUILD_STAGE_NAME" = "test" ]; then
-  if [[ $TESTS == coverage-* ]]; then
-    echo "1536M"
-  else
-    echo "256M"
-  fi
-else
-  fatal "Unknown build stage: '$TRAVIS_BUILD_STAGE_NAME'"
-fi

ci/travis-script.bash

@@ -1,134 +0,0 @@
-#!/usr/bin/env bash
-# DESCRIPTION: Verilator: Travis CI main job script
-#
-# Copyright 2020 by Geza Lore. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-#
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-################################################################################
-# This is the main script executed in the 'script' phase by all jobs. We use a
-# single script to keep the .travis.yml spec simple. We pass job parameters via
-# environment variables using 'env' keys. Having different 'env' keys in jobs
-# ensures they use different Travis build caches.
-################################################################################
-
-set -e
-set -x
-
-fatal() {
-  echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
-}
-
-if [ "$TRAVIS_OS_NAME" = "linux" ]; then
-  export MAKE=make
-  NPROC=$(nproc)
-elif [ "$TRAVIS_OS_NAME" = "osx" ]; then
-  export MAKE=make
-  NPROC=$(sysctl -n hw.logicalcpu)
-elif [ "$TRAVIS_OS_NAME" = "freebsd" ]; then
-  export MAKE=gmake
-  NPROC=$(sysctl -n hw.ncpu)
-else
-  fatal "Unknown os: '$TRAVIS_OS_NAME'"
-fi
-
-if [ "$TRAVIS_BUILD_STAGE_NAME" = "build" ]; then
-  ##############################################################################
-  # Build verilator
-
-  if [ "$COVERAGE" != 1 ]; then
-    autoconf
-    ./configure --enable-longtests --enable-ccwarn
-    "$MAKE" -j "$NPROC"
-    if [ "$TRAVIS_OS_NAME" = "osx" ]; then
-      file bin/verilator_bin
-      file bin/verilator_bin_dbg
-      md5 bin/verilator_bin
-      md5 bin/verilator_bin_dbg
-      stat bin/verilator_bin
-      stat bin/verilator_bin_dbg
-    fi
-  else
-    nodist/code_coverage --stages 1-2
-  fi
-elif [ "$TRAVIS_BUILD_STAGE_NAME" = "test" ]; then
-  ##############################################################################
-  # Run tests
-
-  if [ "$TRAVIS_OS_NAME" = "osx" ]; then
-    export VERILATOR_TEST_NO_GDB=1 # Pain to get GDB to work on OS X
-    export VERILATOR_TEST_NO_GPROF=1 # Apple Clang has no -pg
-    # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd
-    file bin/verilator_bin
-    file bin/verilator_bin_dbg
-    md5 bin/verilator_bin
-    md5 bin/verilator_bin_dbg
-    stat bin/verilator_bin
-    stat bin/verilator_bin_dbg
-    # For some reason, the dbg exe is corrupted by this point ('file' reports
-    # it as data rather than a Mach-O). Unclear if this is an OS X issue or
-    # one for Travis. Remove the file and re-link...
-    rm bin/verilator_bin_dbg
-    "$MAKE" -j "$NPROC"
-  elif [ "$TRAVIS_OS_NAME" = "freebsd" ]; then
-    export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run
-    export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
-  fi
-
-  # Run the specified test
-  case $TESTS in
-    dist-vlt-0)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt" DRIVER_HASHSET=--hashset=0/2
-      ;;
-    dist-vlt-1)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt" DRIVER_HASHSET=--hashset=1/2
-      ;;
-    vltmt-0)
-      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=0/2
-      ;;
-    vltmt-1)
-      "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=1/2
-      ;;
-    coverage-dist)
-      nodist/code_coverage --stages 3- --scenarios=--dist
-      ;;
-    coverage-vlt-0)
-      nodist/code_coverage --stages 3- --scenarios=--vlt --hashset=0/4
-      ;;
-    coverage-vlt-1)
-      nodist/code_coverage --stages 3- --scenarios=--vlt --hashset=1/4
-      ;;
-    coverage-vlt-2)
-      nodist/code_coverage --stages 3- --scenarios=--vlt --hashset=2/4
-      ;;
-    coverage-vlt-3)
-      nodist/code_coverage --stages 3- --scenarios=--vlt --hashset=3/4
-      ;;
-    coverage-vltmt-0)
-      nodist/code_coverage --stages 3- --scenarios=--vltmt --hashset=0/4
-      ;;
-    coverage-vltmt-1)
-      nodist/code_coverage --stages 3- --scenarios=--vltmt --hashset=1/4
-      ;;
-    coverage-vltmt-2)
-      nodist/code_coverage --stages 3- --scenarios=--vltmt --hashset=2/4
-      ;;
-    coverage-vltmt-3)
-      nodist/code_coverage --stages 3- --scenarios=--vltmt --hashset=3/4
-      ;;
-    *)
-      fatal "Unknown test: $TESTS"
-      ;;
-  esac
-  # Upload coverage data to codecov.io
-  if [[ $TESTS == coverage-* ]]; then
-    bash <(curl -s https://codecov.io/bash) -f nodist/obj_dir/coverage/app_total.info
-  fi
-else
-  ##############################################################################
-  # Unknown build stage
-  fatal "Unknown build stage: '$TRAVIS_BUILD_STAGE_NAME'"
-fi

codecov.yml

@@ -1,6 +1,6 @@
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2020 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2021 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -15,7 +15,7 @@ codecov:
 coverage:
   precision: 2
   round: down
-  range: "70...100"
+  range: "50...100"
   ignore:
     - "ci"
     - "docs"

configure.ac

@@ -1,13 +1,13 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[4.040 2020-08-15],
+AC_INIT([Verilator],[4.214 2021-10-17],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
@@ -15,12 +15,13 @@ AC_INIT([Verilator],[4.040 2020-08-15],
 # Then 'make maintainer-dist'
 
 AC_CONFIG_HEADER(src/config_build.h)
-AC_CONFIG_FILES(Makefile docs/Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
+AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
 
 # Version
 AC_MSG_RESULT([configuring for $PACKAGE_STRING])
 PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'`
 AC_SUBST(PACKAGE_VERSION_NUMBER)
+AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number])
 
 # Ignore automake flags passed by Ubuntu builds
 AC_ARG_ENABLE([dependency-tracking],
@@ -34,7 +35,7 @@ AC_ARG_ENABLE([silent-rules],
 AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary)
 AC_ARG_ENABLE([partial-static],
               [AS_HELP_STRING([--disable-partial-static],
-                              [By default, for Verilation peformance, Verilator
+                              [By default, for Verilation performance, Verilator
                                is linked against some of its dependencies
                                statically. Use this to link the Verilator binary
                                fully dynamically.])],
@@ -51,7 +52,7 @@ AC_MSG_CHECKING(whether to use tcmalloc)
 AC_ARG_ENABLE([tcmalloc],
               [AS_HELP_STRING([--enable-tcmalloc],
                               [Use libtcmalloc_minimal for faster dynamic memory
-                               management in Verilator binary@<:@default=check@:>@])],
+                               management in Verilator binary @<:@default=check@:>@])],
               [case "${enableval}" in
                 yes) CFG_WITH_TCMALLOC=yes ;;
                 no)  CFG_WITH_TCMALLOC=no ;;
@@ -60,6 +61,34 @@ AC_ARG_ENABLE([tcmalloc],
               [CFG_WITH_TCMALLOC=check;])
 AC_MSG_RESULT($CFG_WITH_TCMALLOC)
 
+# Flag to enable -m32 build
+AC_MSG_CHECKING(whether to use -m32)
+AC_ARG_ENABLE([m32],
+              [AS_HELP_STRING([--enable-m32],
+                              [Use -m32 for all compilation and link,
+                               including Verialtor and generated models.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_M32=yes ;;
+                no)  CFG_ENABLE_M32=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-m32]) ;;
+               esac],
+               CFG_ENABLE_M32=no)
+AC_MSG_RESULT($CFG_ENABLE_M32)
+
+# Flag to enable coverage build
+AC_MSG_CHECKING(whether to build for coverage collection)
+AC_ARG_ENABLE([coverage],
+              [AS_HELP_STRING([--enable-coverage],
+                              [Build Verilator for code coverage collection.
+                               For developers only.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_COVERAGE=yes ;;
+                no)  CFG_ENABLE_COVERAGE=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-coverage]) ;;
+               esac],
+               CFG_ENABLE_COVERAGE=no)
+AC_MSG_RESULT($CFG_ENABLE_COVERAGE)
+
 # Special Substitutions - CFG_WITH_DEFENV
 AC_MSG_CHECKING(whether to use hardcoded paths)
 AC_ARG_ENABLE([defenv],
@@ -113,22 +142,6 @@ AC_ARG_ENABLE([longtests],
 AC_SUBST(CFG_WITH_LONGTESTS)
 AC_MSG_RESULT($CFG_WITH_LONGTESTS)
 
-# CFG_WITH_PREC11
-AC_MSG_CHECKING(whether allow pre-C++11)
-AC_ARG_ENABLE([prec11-final],
-              [AS_HELP_STRING([--enable-prec11-final],
-                              [enable pre-C++11 compilers for Verilator binary
-                               and Verilated makefiles])],
-              [case "${enableval}" in
-                yes) CFG_WITH_PREC11=yes ;;
-                no)  CFG_WITH_PREC11=no ;;
-                *)   AC_MSG_ERROR([bad value ${enableval} for --enable-prec11-final]) ;;
-               esac],
-              [CFG_WITH_PREC11=no;]
-              )
-AC_SUBST(CFG_WITH_PREC11)
-AC_MSG_RESULT($CFG_WITH_PREC11)
-
 # Compiler flags (ensure they are not empty to avoid configure defaults)
 CFLAGS+=" "
 CPPFLAGS+=" "
@@ -150,11 +163,21 @@ AC_RUN_IFELSE(
     AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]),
     AC_MSG_RESULT(yes))
 
+AC_CHECK_PROG(AR,ar,ar)
+if test "x$AR" = "x" ; then
+   AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it])
+fi
+
 AC_PATH_PROG(PERL,perl)
 if test "x$PERL" = "x" ; then
    AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
 fi
 
+AC_PATH_PROG(PYTHON3,python3)
+if test "x$PYTHON3" = "x" ; then
+   AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it])
+fi
+
 AC_PATH_PROG(LEX,flex)
 if test "x$LEX" = "x" ; then
    AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it])
@@ -221,24 +244,34 @@ AC_DEFUN([_MY_CXX_CHECK_FLAG],
     CXXFLAGS="$ACO_SAVE_CXXFLAGS"
    ])
 
+AC_DEFUN([_MY_CXX_CHECK_IFELSE],
+   [# _MY_CXX_CHECK_IFELSE(option,action-if-supported,action-if-not-supported)
+    # Check if compiler supports specific option. If it does,
+    # do action-if-supported, otherwise do action-if-not-supported
+    _MY_CXX_CHECK_FLAG($1)
+    if test "$_my_result" = "yes" ; then
+      true
+      $2
+    else
+      true
+      $3
+    fi
+   ])
+
 AC_DEFUN([_MY_CXX_CHECK_SET],
-   [# _MY_CXX_CHECK_SET(variable,flag) -- Check if compiler supports specific options
-    # If it does, set variable to flag, only if not previously set
+   [# _MY_CXX_CHECK_SET(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # set variable to option, only if not previously set.
     if test "$$1" = ""; then
-       _MY_CXX_CHECK_FLAG($2)
-       if test "$_my_result" = "yes" ; then
-          $1="$2"
-       fi
+       _MY_CXX_CHECK_IFELSE($2, $1="$2")
     fi
    ])
 
 AC_DEFUN([_MY_CXX_CHECK_OPT],
-   [# _MY_CXX_CHECK_OPT(flag) -- Check if compiler supports specific options
-    # If it does, append flag to variable
-    _MY_CXX_CHECK_FLAG($2)
-    if test "$_my_result" = "yes" ; then
-       $1="$$1 $2"
-    fi
+   [# _MY_CXX_CHECK_OPT(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # append option to variable
+    _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
 AC_DEFUN([_MY_LDLIBS_CHECK_FLAG],
@@ -280,31 +313,52 @@ AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
     _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
+# When using -m32. Check this first as later checks may fail with the -m32 flag.
+if test "$CFG_ENABLE_M32" = "yes"; then
+  _MY_CXX_CHECK_IFELSE(
+    -m32,
+    [CXX="$CXX -m32"],
+    [AC_MSG_ERROR([--enable-m32 was given but compiler does not support -m32])])
+fi
+
+# Similarly, add the coverage flags early as they influence later checks.
+if test "$CFG_ENABLE_COVERAGE" = "yes"; then
+  _MY_CXX_CHECK_OPT(CXX,--coverage)
+  # Otherwise inline may not show as uncovered
+  #  If we use this then e.g. verilated.h functions properly show up
+  #  if unused.
+  #  However, VerilatedSerialize::write then changes from covered
+  #  to uncovered (in G++ 9.3.0) even with all inlining turned off.
+  #  Having false negative coverage is more effort then missing negatives.
+  #  Also this seems to explode the runtime (since a lot more data).
+  #  _MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions)
+  # Otherwise static may not show as uncovered
+  _MY_CXX_CHECK_OPT(CXX,-fkeep-static-functions)
+  # Exceptions can pollute the branch coverage data
+  _MY_CXX_CHECK_OPT(CXX,-fno-exceptions)
+  # Define-out some impossible stuff
+  _MY_CXX_CHECK_OPT(CXX,-DVL_GCOV)
+fi
+
+# Compiler flags to enable profiling
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PROFILE,-pg)
+AC_SUBST(CFG_CXXFLAGS_PROFILE)
+
 # Flag to select newest language standard supported
 # Macros work such that first option that passes is the one we take
-# gnu++17 code is clean, but SystemC in 2018 doesn't link with it (bug1339)
-# gnu++14 is the newest that Verilator supports
-# std++03 is the oldest that Verilator supports
+# Currently enabled c++14 due to packaged SystemC dependency
+# c++14 is the newest that Verilator is regressed to support
+# c++11 is the oldest that Verilator supports
+# gnu is requried for Cygwin to compile verilated.h successfully
+#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20)
+#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++03)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++03)
 AC_SUBST(CFG_CXXFLAGS_STD_NEWEST)
-# And likewise oldest standard (same list above, backwards)
-# This is used for internal testing
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++17)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++17)
-AC_SUBST(CFG_CXXFLAGS_STD_OLDEST)
 
 # Flags for compiling Verilator internals including parser, and Verilated files
 # These turn on extra warnings and are only used with 'configure --enable-ccwarn'
@@ -328,6 +382,18 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-parentheses-equality)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-unused)
 AC_SUBST(CFG_CXXFLAGS_PARSER)
 
+# Flags for compiling the debug version of Verilator (in addition to above CFG_CXXFLAGS_SRC)
+if test "$CFG_ENABLE_COVERAGE" = "no"; then # Do not optimize for the coverage build
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-Og)
+fi
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-ggdb)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_CXXFLAGS_DEBUG)
+
+# Flags for linking the debug version of Verilator (in addition to above CFG_LDFLAGS_SRC)
+_MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_LDFLAGS_DEBUG)
+
 # Flags for Verilated makefile
 # For example, -Wno-div-by-zero isn't in 4.1.2
 # Random code often does / 0.  Unfortunately VL_DIV_I(0,0) will warn
@@ -410,12 +476,17 @@ _MY_LDLIBS_CHECK_IFELSE(
    fi])
 AC_SUBST(CFG_LIBS)
 
-# Set CFG_WITH_THREADED if can support threading
-AC_MSG_CHECKING(whether $CXX supports Verilated threads)
-ACO_SAVE_CXXFLAGS="$CXXFLAGS"
-CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD_NEWEST $CFG_CXXFLAGS_NO_UNUSED"
-AC_LINK_IFELSE(
-     [AC_LANG_PROGRAM([#include <thread>], [[ ]])],
+# Need C++11 at least
+#Alternative: AX_CXX_COMPILE_STDCXX([11])
+AC_DEFUN([_MY_CXX_CHECK_CXX_VER],
+   [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++11
+    # Set $_my_result
+    AC_LINK_IFELSE(
+     [AC_LANG_PROGRAM([#include <thread>
+#if (__cplusplus < 201103L)
+# error "Too old"
+#endif
+    ], [[ ]])],
      [_my_result=yes
       if test -s conftest.err; then
         if grep -e "$1" conftest.err >/dev/null; then
@@ -423,24 +494,24 @@ AC_LINK_IFELSE(
         fi
       fi],
      [_my_result=no])
-CFG_WITH_THREADED=$_my_result
-AC_SUBST(CFG_WITH_THREADED)
-AC_MSG_RESULT($CFG_WITH_THREADED)
-CXXFLAGS="$ACO_SAVE_CXXFLAGS"
+   ])
 
-# Check compiler flag
-if test "$CFG_WITH_THREADED" = "no" ; then
-   if test "$CFG_WITH_PREC11" = "no" ; then
-      AC_MSG_NOTICE([[]])
-      AC_MSG_ERROR([[the $CXX compiler appears to not support C++11.
+AC_MSG_CHECKING(whether $CXX supports C++11)
+_MY_CXX_CHECK_CXX_VER()
+AC_MSG_RESULT($_my_result)
+if test "$_my_result" = "no" ; then
+   CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD_NEWEST"
+   CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD_NEWEST"
+   AC_MSG_CHECKING(whether $CXX supports C++11 with $CFG_CXXFLAGS_STD_NEWEST)
+   _MY_CXX_CHECK_CXX_VER()
+   AC_MSG_RESULT($_my_result)
+fi
+if test "$_my_result" = "no" ; then
+   AC_MSG_NOTICE([[]])
+   AC_MSG_ERROR([[the $CXX compiler appears to not support C++11.
 
-Verilator will require a C++11 or newer compiler for all releases starting
-September 2020.  Please investigate a C++11 build environment now so you
-will be ready.  Until then you may rerun configure with the
---enable-prec11-final argument to enable reduced functionality with such
-older compilers. Thanks.]])
+Verilator requires a C++11 or newer compiler.]])
 
-   fi
 fi
 
 # Checks for library functions.

docs/.gitignore

@@ -1,4 +1,4 @@
 *.1
 *.html
 *.pdf
-Makefile
+_build

docs/CONTRIBUTING.adoc

@@ -1,82 +0,0 @@
-= How to contribute to Verilator
-
-Thanks for using Verilator!  We welcome your contributions in whatever form.
-
-This contributing document contains some suggestions that may make
-contributions flow more efficiently.
-
-==== Did you find a bug?
-
-* Please **Ensure the bug was not already reported** by searching
-  https://verilator.org/issues[Verilator Issues].
-
-* If you're unable to find an open issue addressing the problem,
-  https://verilator.org/issues/new[open a new Verilator issue].
-
-** Be sure to include a **code sample** or an **executable test case**
-   demonstrating the bug and expected behavior that is not occurring.
-
-** The ideal example works against other simulators, and is in the
-   test_regress/t test format, as described in
-   link:internals.adoc[docs/internals].
-
-==== Did you write a patch that fixes a bug?
-
-* Please https://verilator.org/issues/new[Open a new issue].
-
-* You may attach a patch to the issue, or (preferred) may request a GitHub
-  pull request.
-
-** Verilator uses Travis CI to provide continuous integration. You may
-   want to setup Travis CI on your GitHub branch to ensure your changes
-   keep the tests passing.  See link:internals.adoc[docs/internals].
-
-* Your source-code contributions must be certified as open source, under
-  the https://developercertificate.org/[Developer Certificate of
-  Origin]. On your first contribution, you must either:
-
-** Have your patch include the addition of your name to
-   link:CONTRIBUTORS[docs/CONTRIBUTORS] (preferred).
-
-** Use "git -s" as part of your commit. This adds a "signed-of-by"
-   attribute which will certify your contribution as described in the
-   https://github.com/wking/signed-off-by/blob/master/Documentation/SubmittingPatches[Signed-of-By
-   convention].
-
-** Email, or post in an issue a statement that you certify your
-   contributions.
-
-** In any of these cases your name will be added to
-   link:CONTRIBUTORS[docs/CONTRIBUTORS] and you are agreeing all future
-   contributions are also certified.
-
-** We occasionally accept contributions where people do not want their name
-   published. Please email us; you must still privately certify your
-   contribution.
-
-* Your test contributions are generally considered released into the
-  Creative Commons Public Domain (CC0), unless you request otherwise or put
-  a GNU/Artistic license on your file.
-
-* Most important is we get your patch. If you'd like to clean up
-  indentation and related issues ahead of our feedback, that is
-  appreciated; please see the coding conventions in
-  link:internals.adoc[docs/internals].
-
-==== Do you have questions?
-
-* Please see FAQ section and rest of the
-  https://verilator.org/verilator_doc.html[Verilator manual],
-  or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)].
-
-* Ask any question in the
-  https://verilator.org/forum[Verilator forum].
-
-==== Code of Conduct
-
-* Our contributors and participants pledge to make participation in our
-  project and our community a positive experience for everyone.  We follow
-  the https://www.contributor-covenant.org/version/1/4/code-of-conduct.html[Contributor
-  Covenant version 1.4].
-
-Thanks!

docs/CONTRIBUTING.rst

@@ -0,0 +1,92 @@
+Contributing to Verilator
+=========================
+
+Thanks for using Verilator! We welcome your contributions in whatever form.
+
+This contributing document contains some suggestions that may make
+contributions flow more efficiently.
+
+
+Did you find a bug?
+-------------------
+
+- Please **Ensure the bug was not already reported** by searching
+  `Verilator Issues <https://verilator.org/issues>`__.
+
+- If you're unable to find an open issue addressing the problem, `open a
+  new Verilator issue <https://verilator.org/issues/new>`__.
+
+  - Be sure to include a **code sample** or an **executable test case**
+    demonstrating the bug and expected behavior that is not occurring.
+
+  - The ideal example works against other simulators, and is in the
+    test_regress/t test format, as described in `docs/internals
+    <internals.rst>`__.
+
+
+Did you write a patch that fixes a bug?
+---------------------------------------
+
+- Please `Open a new issue <https://verilator.org/issues/new>`__.
+
+- You may attach a patch to the issue, or (preferred) may request a
+  GitHub pull request.
+
+  - Verilator uses GitHub Actions to provide continuous integration.  You
+    may want to enable Actions on your GitHub branch to ensure your changes
+    keep the tests passing. See `docs/internals <internals.rst>`__.
+
+- Your source-code contributions must be certified as open source,
+  under the `Developer Certificate of
+  Origin <https://developercertificate.org/>`__. On your first
+  contribution, you must either:
+
+  - Have your patch include the addition of your name to `docs/CONTRIBUTORS
+    <CONTRIBUTORS>`__ (preferred).
+
+  - Use "git -s" as part of your commit. This adds a "signed-of-by"
+    attribute which will certify your contribution as described in the
+    `Signed-of-By convention
+    <https://github.com/wking/signed-off-by/blob/master/Documentation/SubmittingPatches>`__.
+
+  - Email, or post in an issue a statement that you certify your
+    contributions.
+
+  - In any of these cases your name will be added to `docs/CONTRIBUTORS
+    <CONTRIBUTORS>`__ and you are agreeing all future contributions are
+    also certified.
+
+  - We occasionally accept contributions where people do not want their
+    name published. Please email us; you must still privately certify your
+    contribution.
+
+- Your test contributions are generally considered released into the
+  Creative Commons Public Domain (CC0), unless you request otherwise or
+  put a GNU/Artistic license on your file.
+
+- Most important is we get your patch. If you’d like to clean up
+  indentation and related issues ahead of our feedback, that is
+  appreciated; please see the coding conventions in `docs/internals
+  <internals.rst>`__.
+
+
+Do you have questions?
+----------------------
+
+- Please see FAQ section and rest of the `Verilator
+  manual <https://verilator.org/verilator_doc.html>`__, or `Verilator
+  manual (PDF) <https://verilator.org/verilator_doc.pdf>`__.
+
+- Ask any question in the `Verilator forum
+  <https://verilator.org/forum>`__.
+
+
+Code of Conduct
+---------------
+
+- Our contributors and participants pledge to make participation in our
+  project and our community a positive experience for everyone. We follow
+  the `Contributor Covenant version 1.4
+  <https://www.contributor-covenant.org/version/1/4/code-of-conduct/>`__.
+
+Thanks!

docs/CONTRIBUTORS

@@ -5,69 +5,103 @@ Please see the Verilator manual for 200+ additional contributors. Thanks to all.
 
 Ahmed El-Mahmoudy
 Alex Chadwick
+Àlex Torregrosa
+Ameya Vikram Singh
+Andreas Kuster
 Chris Randall
 Conor McCullough
 Dan Petrisko
+Daniel Bates
 David Horton
+David Metz
 David Stanford
+David Turner
+Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
 Eric Rippey
 Fan Shupei
+Felix Yan
 Garrett Smith
 Geza Lore
 Gianfranco Costamagna
 Glen Gibb
+Graham Rushton
 Harald Heckmann
 Howard Su
 Huang Rui
+HyungKi Jeong
+Iru Cai
+Ivan Vnučec
 Iztok Jeras
 James Hanlon
 James Hutchinson
+James Pallister
 Jamey Hicks
 Jan Van Winkel
+Jean Berniolles
 Jeremy Bennett
 John Coiner
 John Demme
+Jonathan Drolet
 Josh Redford
 Julien Margetts
+Kaleb Barrett
 Kanad Kanhere
+Keith Colbert
 Kevin Kiningham
+Krzysztof Bieganski
 Kuba Ober
 Ludwig Rogiers
 Lukasz Dalek
 Maarten De Braekeleer
 Maciej Sobkowski
 Marco Widmer
+Markus Krause
+Marlon James
 Marshal Qiao
+Martin Schmidt
 Matthew Ballance
 Michael Killough
 Mike Popoloski
+Miodrag Milanović
+Morten Borup Petersen
+Nandu Raj
 Nathan Kohagen
 Nathan Myers
 Patrick Stewart
+Paul Wright
 Peter Horvath
 Peter Monsson
 Philipp Wagner
+Pierre-Henri Horrein
 Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
+Rafal Kapuscik
 Richard Myers
+Rupert Swarbrick
+Samuel Riedel
 Sean Cross
 Sebastien Van Cauwenberghe
 Sergi Granell
 Stefan Wallentowitz
 Stephen Henry
+Steven Hugg
 Tim Snyder
 Tobias Rosenkranz
 Tobias Wölfel
 Todd Strader
 Tomasz Gorochowik
 Tymoteusz Blazejczyk
+Udi Finkelstein
+Unai Martinez-Corral
 Vassilis Papaefstathiou
 Veripool API Bot
+Victor Besyakov
 Wilson Snyder
 Yossi Nivin
 Yuri Victorovich
 Yutetsu TAKATSUKASA
 Yves Mathieu
+Zhanglei Wang

docs/Makefile

@@ -0,0 +1,82 @@
+#*****************************************************************************
+# DESCRIPTION: Verilator documentation: Makefile pre-configure version
+#
+# This file is part of Verilator.
+#
+# Code available from: https://verilator.org
+#
+# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+#
+######################################################################
+#
+# This file is intended only to be called from the top-level Verilator Makefile.
+
+RST2HTML = rst2html
+PYTHON3 = python3
+DOXYGEN = doxygen
+SPHINXOPTS ?= -c guide
+SPHINXBUILD ?= sphinx-build
+
+SOURCEDIR = guide
+BUILDDIR = _build
+
+######################################################################
+
+.SUFFIXES:
+
+default:
+	@echo "error: make not supported here, run 'make docs' from Verilator top-level"
+
+######################################################################
+# Intermediate rules
+
+vl-extract: ../bin/verilator ../Changes
+	mkdir -p _build/gen
+	$(PYTHON3) bin/vl_sphinx_extract ../bin/verilator
+	sed 's/`/\&96;/g' < ../Changes > _build/gen/Changes
+
+######################################################################
+# HTML
+
+server: html
+	cd _build/html && $(PYTHON3) -m http.server
+
+%.html: %.rst
+	$(RST2HTML) $< $@
+
+######################################################################
+# PDF
+
+.PHONY: verilator.pdf
+
+verilator.pdf: pdf
+pdf:
+	$(MAKE) vl-extract
+	$(MAKE) latex
+	$(PYTHON3) bin/vl_sphinx_fix _build
+	$(MAKE) -C _build/latex
+	cp _build/latex/verilator.pdf ..
+
+######################################################################
+
+html latex linkcheck spelling::
+	$(MAKE) vl-extract
+	$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS)
+	$(PYTHON3) bin/vl_sphinx_fix _build
+
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS)
+
+clean mostlyclean distclean maintainer-clean::
+	rm -f $(SCRIPTS) *.tmp
+	rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
+	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
+	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
+	rm -f *.tex
+
+distclean maintainer-clean::
+	rm -f *.info* *.1 *.html *.pdf $(INFOS)

docs/Makefile.in

@@ -1,50 +0,0 @@
-#*****************************************************************************
-# DESCRIPTION: Verilator documentation: Makefile pre-configure version
-#
-# This file is part of Verilator.
-#
-# Code available from: https://verilator.org
-#
-#*****************************************************************************
-#
-# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-#
-#****************************************************************************/
-#
-# This file is intended only to be called from the top-level Verilator Makefile.
-
-#### Start of system configuration section. ####
-
-ASCIIDOCTOR = asciidoctor
-DOXYGEN = doxygen
-
-#### End of system configuration section. ####
-######################################################################
-
-.SUFFIXES:
-
-default:
-	@echo "error: make not supported here, run 'make docs' from Verilator top-level"
-
-%.html: %.adoc
-	$(ASCIIDOCTOR) $< -n -o $@
-
-clean mostlyclean distclean maintainer-clean::
-	rm -f $(SCRIPTS) *.tmp
-	rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
-	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
-	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
-	rm -f *.tex
-
-distclean maintainer-clean::
-	rm -f *.info* *.1 *.html *.pdf $(INFOS)
-	rm -f Makefile
-
-.PHONY: doxygen
-
-doxygen:
-	$(DOXYGEN) doxygen.config

docs/TODO

@@ -1,113 +0,0 @@
-// DESCRIPTION: Verilator: List of To Do issues.
-//
-// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can
-// redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License
-// Version 2.0.
-// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-* Language support:
-** Fix ordering of each bit separately in a signal (mips)
-   assign b[3:0] = b[7:4];  assign b[7:4] = in;
-** Support UDP gate primitives/ cell libraries
-   (have code for combos - problem is sequential udps)
-** Function to eval combo logic after /*verilator public*/ functions [gwaters]
-** Support generated clocks (correctness)
-** Recursive functions
-** Verilog configuration files
-** Expression coverage (see notes)
-** Better tristate support
-** UVM
-
-* Long-term Features
-** Assertions
-** Tristate support
-
-* Testing:
-** Code to make wrapper that sets signals, so can do comparison checks
-** New random program generator
-** Better graph viewer with search and zoom
-
-* Usability:
-** Detect and pre-remove most UNOPTFLATs
-** Better reporting of unopt problems, including what lines of code
-** Report more errors (all of them?) before exiting [Eugene Weber]
-** Auto-create scons config files
-** Print version/etc message at runtime. (4.000?)
-   Include number of lines of code, percent comments, code complexity measurement
-   <-80chars------------------------------------------------------------------->
-   Verilator 3.600 - The fast free open-sourced simulator.  Copyright 2001-2013.
-   Verilated #### modules, #### instances, ##### sigs,
-         #### non-comment lines, ##### ops, ### KB model size
-
-* Lint:
-** CDCRSTLOGIC should allow filtering with paths
-   "waive CDCRSTLOGIC --from a.b.sig  --to a.c.sig --via OR"
-
-* Internal Code:
-** A Visitor class that understands how to traverse data types
-** V3Graph should be templated container type, taking in Vertex + Edge types
-** Instead of string, have an VEncodedString/VIdString which contains __DOT__ish
-   things, to reduce bugs.  Also add _20 trailing space to \ encoded names.
-
-* Runtime:
-** New evalulation loop   ~/src/verilator/notes/event_loop.txt (4.000?)
-** Remove all private internal functions from top level wrapper header, move
-   to new level
-** Completely standalone simulation
-    main() records arguments for $test$plusvars
-    instantiates top,
-    does tracing  (support $dump?)
-    calls top->simulateForever()
-    exits
-
-* Performance:
-** Latch optimizations
-** Constant propagation
-   Extra cleaning AND:  1 & ((VARREF >> 1) | ((&VARREF >> 1) & VARREF))
-   Extra shift (perhaps due to clean): if (1 & CAST (VARREF >> #))
-** Gated clock and latch conversion to flops.  [JeanPaul Vanitegem]
-   Could propagate the AND into pos/negedges and let domaining optimize.
-** Negedge reset
-   Switch to remove negedges that don't matter
-   Can't remove async resets from control flops (like in syncronizers)
-** If all references to array have a constant index, blow up into separate signals-per-index
-** Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings.
-** Move _last sets and all other combo logic inside master
-   if() that triggers on all possible sense items
-** Rewrite and combine V3Life, V3Subst
-   If block temp only ever set in one place to constant, propagate it
-     Used in t_mem for array delayed assignments
-   Replace variables if set later in same cfunc branch
-     See for example duplicate sets of _narrow in cycle 90/91 of t_select_plusloop
-** Same assignment on both if branches
-   "if (a) { ... b=2; } else { ... b=2;}" -> "b=2; if ..."
-   Careful though, as b could appear in the statement or multiple times in statement
-   (Could just require exatly two 'b's in statement)
-** Simplify XOR/XNOR/AND/OR bit selection trees
-   Foo = A[1] ^ A[2] ^ A[3] etc are better as ^ ( A & 32'b...1110 )
-** Combine variables into wider elements
-   Parallel statements on different bits should become single signal
-   Variables that are always consumed in "parallel" can be joined
-** Duplicate assignments in gate optimization
-   Common to have many separate posedge blocks, each with identical
-   reset_r <= rst_in
-** If signal is used only once (not counting trace), always gate substitute
-   Don't merge if any combining would form circ logic (out goes back to in)
-** Multiple assignments each bit can become single assign with concat
-   Make sure a SEL of a CONCAT can get the single bit back.
-** Usually blocks/values
-   Enable only after certain time, so VL_TIME_I(32) > 0x1e gets eliminated out
-** Better ordering of a<=b, b<=c, put all refs to 'b' next to each other to optimize caching
-** I-cache packing improvements (what/how?)
-** Data cache organization (order of vars in class)
-   First have clocks,
-   then bools instead of uint32_t's
-   then based on what sense list they come from, all outputs, then all inputs
-   finally have any signals part of a "usually" block, or constant.
-** Rather then tracking widths, have a MSB...LSB of this expression
-   (or better, a bitmask of bits relevant in this expression)
-** Track recirculation and convert into clock-enables
-** Clock enables should become new clocking domains for speed
-** If floped(a) & flopped(b) and no other a&b, then instead flop(a&b).
-** Sort by output bitselects so can combine more assignments (see DDP example dx_dm signal)

docs/_static/css/vlt_sphinx.css

@@ -0,0 +1,25 @@
+/* Verilator blue #008fd7; set in html */
+
+.wy-side-nav-search > div.version {
+  color: #111;
+}
+
+.fa-github::before,
+.icon-github::before {
+  content: "";
+}
+
+.fa-home::before,
+.icon-home::before {
+  content: "";
+}
+
+.fa-arrow-circle-right::before,
+.icon-circle-arrow-right::before {
+  content: "";
+}
+
+.fa-arrow-circle-left::before,
+.icon-circle-arrow-left::before {
+  content: "";
+}

docs/bin/vl_sphinx_extract

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0201,R0903
+# -*- Python -*- See copyright, etc below
+######################################################################
+
+import argparse
+import re
+
+#######################################################################
+
+
+class VlSphinxExtract:
+    debug = 0
+    SkipBasenames = {}
+
+    def process(self, filename):
+        with open(filename) as fhr:
+            fhw = None
+            for line in fhr:
+                # =for VL_SPHINX_EXTRACT "file_to_write_to"
+                match = re.search(r'VL_SPHINX_EXTRACT +"([^"]+)"', line)
+                if match:
+                    outname = match.group(1)
+                    print("Writing %s" % outname)
+                    fhw = open(outname, "w")
+                    fhw.write(
+                        ".. comment: generated by vl_sphinx_extract from " +
+                        filename + "\n")
+                    fhw.write(".. code-block::\n")
+                elif re.match(r'^[=a-zA-Z0-9_]', line):
+                    fhw = None
+                elif fhw:
+                    fhw.write(line)
+
+
+#######################################################################
+
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Read a file and extract documentation data.""",
+    epilog=
+    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+you can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('path', help='path to extract from')
+Args = parser.parse_args()
+
+o = VlSphinxExtract()
+o.debug = Args.debug
+o.process(Args.path)
+
+######################################################################
+# Local Variables:
+# compile-command: "./vl_sphinx_extract --debug ../../bin/verilator"
+# End:

docs/bin/vl_sphinx_fix

@@ -0,0 +1,79 @@
+#!/usr/bin/env python3
+# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0903
+# -*- Python -*- See copyright, etc below
+######################################################################
+
+import argparse
+import os
+import re
+
+#######################################################################
+
+
+class VlSphinxFix:
+    debug = 0
+    SkipBasenames = {}
+
+    def process(self, path):
+        if os.path.isdir(path):
+            for basefile in os.listdir(path):
+                file = os.path.join(path, basefile)
+                if ((basefile != ".") and (basefile != "..")
+                        and basefile not in self.SkipBasenames
+                        and not os.path.islink(file)):
+                    self.process(file)
+        elif re.search(r'\.(html|tex)$', path):
+            self._edit(path)
+
+    def _edit(self, filename):
+        is_html = re.search(r'\.(html)$', filename)
+        with open(filename) as fhr:
+            origfile = fhr.read()
+            wholefile = origfile
+            # Option doesn't like spaces, so we use
+            # :option:`/*verilator&32;metacomment*/`
+            wholefile = re.sub(r'verilator-32-', r'verilator-', wholefile)
+            if is_html:
+                wholefile = re.sub(r'&32;', r' ', wholefile)
+                wholefile = re.sub(r'&96;', r'`', wholefile)
+            else:
+                wholefile = re.sub(r'&32;', r' ', wholefile)
+                wholefile = re.sub(r'&96;', r'`', wholefile)
+            if wholefile != origfile:
+                if self.debug:
+                    print("Edit %s" % filename)
+                tempname = filename + ".tmp"
+                with open(tempname, "w") as fhw:
+                    fhw.write(wholefile)
+                os.rename(tempname, filename)
+
+
+#######################################################################
+
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Post-process Sphinx HTML.""",
+    epilog=
+    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+you can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('path', help='path to edit')
+Args = parser.parse_args()
+
+o = VlSphinxFix()
+o.debug = Args.debug
+o.process(Args.path)
+
+######################################################################
+# Local Variables:
+# compile-command: "./vl_sphinx_fix --debug _build"
+# End:

docs/doxygen-mainpage

@@ -1,6 +0,0 @@
-/*! \mainpage Verilator Doxygen Documentation
- *
- * \section intro_sec Introduction
- *
- * This is a full doxygen analysis of the Verilator source tree.
- */

docs/gen/ex_DIDNOTCONVERGE_faulty.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block:: sv
+   :linenos:
+
+      always_comb b = ~a;
+      always_comb a = b;

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -0,0 +1,7 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block::
+
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request_1
+   -V{t#,#}        CHANGE: t/t_lint_didnotconverge_bad.v:14: a
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_didnotconverge_nodbg_bad
+.. code-block::
+
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_MULTIDRIVEN_faulty.rst

@@ -0,0 +1,11 @@
+.. comment: generated by t_lint_multidriven_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 2,5
+
+      always @(posedge clk) begin
+         out2[7:0] <= d0;  // <--- Warning
+      end
+      always @(negedge clk) begin
+         out2[15:8] <= d0;  // <--- Warning
+      end

docs/gen/ex_MULTIDRIVEN_msg.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_multidriven_bad
+.. code-block::
+
+   %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 'out2'
+                         example.v:1:7 ... Location of first driving block
+                         example.v:1:7 ... Location of other driving block

docs/gen/ex_STMTDLY_faulty.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block:: sv
+   :emphasize-lines: 1
+
+         #100 $finish;  //<--- Warning

docs/gen/ex_STMTDLY_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block::
+
+   %Warning-STMTDLY: example.v:1:8 Unsupported: Ignoring delay on this delayed statement.

docs/gen/ex_USERERROR_faulty.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block:: sv
+
+         $error("User elaboration-time error");

docs/gen/ex_USERERROR_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block::
+
+   %Warning-USERERROR: example.v:1:7 User elaboration-time error

docs/gen/ex_USERFATAL_faulty.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block:: sv
+
+         $fatal(0, "User elaboration-time fatal");

docs/gen/ex_USERFATAL_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block::
+
+   %Warning-USERFATAL: example.v:1:7 User elaboration-time fatal

docs/gen/ex_USERINFO_faulty.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block:: sv
+
+         $info("User elaboration-time info");

docs/gen/ex_USERINFO_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block::
+
+   -Info: example.v:1:7 User elaboration-time info

docs/gen/ex_USERWARN_faulty.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block:: sv
+
+         $warning("User elaboration-time warning");

docs/gen/ex_USERWARN_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_assert_comp_bad
+.. code-block::
+
+   %Warning-USERWARN: example.v:1:7 User elaboration-time warning

docs/gen/ex_VARHIDDEN_faulty.rst

@@ -0,0 +1,8 @@
+.. comment: generated by t_var_bad_hide_docs
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 2
+
+   module t;
+      integer t;  //<--- Warning ('t' hidden by module 't')
+   endmodule

docs/gen/ex_VARHIDDEN_msg.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_var_bad_hide_docs
+.. code-block::
+
+   %Warning-VARHIDDEN: example.v:2:12 Declaration of signal hides declaration in upper scope: 't'
+                       example.v:1:8 ... Location of original declaration

docs/gen/ex_WIDTH_1_faulty.rst

@@ -0,0 +1,8 @@
+.. comment: generated by t_lint_width_docs_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 3
+
+      int array[5];
+      bit [1:0] rd_addr;
+      wire int rd_value = array[rd_addr];  //<--- Warning

docs/gen/ex_WIDTH_1_fixed.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_lint_width_docs_bad
+.. code-block:: sv
+   :emphasize-lines: 1
+
+      wire int rd_value = array[{1'b0, rd_addr}];  //<--- Fixed

docs/gen/ex_WIDTH_1_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_width_docs_bad
+.. code-block::
+
+   %Warning-WIDTH: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits.

docs/guide/changes.rst

@@ -0,0 +1,16 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+****************
+Revision History
+****************
+
+.. COMMENT above header must use ### so there is an extra level of headers
+   here so the index won't show the huge list of revisions when clicking on
+   "Revision History" in the sidebar.
+
+Changes are contained in the :file:`Changes` file of the distribution, and
+also summarized below.  To subscribe to new versions see `Verilator
+Announcements <https://github.com/verilator/verilator-announce>`_.
+
+.. include:: ../_build/gen/Changes

docs/guide/conf.py

@@ -0,0 +1,228 @@
+# pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
+#
+# Configuration file for Verilator's Sphinx documentation builder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+#
+# This file only contains overridden options. For a full list:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+#
+# ----------------------------------------------------------------------
+# -- Path setup
+
+from datetime import datetime
+import os
+import re
+import sys
+sys.path.insert(0, os.path.abspath('./_ext'))
+
+import sphinx_rtd_theme  # pylint: disable=wrong-import-position,
+
+
+def get_vlt_version():
+    filename = "../../Makefile"
+    with open(filename) as fh:
+        for line in fh:
+            match = re.search(r"PACKAGE_VERSION_NUMBER *= *([a-z0-9.]+)", line)
+            if match:
+                return match.group(1)
+    return "unknown"
+
+
+def setup(app):
+    app.add_css_file('css/vlt_sphinx.css')
+
+
+# ----------------------------------------------------------------------
+# -- Project information
+
+project = 'Verilator'
+copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
+author = 'Wilson Snyder'
+
+# The master toctree document.
+master_doc = "index"
+
+version = get_vlt_version()
+release = get_vlt_version()
+
+rst_prolog = """
+.. role:: vlopt(option)
+"""
+
+# ----------------------------------------------------------------------
+# -- General configuration
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+# To install:
+#   sudo install enchant
+#   sudo pip3 install sphinx sphinx_rtd_theme breathe sphinxcontrib-spelling
+# We keep this list empty for now to avoid needing dependencies
+extensions = []
+# extensions = ['breathe', 'sphinxcontrib.spelling']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+    '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*',
+    'CONTRIBUTING.rst'
+]
+
+# Warn about refs
+nitpicky = True
+nitpicky_ignore = []
+
+# Number figures for referencing
+numfig = True
+
+# The name of the Pygments (syntax highlighting) style to use.
+pygments_style = "sphinx"
+
+# The suffix(es) of source filenames.
+# You can specify multiple suffix as a list of string:
+source_suffix = [".rst"]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# Date format to ISO
+today_fmt = datetime.now().strftime("%F")
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = True
+
+# Could use this for internals<->guide references
+# intersphinx_mapping = { 'sphinx': ('https://sphinx-doc.org/', None), }
+
+# ----------------------------------------------------------------------
+# -- Options for HTML output
+
+# html_baseurl =
+
+html_domain_indices = False
+
+html_logo = "../_static/verilator_192_150_min.png"
+
+html_theme = 'sphinx_rtd_theme'
+html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
+
+html_theme_options = {
+    'analytics_id': 'G-D27B0C9QEB',
+    'logo_only': True,
+    'style_nav_header_background': "#45acf8",  # Default is #2980B9
+    # 'canonical_url':
+}
+
+html_context = {
+    'display_github': True,
+    'github_user': 'verilator',
+    'github_repo': 'verilator',
+    'github_version': 'master/docs/guide/',
+}
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['../_static']
+
+# If true, "Created using Sphinx" is shown in the HTML footer. Default is True.
+html_show_sphinx = False
+
+html_copy_source = False
+html_show_sourcelink = False
+
+html_use_index = False
+
+html_favicon = "../_static/verilator_32x32_min.png"
+
+# Custom sidebar templates, maps document names to template names.
+# html_sidebars
+
+# Add any extra paths that contain custom files (such as robots.txt or
+# .htaccess) here, relative to this directory. These files are copied
+# directly to the root of the documentation.
+# html_extra_path = []
+
+# Additional templates that should be rendered to pages, maps page names to
+# template names.
+# html_additional_pages = {}
+
+# ----------------------------------------------------------------------
+# -- Options for Latex output
+
+latex_logo = "../_static/verilator_logo.png"
+
+latex_elements = {
+    'extraclassoptions': 'openany,oneside',
+    'papersize': 'letterpaper',
+    'makeindex': '',
+    'printindex': '',
+    # 'pointsize': '10pt',
+    # 'preamble': '',
+}
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+#  author, documentclass [howto, manual, or own class]).
+# latex_documents = [
+#    (
+#        master_doc,
+#        "Verilog-to-Routing.tex",
+#        "Verilog-to-Routing Documentation",
+#        "VTR Developers",
+#        "manual",
+#    ),
+# ]
+
+# For "manual" documents, if this is true, then toplevel headings are parts,
+# not chapters.
+# latex_use_parts = False
+
+# If true, show page references after internal links.
+# latex_show_pagerefs = False
+
+# If true, show URL addresses after external links.
+# latex_show_urls = False
+
+latex_domain_indices = False
+
+# ----------------------------------------------------------------------
+# -- Options for manual page output
+
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+# man_pages = [(master_doc, "verilog-to-routing", "Verilog-to-Routing Documentation", [author], 1)]
+
+# If true, show URL addresses after external links.
+# man_show_urls = False
+
+# ----------------------------------------------------------------------
+# -- Options for spelling
+
+spelling_word_list_filename = ['spelling.txt']
+spelling_ignore_contributor_names = True
+
+# ----------------------------------------------------------------------
+# -- Options for doxygen
+
+# if shutil.which("doxygen"):
+#    breathe_projects = {
+#        "verilated": "../_build/doxygen/verilated/xml",
+#    }
+#    breathe_default_project = "verilated"
+#
+#    if not os.environ.get("SKIP_DOXYGEN", None) == "True":
+#        for prjname, prjdir in breathe_projects.items():
+#            print("Generating doxygen files for {}...".format(prjname))
+#            os.makedirs(prjdir, exist_ok=True)
+#            cmd = "cd ../_doxygen && doxygen {}.dox".format(prjname)
+#            subprocess.call(cmd, shell=True)
+#    else:
+#        for prjname, prjdir in breathe_projects.items():
+#            assert os.path.exists(prjdir) == True, "Regenerate doxygen XML for {}".format(prjname)
+
+breathe_projects = {"verilated": "_build/doxygen/verilated/xml/"}
+breathe_default_project = "verilated"
+breathe_default_members = ('members')

docs/guide/connecting.rst

@@ -0,0 +1,516 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Connecting:
+
+******************************
+Connecting to Verilated Models
+******************************
+
+Structure of the Verilated Model
+================================
+
+Verilator outputs a :file:`{prefix}.h` header file which defines a class
+named :code:`{prefix}` which represents the generated model the user is
+supposed to instantiate.  This model class defines the interface of the
+Verilated model.
+
+Verilator will additionally create a :file:`{prefix}.cpp` file, together
+with additional .h and .cpp files for internals.  See the :file:`examples`
+directory in the kit for examples.  See :ref:`Files Read/Written` for
+information on all the files Verilator might output.
+
+The output of Verilator will contain a :file:`{prefix}.mk` file that may be
+used with Make to build a :file:`{prefix}__ALL.a` library with all required
+objects in it.
+
+The generated model class file manages all internal state required by the
+model, and exposes the following interface that allows interaction with the
+model:
+
+* Top level IO ports are exposed as references to the appropriate internal
+  equivalents.
+
+* Public top level module instances are exposed as pointers to allow access
+  to :code:`/* verilator public */` items.
+
+* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
+  exposed via the :code:`rootp` member pointer to allow access to model
+  internals, including :code:`/* verilator public_flat */` items.
+
+
+.. _Porting from pre 4.210:
+
+Model interface changes in version 4.210
+------------------------------------------
+
+Starting from version 4.210, the model class is an interface object.
+
+Up until Verilator version 4.204 inclusive, the generated model class was
+also the instance of the top level instance in the design hierarchy (what
+you would refer to with :code:`$root` in SystemVerilog).  This meant that
+all internal variables that were implemented by Verilator in the root scope
+were accessible as members of the model class itself.  Note there were often
+many such variable due to module inlining, including :code:`/* verilator
+public_flat */` items.
+
+This means that user code that accesses internal signals in the model
+(likely including :code:`/* verilator public_flat */` signals, as they are
+often inlined into the root scope) will need to be updated as follows:
+
+* No change required for accessing top level IO signals. These are directly
+  accessible in the model class via references.
+
+* No change required for accessing :code:`/* verilator public */` items.
+  These are directly accessible via sub-module pointers in the model class.
+
+* Accessing any other internal members, including
+  :code:`/* verilator public_flat */` items requires the following changes:
+
+  * Additionally include :file:`{prefix}___024root.h`. This header defines
+    type of the :code:`rootp` pointer within the model class. Note the
+    :code:`__024` substring is the Verilator escape sequence for the
+    :code:`$` character, i.e.: :code:`rootp` points to the Verilated
+    SystemVerilog :code:`$root` scope.
+
+  * Replace :code:`modelp->internal->member->lookup` references with
+    :code:`modelp->rootp->internal->member->lookup` references, which
+    contain one additional indirection via the :code:`rootp` pointer.
+
+
+.. _Connecting to C++:
+
+Connecting to C++
+=================
+
+In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
+simple C++ class.  The user must write a C++ wrapper and main loop for the
+simulation, which instantiates the model class, and link with the Verilated
+model.  Here is a simple example:
+
+.. code-block:: C++
+
+         #include <verilated.h>          // Defines common routines
+         #include <iostream>             // Need std::cout
+         #include "Vtop.h"               // From Verilating "top.v"
+
+         Vtop *top;                      // Instantiation of model
+
+         vluint64_t main_time = 0;       // Current simulation time
+         // This is a 64-bit integer to reduce wrap over issues and
+         // allow modulus.  This is in units of the timeprecision
+         // used in Verilog (or from --timescale-override)
+
+         double sc_time_stamp() {        // Called by $time in Verilog
+             return main_time;           // converts to double, to match
+                                         // what SystemC does
+         }
+
+         int main(int argc, char** argv) {
+             Verilated::commandArgs(argc, argv);   // Remember args
+
+             top = new Vtop;             // Create model
+
+             top->reset_l = 0;           // Set some inputs
+
+             while (!Verilated::gotFinish()) {
+                 if (main_time > 10) {
+                     top->reset_l = 1;   // Deassert reset
+                 }
+                 if ((main_time % 10) == 1) {
+                     top->clk = 1;       // Toggle clock
+                 }
+                 if ((main_time % 10) == 6) {
+                     top->clk = 0;
+                 }
+                 top->eval();            // Evaluate model
+                 cout << top->out << endl;       // Read a output
+                 main_time++;            // Time passes...
+             }
+
+             top->final();               // Done simulating
+             //    // (Though this example doesn't get here)
+             delete top;
+         }
+
+
+Note top level IO signals are read and written as members of the model.  You
+call the :code:`eval()` method to evaluate the model.  When the simulation is
+complete call the :code:`final()` method to execute any SystemVerilog final
+blocks, and complete any assertions. See :ref:`Evaluation Loop`.
+
+
+Connecting to SystemC
+=====================
+
+In SystemC output mode (:vlopt:`--sc`), the Verilator generated model class
+is a SystemC SC_MODULE.  This module will attach directly into a SystemC
+netlist as an instantiation.
+
+The SC_MODULE gets the same pinout as the Verilog module, with the
+following type conversions: Pins of a single bit become bool.  Pins 2-32
+bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
+vluint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
+become sc_bv's.  (Uints simulate the fastest so are used where possible.)
+
+Model internals, including lower level sub-modules are not pure SystemC
+code.  This is a feature, as using the SystemC pin interconnect scheme
+everywhere would reduce performance by an order of magnitude.
+
+
+Direct Programming Interface (DPI)
+==================================
+
+Verilator supports SystemVerilog Direct Programming Interface import and
+export statements.  Only the SystemVerilog form ("DPI-C") is supported, not
+the original Synopsys-only DPI.
+
+DPI Example
+-----------
+
+In the SYSTEMC example above, if you wanted to import C++ functions into
+Verilog, put in our.v:
+
+.. code-block::
+
+    import "DPI-C" function int add (input int a, input int b);
+
+    initial begin
+       $display("%x + %x = %x", 1, 2, add(1,2));
+    endtask
+
+Then after Verilating, Verilator will create a file Vour__Dpi.h with the
+prototype to call this function:
+
+.. code-block:: C++
+
+     extern int add(int a, int b);
+
+From the sc_main.cpp file (or another .cpp file passed to the Verilator
+command line, or the link), you'd then:
+
+.. code-block:: C++
+
+     #include "svdpi.h"
+     #include "Vour__Dpi.h"
+     int add(int a, int b) { return a+b; }
+
+
+DPI System Task/Functions
+-------------------------
+
+Verilator extends the DPI format to allow using the same scheme to
+efficiently add system functions.  Simply use a dollar-sign prefixed system
+function name for the import, but note it must be escaped.
+
+.. code-block:: sv
+
+    export "DPI-C" function integer \$myRand;
+
+    initial $display("myRand=%d", $myRand());
+
+Going the other direction, you can export Verilog tasks so they can be
+called from C++:
+
+.. code-block:: sv
+
+    export "DPI-C" task publicSetBool;
+
+    task publicSetBool;
+       input bit in_bool;
+       var_bool = in_bool;
+    endtask
+
+Then after Verilating, Verilator will create a file Vour__Dpi.h with the
+prototype to call this function:
+
+.. code-block:: C++
+
+     extern void publicSetBool(svBit in_bool);
+
+From the sc_main.cpp file, you'd then:
+
+.. code-block:: C++
+
+     #include "Vour__Dpi.h"
+     publicSetBool(value);
+
+Or, alternatively, call the function under the design class.  This isn't
+DPI compatible but is easier to read and better supports multiple designs.
+
+.. code-block:: C++
+
+     #include "Vour__Dpi.h"
+     Vour::publicSetBool(value);
+     // or top->publicSetBool(value);
+
+Note that if the DPI task or function accesses any register or net within
+the RTL, it will require a scope to be set. This can be done using the
+standard functions within svdpi.h, after the module is instantiated, but
+before the task(s) and/or function(s) are called.
+
+For example, if the top level module is instantiated with the name "dut"
+and the name references within tasks are all hierarchical (dotted) names
+with respect to that top level module, then the scope could be set with
+
+.. code-block:: C++
+
+     #include "svdpi.h"
+     ...
+     svSetScope(svGetScopeFromName("TOP.dut"));
+
+(Remember that Verilator adds a "TOP" to the top of the module hierarchy.)
+
+Scope can also be set from within a DPI imported C function that has been
+called from Verilog by querying the scope of that function. See the
+sections on DPI Context Functions and DPI Header Isolation below and the
+comments within the svdpi.h header for more information.
+
+
+DPI Imports that access signals
+-------------------------------
+
+If a DPI import accesses a signal through the VPI Verilator will not be
+able to know what variables are accessed and may schedule the code
+inappropriately.  Ideally pass the values as inputs/outputs so the VPI is
+not required.  Alternatively a workaround is to use a non-inlined task as a
+wrapper:
+
+.. code-block::
+
+     logic din;
+
+     // This DPI function will read "din"
+     import "DPI-C" context function void dpi_that_accesses_din();
+
+     always @(...)
+        dpi_din_args(din);
+
+     task dpi_din_args(input din);
+        /* verilator no_inline_task */
+        dpi_that_accesses_din();
+     endtask
+
+
+DPI Display Functions
+---------------------
+
+Verilator allows writing $display like functions using this syntax:
+
+.. code-block::
+
+    import "DPI-C" function void
+          \$my_display(input string formatted /*verilator sformat*/ );
+
+The :option:`/*verilator&32;sformat*/` metacomment indicates that this
+function accepts a $display like format specifier followed by any number of
+arguments to satisfy the format.
+
+
+DPI Context Functions
+---------------------
+
+Verilator supports IEEE DPI Context Functions.  Context imports pass the
+simulator context, including calling scope name, and filename and line
+number to the C code.  For example, in Verilog:
+
+.. code-block::
+
+    import "DPI-C" context function int dpic_line();
+    initial $display("This is line %d, again, line %d\n", `line, dpic_line());
+
+This will call C++ code which may then use the svGet\* functions to read
+information, in this case the line number of the Verilog statement that
+invoked the dpic_line function:
+
+.. code-block:: C++
+
+    int dpic_line() {
+        // Get a scope:  svScope scope = svGetScope();
+
+        const char* scopenamep = svGetNameFromScope(scope);
+        assert(scopenamep);
+
+        const char* filenamep = "";
+        int lineno = 0;
+        if (svGetCallerInfo(&filenamep, &lineno)) {
+            printf("dpic_line called from scope %s on line %d\n",
+               scopenamep, lineno);
+            return lineno;
+        } else {
+            return 0;
+        }
+    }
+
+See the IEEE Standard for more information.
+
+
+DPI Header Isolation
+--------------------
+
+Verilator places the IEEE standard header files such as svdpi.h into a
+separate include directory, vltstd (VeriLaTor STandarD).  When compiling
+most applications $VERILATOR_ROOT/include/vltstd would be in the include
+path along with the normal $VERILATOR_ROOT/include.  However, when
+compiling Verilated models into other simulators which have their own
+svdpi.h and similar standard files with different contents, the vltstd
+directory should not be included to prevent picking up incompatible
+definitions.
+
+
+Public Functions
+----------------
+
+Instead of DPI exporting, there's also Verilator public functions, which
+are slightly faster, but less compatible.
+
+
+Verification Procedural Interface (VPI)
+=======================================
+
+Verilator supports a limited subset of the VPI.  This subset allows
+inspection, examination, value change callbacks, and depositing of values
+to public signals only.
+
+VPI is enabled with the Verilator :vlopt:`--vpi` option.
+
+To access signals via the VPI, Verilator must be told exactly which signals
+are to be accessed.  This is done using the Verilator public pragmas
+documented below.
+
+Verilator has an important difference from an event based simulator; signal
+values that are changed by the VPI will not immediately propagate their
+values, instead the top level header file's :code:`eval()` method must be
+called.  Normally this would be part of the normal evaluation (i.e. the
+next clock edge), not as part of the value change.  This makes the
+performance of VPI routines extremely fast compared to event based
+simulators, but can confuse some test-benches that expect immediate
+propagation.
+
+Note the VPI by its specified implementation will always be much slower
+than accessing the Verilator values by direct reference
+(structure->module->signame), as the VPI accessors perform lookup in
+functions at simulation runtime requiring at best hundreds of instructions,
+while the direct references are evaluated by the compiler and result in
+only a couple of instructions.
+
+For signal callbacks to work the main loop of the program must call
+:code:`VerilatedVpi::callValueCbs()`.
+
+
+.. _VPI Example:
+
+VPI Example
+-----------
+
+In the below example, we have readme marked read-only, and writeme which if
+written from outside the model will have the same semantics as if it
+changed on the specified clock edge.
+
+.. code-block:: bash
+
+     cat >our.v <<'EOF'
+       module our (input clk);
+          reg readme   /*verilator public_flat_rd*/;
+          reg writeme  /*verilator public_flat_rw @(posedge clk) */;
+          initial $finish;
+       endmodule
+     EOF
+
+There are many online tutorials and books on the VPI, but an example that
+accesses the above signal "readme" would be:
+
+.. code-block:: bash
+
+     cat >sim_main.cpp <<'<<EOF'
+       #include "Vour.h"
+       #include "verilated.h"
+       #include "verilated_vpi.h"  // Required to get definitions
+
+       vluint64_t main_time = 0;   // See comments in first example
+       double sc_time_stamp() { return main_time; }
+
+       void read_and_check() {
+           vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8*)"TOP.our.readme", NULL);
+           if (!vh1) vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
+           const char* name = vpi_get_str(vpiName, vh1);
+           printf("Module name: %s\n", name);  // Prints "readme"
+
+           s_vpi_value v;
+           v.format = vpiIntVal;
+           vpi_get_value(vh1, &v);
+           printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
+       }
+
+       int main(int argc, char** argv, char** env) {
+           Verilated::commandArgs(argc, argv);
+           Vour* top = new Vour;
+           Verilated::internalsDump();  // See scopes to help debug
+           while (!Verilated::gotFinish()) {
+               top->eval();
+               VerilatedVpi::callValueCbs();  // For signal callbacks
+               read_and_check();
+           }
+           delete top;
+           return 0;
+       }
+     EOF
+
+
+.. _Evaluation Loop:
+
+Wrappers and Model Evaluation Loop
+==================================
+
+When using SystemC, evaluation of the Verilated model is managed by the
+SystemC kernel, and for the most part can be ignored.  When using C++, the
+user must call :code:`eval()`, or :code:`eval_step()` and
+:code:`eval_end_step()`.
+
+1. When there is a single design instantiated at the C++ level that needs
+to evaluate within a given context, call :code:`designp->eval()`.
+
+2. When there are multiple designs instantiated at the C++ level that need
+to evaluate within a context, call :code:`first_designp->eval_step()` then
+:code:`->eval_step()` on all other designs.  Then call
+:code:`->eval_end_step()` on the first design then all other designs.  If
+there is only a single design, you would call :code:`eval_step()` then
+:code:`eval_end_step()`; in fact :code:`eval()` described above is just a
+wrapper which calls these two functions.
+
+When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for
+changes in clock signals and evaluates related sequential always blocks,
+such as computing always_ff @ (posedge...) outputs.  Then Verilator
+evaluates combinatorial logic.
+
+Note combinatorial logic is not computed before sequential always blocks
+are computed (for speed reasons). Therefore it is best to set any non-clock
+inputs up with a separate :code:`eval()` call before changing clocks.
+
+Alternatively, if all always_ff statements use only the posedge of clocks,
+or all inputs go directly to always_ff statements, as is typical, then you
+can change non-clock inputs on the negative edge of the input clock, which
+will be faster as there will be fewer :code:`eval()` calls.
+
+For more information on evaluation, see :file:`docs/internals.rst` in the
+distribution.
+
+
+Verilated and VerilatedContext
+==============================
+
+Multiple Verilated models may be part of the same simulation context, that
+is share a VPI interface, sense of time, and common settings.  This common
+simulation context information is stored in a ``VerilatedContext``
+structure.  If a ``VerilatedContext`` is not created prior to creating a
+model, a default global one is created automatically.
+
+The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
+shown above, simply call VerilatedContext methods using the default global
+VerilatedContext.  (Technically they operate on the last one used by a
+given thread.)  If you are using multiple simulation contexts you should
+not use the Verilated:: methods, and instead always use VerilatedContext
+methods called on the appropriate VerilatedContext object.
+
+For methods available under Verilated and VerilatedContext see
+:file:`include/verilated.h` in the distribution.

docs/guide/contributing.rst

@@ -0,0 +1,68 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+*******************************
+Contributing and Reporting Bugs
+*******************************
+
+Announcements
+=============
+
+To get notified of new releases and other important announcements, go to
+`Verilator announcement repository
+<https://github.com/verilator/verilator-announce>`__ and follow the
+instructions there.
+
+
+Reporting Bugs
+==============
+
+First, check the :ref:`Language Limitations` section.
+
+Next, try the :vlopt:`--debug` option.  This will enable additional
+internal assertions, and may help identify the problem.
+
+Finally, reduce your code to the smallest possible routine that exhibits
+the bug.  Even better, create a test in the :file:`test_regress/t`
+directory, as follows:
+
+.. code-block:: bash
+
+       cd test_regress
+       cp -p t/t_EXAMPLE.pl t/t_BUG.pl
+       cp -p t/t_EXAMPLE.v t/t_BUG.v
+
+There are many hints on how to write a good test in the
+:file:`test_regress/driver.pl` documentation which can be seen by running:
+
+.. code-block:: bash
+
+       cd $VERILATOR_ROOT  # Need the original distribution kit
+       test_regress/driver.pl --help
+
+Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want
+in the Verilog code there; just make sure it retains the single clk input
+and no outputs.  Now, the following should fail:
+
+.. code-block:: bash
+
+       cd $VERILATOR_ROOT  # Need the original distribution kit
+       cd test_regress
+       t/t_BUG.pl  # Run on Verilator
+       t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator
+       t/t_BUG.pl --vcs  # Run on VCS simulator
+       t/t_BUG.pl --nc|--iv|--ghdl  # Likewise on other simulators
+
+The test driver accepts a number of options, many of which mirror the main
+Verilator options. For example the previous test could have been run with
+debugging enabled.  The full set of test options can be seen by running
+:command:`driver.pl --help` as shown above.
+
+Finally, report the bug at `Verilator Issues
+<https://verilator.org/issues>`_.  The bug will become publicly visible; if
+this is unacceptable, mail the bug report to ``[email protected]``.
+
+
+.. Contributing
+.. ============
+.. include:: ../CONTRIBUTING.rst

docs/guide/contributors.rst

@@ -0,0 +1,156 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+************************
+Contributors and Origins
+************************
+
+Authors
+=======
+
+When possible, please instead report bugs at `Verilator Issues
+<https://verilator.org/issues>`_.
+
+Primary author is Wilson Snyder <[email protected]>.
+
+Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
+Takatsukasa, and Jie Xu.
+
+
+Contributors
+============
+
+Many people have provided ideas and other assistance with Verilator.
+
+Verilator is receiving major development support from the `CHIPS Alliance
+<https://chipsalliance.org>`_.
+
+Previous major corporate sponsors of Verilator, by providing significant
+contributions of time or funds included include: Atmel Corporation, Cavium
+Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
+Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
+Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
+and SiCortex Inc.
+
+The people who have contributed major functionality are: Byron Bradley,
+Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd
+Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder.
+Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David
+Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van
+Cauwenberghe, Gene Weber, and Clifford Wolf.
+
+Some of the people who have provided ideas, and feedback for Verilator
+include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm,
+Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew
+Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael
+Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof
+Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black,
+Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard,
+Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie
+Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher,
+Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal
+Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark,
+Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean
+Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh
+Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme,
+Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny
+Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler,
+Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar
+E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud,
+Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric
+LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein,
+Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner,
+Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl,
+Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew
+Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner,
+Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil
+Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto,
+Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen
+Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki
+Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae
+Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da
+Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver,
+Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok
+Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike
+Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi,
+Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf
+Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan
+Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot
+Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce,
+Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David
+Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve
+Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor
+Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul
+Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan
+Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien
+Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves
+Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick,
+Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis
+Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris
+Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon,
+Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz,
+Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad
+Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall,
+Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter,
+Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu
+Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic
+Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig
+Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis
+Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu
+Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan
+Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim
+Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov,
+Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson,
+Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki,
+Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun,
+Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe,
+Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede,
+Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar,
+Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner,
+Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien
+Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri
+Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan
+Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene
+Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel
+Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise,
+Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding
+Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and
+Keyi Zhang.
+
+Thanks to them, and all those we've missed including above, or wished to
+remain anonymous.
+
+Historical Origins
+==================
+
+Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
+Digital Equipment Corporation.  The Verilog code that was converted to C
+was then merged with a C based CPU model of the Alpha processor and
+simulated in a C based environment called CCLI.
+
+In 1995 Verilator started being used also for Multimedia and Network
+Processor development inside Digital.  Duane Galbi took over active
+development of Verilator, and added several performance enhancements.  CCLI
+was still being used as the shell.
+
+In 1998, through the efforts of existing DECies, mainly Duane Galbi,
+Digital graciously agreed to release the source code.  (Subject to the code
+not being resold, which is compatible with the GNU Public License.)
+
+In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called
+it Verilator2.  This was the first packaged public release.
+
+In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
+scratch in C++.  This added many optimizations, yielding about a 2-5x
+performance gain.
+
+In 2009, major SystemVerilog and DPI language support was added.
+
+In 2018, Verilator 4.000 was released with multithreaded support.
+
+In 2019, Verilator joined the `CHIPS Alliance
+<https://chipsalliance.org>`_.
+
+Currently, various language features and performance enhancements are added
+as the need arises.  Verilator is now about 3x faster than in 2002, and is
+faster than most (if not every) other simulator.

docs/guide/copyright.rst

@@ -0,0 +1,19 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+*********
+Copyright
+*********
+
+The latest version of Verilator is available from `https://verilator.org
+<https://verilator.org>`_.
+
+Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify the Verilator internals under the terms
+of either the GNU Lesser General Public License Version 3 or the Perl
+Artistic License Version 2.0.
+
+All Verilog and C++/SystemC code quoted within this documentation file are
+released as Creative Commons Public Domain (CC0).  Many example files and
+test files are likewise released under CC0 into effectively the Public
+Domain as described in the files themselves.

docs/guide/deprecations.rst

@@ -0,0 +1,25 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+Deprecations
+============
+
+The following deprecated items are scheduled for future removal:
+
+C++11 compiler support
+  Verilator currently requires C++11 or newer compilers.  Verilator will
+  require C++14 or newer compilers for both compiling Verilator and
+  compiling Verilated models no sooner than January 2022.
+
+Verilated_heavy.h
+  The legacy "verilated_heavy.h" include was replaced with just including
+  "verilated.h". Verilated_heavy.h is planned for removal no sooner than
+  July 2022.
+
+Configuration File -msg
+  The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule"
+  option.  "-msg" is planned for removal no sooner than January 2021.
+
+XML locations
+  The XML "fl" attribute has been replaced with the "loc" attribute.  "fl"
+  is planned for removal no sooner than January 2021.

docs/guide/environment.rst

@@ -0,0 +1,93 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+Environment
+===========
+
+This section describes the environment variables used by Verilator and
+associated programs.
+
+.. option:: LD_LIBRARY_PATH
+
+   A generic Linux/OS variable specifying what directories have shared
+   object (.so) files.  This path should include SystemC and any other
+   shared objects needed at simulation runtime.
+
+.. option:: MAKE
+
+   Names the executable of the make command invoked when using the
+   :vlopt:`--build` option.  Some operating systems may require "gmake" to
+   this variable to launch GNU make.  If this variable is not specified,
+   "make" is used.
+
+.. option:: OBJCACHE
+
+   Optionally specifies a caching or distribution program to place in front
+   of all runs of the C++ compiler.  For example, "ccache".  If using
+   :command:`distcc` or :command:`icecc`/:command:`icecream`, they would
+   generally be run under :command:`ccache`; see the documentation for
+   those programs.  If OBJCACHE is not set, and at configure time ccache
+   was present, ccache will be used as a default.
+
+.. option:: SYSTEMC
+
+   Deprecated.  Used only if :option:`SYSTEMC_INCLUDE` or
+   :option:`SYSTEMC_LIBDIR` is not set.  If set, specifies the directory
+   containing the SystemC distribution.  If not specified, it will come
+   from a default optionally specified at configure time (before Verilator
+   was compiled).
+
+.. option:: SYSTEMC_ARCH
+
+   Deprecated.  Used only if :option:`SYSTEMC_LIBDIR` is not set.
+   Specifies the architecture name used by the SystemC kit.  This is the
+   part after the dash in the "lib-{...}" directory name created by a
+   :command:`make` in the SystemC distribution.  If not set, Verilator will
+   try to intuit the proper setting, or use the default optionally
+   specified at configure time (before Verilator was compiled).
+
+.. option:: SYSTEMC_CXX_FLAGS
+
+   Specifies additional flags that are required to be passed to GCC when
+   building the SystemC model.  System 2.3.0 may need this set to
+   "-pthread".
+
+.. option:: SYSTEMC_INCLUDE
+
+   If set, specifies the directory containing the systemc.h header file. If
+   not specified, it will come from a default optionally specified at
+   configure time (before Verilator was compiled), or computed from
+   SYSTEMC/include.
+
+.. option:: SYSTEMC_LIBDIR
+
+   If set, specifies the directory containing the libsystemc.a library. If
+   not specified, it will come from a default optionally specified at
+   configure time (before Verilator was compiled), or computed from
+   SYSTEMC/lib-SYSTEMC_ARCH.
+
+.. option:: VERILATOR_BIN
+
+   If set, specifies an alternative name of the ``verilator`` binary.  May
+   be used for debugging and selecting between multiple operating system
+   builds.
+
+.. option:: VERILATOR_COVERAGE_BIN
+
+   If set, specifies an alternative name of the ``verilator_coverage``
+   binary.  May be used for debugging and selecting between multiple
+   operating system builds.
+
+.. option:: VERILATOR_GDB
+
+   If set, the command to run when using the :vlopt:`--gdb` option, such as
+   "ddd".  If not specified, it will use "gdb".
+
+.. option:: VERILATOR_ROOT
+
+   Specifies the directory containing the distribution kit.  This is used
+   to find the executable, Perl library, and include files.  If not
+   specified, it will come from a default optionally specified at configure
+   time (before Verilator was compiled).  It should not be specified if
+   using a pre-compiled Verilator package as the hard-coded value should be
+   correct.  See :ref:`Installation`.

docs/guide/example_cc.rst

@@ -0,0 +1,92 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Example C++ Execution:
+
+Example C++ Execution
+=====================
+
+We'll compile this example into C++.  For an extended and commented version
+of what this C++ code is doing, see
+:file:`examples/make_tracing_c/sim_main.cpp` in the distribution.
+
+.. include:: example_common_install.rst
+
+Now, let's create an example Verilog, and C++ wrapper file:
+
+.. code-block:: bash
+
+     mkdir test_our
+     cd test_our
+
+     cat >our.v <<'EOF'
+       module our;
+          initial begin $display("Hello World"); $finish; end
+       endmodule
+     EOF
+
+     cat >sim_main.cpp <<'EOF'
+       #include "Vour.h"
+       #include "verilated.h"
+       int main(int argc, char** argv, char** env) {
+           VerilatedContext* contextp = new VerilatedContext;
+           contextp->commandArgs(argc, argv);
+           Vour* top = new Vour{contextp};
+           while (!contextp->gotFinish()) { top->eval(); }
+           delete top;
+           delete contextp;
+           return 0;
+       }
+     EOF
+
+Now we run Verilator on our little example.
+
+.. code-block:: bash
+
+     verilator -Wall --cc --exe --build sim_main.cpp our.v
+
+Breaking this command down:
+
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings
+   enabled.
+
+#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC
+   or only linting).
+
+#. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so
+   the build will create an executable instead of only a library.
+
+#. :vlopt:`--build` so Verilator will call make itself. This is we don't
+   need to manually call make as a separate step. You can also write your
+   own compile rules, and run make yourself as we show in :ref:`Example
+   SystemC Execution`.)
+
+#. An finally, :command:`our.v` which is our SystemVerilog design file.
+
+Once Verilator completes we can see the generated C++ code under the
+:file:`obj_dir` directory.
+
+.. code-block:: bash
+
+     ls -l obj_dir
+
+(See :ref:`Files Read/Written` for descriptions of some of the files that
+were created.)
+
+And now we run it:
+
+.. code-block:: bash
+
+     obj_dir/Vour
+
+And we get as output:
+
+.. code-block:: bash
+
+     Hello World
+     - our.v:2: Verilog $finish
+
+Really, you're better off using a Makefile to run the steps for you so when
+your source changes it will automatically run all of the appropriate steps.
+To aid this Verilator can create a makefile dependency file.  For examples
+that do this see the :file:`examples` directory in the distribution.

docs/guide/example_common_install.rst

@@ -0,0 +1,16 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+First you need Verilator installed, see :ref:`Installation`. In brief, if
+you installed Verilator using the package manager of your operating system,
+or did a :command:`make install` to place Verilator into your default path,
+you do not need anything special in your environment, and should not have
+VERILATOR_ROOT set.  However, if you installed Verilator from sources and
+want to run Verilator out of where you compiled Verilator, you need to
+point to the kit:
+
+.. code-block:: bash
+
+     # See above; don't do this if using an OS-distributed Verilator
+     export VERILATOR_ROOT=/path/to/where/verilator/was/installed
+     export PATH=$VERILATOR_ROOT/bin:$PATH

docs/guide/example_dist.rst

@@ -0,0 +1,40 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Examples in the Distribution:
+
+Examples in the Distribution
+============================
+
+See the ``examples/`` directory that is part of the distribution, and
+is installed (in a OS-specific place, often in e.g.
+``/usr/local/share/verilator/examples``).  These examples include:
+
+examples/make_hello_c
+   Example GNU-make simple Verilog->C++ conversion
+examples/make_hello_sc
+   Example GNU-make simple Verilog->SystemC conversion
+examples/make_tracing_c
+   Example GNU-make Verilog->C++ with tracing
+examples/make_tracing_sc
+   Example GNU-make Verilog->SystemC with tracing
+examples/make_protect_lib
+   Example using --protect-lib
+examples/cmake_hello_c
+   Example building make_hello_c with CMake
+examples/cmake_hello_sc
+   Example building make_hello_sc with CMake
+examples/cmake_tracing_c
+   Example building make_tracing_c with CMake
+examples/cmake_tracing_sc
+   Example building make_tracing_sc with CMake
+examples/cmake_protect_lib
+   Example building make_protect_lib with CMake
+
+To run an example copy the example to a new directory and run it.
+
+::
+
+      cp -rp {path_to}/examples/make_hello_c make_hello_c
+      cd make_hello_c
+      make

docs/guide/example_sc.rst

@@ -0,0 +1,73 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Example SystemC Execution:
+
+Example SystemC Execution
+=========================
+
+This is an example similar to the :ref:`Example C++ Execution`, but using
+SystemC. We'll also explicitly run make.
+
+.. include:: example_common_install.rst
+
+Now, let's create an example Verilog, and SystemC wrapper file:
+
+.. code-block:: bash
+
+     mkdir test_our_sc
+     cd test_our_sc
+
+     cat >our.v <<'EOF'
+       module our (clk);
+          input clk;  // Clock is required to get initial activation
+          always @(posedge clk)
+             begin $display("Hello World"); $finish; end
+       endmodule
+     EOF
+
+     cat >sc_main.cpp <<'EOF'
+       #include "Vour.h"
+       int sc_main(int argc, char** argv) {
+           Verilated::commandArgs(argc, argv);
+           sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
+           Vour* top = new Vour{"top"};
+           top->clk(clk);
+           while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
+           delete top;
+           return 0;
+       }
+     EOF
+
+Now we run Verilator on our little example:
+
+.. code-block:: bash
+
+     verilator -Wall --sc --exe sc_main.cpp our.v
+
+This example does not use --build, therefore we need to explicitly compile
+it:
+
+.. code-block:: bash
+
+     make -j -C obj_dir -f Vour.mk Vour
+
+And now we run it:
+
+.. code-block:: bash
+
+     obj_dir/Vour
+
+And we get, after the SystemC banner, the same output as the C++ example:
+
+.. code-block:: bash
+
+     SystemC 2.3.3-Accellera
+
+     Hello World
+     - our.v:4: Verilog $finish
+
+Really, you're better off using a Makefile to run the steps for you so when
+your source changes it will automatically run all of the appropriate steps.
+For examples that do this see the :file:`examples` directory in the
+distribution.

docs/guide/examples.rst

@@ -0,0 +1,22 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Examples:
+
+========
+Examples
+========
+
+This section covers the following examples:
+
+* :ref:`Example C++ Execution`
+* :ref:`Example SystemC Execution`
+* :ref:`Examples in the Distribution`
+
+.. toctree::
+   :maxdepth: 1
+   :hidden:
+
+   example_cc.rst
+   example_sc.rst
+   example_dist.rst

docs/guide/exe_sim.rst

@@ -0,0 +1,95 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Simulation Runtime Arguments:
+
+Simulation Runtime Arguments
+============================
+
+The following are the arguments that may be passed to a Verilated
+executable, provided that executable calls
+:code:`Verilated::commandArgs()`.
+
+All simulation runtime arguments begin with "+verilator", so that the
+user's executable may skip over all "+verilator" arguments when parsing its
+command line.
+
+Summary:
+
+   .. include:: ../_build/gen/args_verilated.rst
+
+
+.. option:: +verilator+debug
+
+   Enable simulation runtime debugging.  Equivalent to
+   :vlopt:`+verilator+debugi+4 <+verilator+debugi+\<value\>>`.
+
+.. option:: +verilator+debugi+<value>
+
+   Enable simulation runtime debugging at the provided level.
+
+.. option:: +verilator+error+limit+<value>
+
+   Set number of non-fatal errors (e.g. assertion failures) before exiting
+   simulation runtime. Also affects number of $stop calls needed before
+   exit. Defaults to 1.
+
+.. option:: +verilator+help
+
+   Display help and exit.
+
+.. option:: +verilator+prof+threads+file+<filename>
+
+   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   simulation runtime filename to dump to.  Defaults to
+   :file:`profile_threads.dat`.
+
+.. option:: +verilator+prof+threads+start+<value>
+
+   When a model was Verilated using :vlopt:`--prof-threads`, the simulation
+   runtime will wait until $time is at this value (expressed in units of
+   the time precision), then start the profiling warmup, then
+   capturing. Generally this should be set to some time that is well within
+   the normal operation of the simulation, i.e. outside of reset. If 0, the
+   dump is disabled. Defaults to 1.
+
+.. option:: +verilator+prof+threads+window+<value>
+
+   When a model was Verilated using :vlopt:`--prof-threads`, after $time
+   reaches :vlopt:`+verilator+prof+threads+start+\<value\>`, Verilator will
+   warm up the profiling for this number of eval() calls, then will capture
+   the profiling of this number of eval() calls.  Defaults to 2, which
+   makes sense for a single-clock-domain module where it's typical to want
+   to capture one posedge eval() and one negedge eval().
+
+.. option:: +verilator+prof+vlt+file+<filename>
+
+   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   profile-guided optimization data runtime filename to dump to.  Defaults
+   to :file:`profile.vlt`.
+
+.. option:: +verilator+rand+reset+<value>
+
+   When a model was Verilated using :vlopt:`--x-initial unique
+   <--x-initial>`, sets the simulation runtime initialization technique.  0
+   = Reset to zeros. 1 = Reset to all-ones.  2 = Randomize.  See
+   :ref:`Unknown States`.
+
+.. option:: +verilator+seed+<value>
+
+   For $random and :vlopt:`--x-initial unique <--x-initial>`, set the
+   simulation runtime random seed value.  If zero or not specified picks a
+   value from the system random number generator.
+
+.. option:: +verilator+noassert
+
+   Disable assert checking per runtime argument. This is the same as
+   calling :code:`Verilated::assertOn(false)` in the model.
+
+.. option:: +verilator+V
+
+   Shows the verbose version, including configuration information.
+
+.. option:: +verilator+version
+
+   Displays program version and exits.

docs/guide/exe_verilator_coverage.rst

@@ -0,0 +1,114 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+verilator_coverage
+==================
+
+Verilator_coverage processes Verilated model-generated coverage reports.
+
+With --annotate, it reads the specified coverage data file and generates
+annotated source code with coverage metrics annotated.  If multiple
+coverage points exist on the same source code line, additional lines will
+be inserted to report the additional points.
+
+Additional Verilog-XL-style standard arguments specify the search paths
+necessary to find the source code that the coverage analysis was performed
+on.
+
+To filter those items to be included in coverage, you may read
+logs/coverage.dat into an editor and do a M-x keep-lines to include only
+those statistics of interest and save to a new .dat file.
+
+For Verilog conditions that should never occur, either add a $stop
+statement to the appropriate statement block, or see
+:option:`/*verilator&32;coverage_off*/`.  This will remove the coverage
+points after the model is re-Verilated.
+
+For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`.
+
+
+verilator_coverage Example Usage
+--------------------------------
+
+..
+
+    verilator_coverage --help
+    verilator_coverage --version
+
+    verilator_coverage --annotate <obj>
+
+    verilator_coverage  -write merged.dat -read <datafiles>...
+
+    verilator_coverage  -write-info merged.info -read <datafiles>...
+
+
+verilator_coverage Arguments
+----------------------------
+
+.. program:: verilator_coverage
+
+.. option:: <filename>
+
+Specifies the input coverage data file.  Multiple filenames may be provided
+to read multiple inputs.  If no data file is specified, by default
+"coverage.dat" will be read.
+
+.. option:: --annotate <output_directory>
+
+Specifies the directory name that source files with annotated coverage data
+should be written to.
+
+.. option:: --annotate-all
+
+Specifies all files should be shown.  By default, only those source files
+which have low coverage are written to the output directory.
+
+.. option:: --annotate-min <count>
+
+Specifies if the coverage point does not include the count number of
+coverage hits, then the coverage point will be considered above the
+threashold, and the coverage report will put a "%" to indicate the coverage
+is not sufficient.  Defaults to 10.
+
+.. option:: --help
+
+Displays a help summary, the program version, and exits.
+
+.. option:: --rank
+
+Prints an experimental report listing the relative importance of each test
+in covering all of the coverage points.  The report shows "Covered" which
+indicates the number of points that test covers; a test is considered to
+cover a point if it has a bucket count of at least 1. The "rank" column has
+a higher number t indicate the test is more important, and rank 0 means the
+test does not need to be run to cover the points.  "RankPts" indicates the
+number of coverage points this test will contribute to overall coverage if
+all tests are run in the order of highest to lowest rank.
+
+.. option:: --unlink
+
+With :option:`--write`, unlink all input files after the output
+has been successfully created.
+
+.. option:: --version
+
+Displays program version and exits.
+
+.. option:: --write <filename>
+
+Specifies the aggregate coverage results, summed across all the files,
+should be written to the given filename in verilator_coverage data format.
+This is useful for use in scripts to combine many coverage data files
+(likely generated from random test runs) into one master coverage file.
+
+.. option:: --write-info <filename.info>
+
+Specifies the aggregate coverage results, summed across all the files,
+should be written to the given filename in :command:`lcov` .info format.
+This may be used to feed into :command:`lcov` to aggregate or generate
+reports.
+
+The info format loses data compared to the Verilator coverage data format;
+the info will all forms of coverage converted to line style coverage, and
+if there are multiple coverage points on a single line, the minimum
+coverage across those points will be used to report coverage of the line.

docs/guide/exe_verilator_gantt.rst

@@ -0,0 +1,87 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+verilator_gantt
+===============
+
+Verilator_gantt creates a visual representation to help analyze Verilator
+multithreaded simulation performance, by showing when each macro-task
+starts and ends, and showing when each thread is busy or idle.
+
+For an overview of use of verilator_gantt, see :ref:`Profiling`.
+
+Gantt Chart VCD
+---------------
+
+Verilated_gnatt creates a value change dump (VCD) format dump file which
+may be viewed in a waveform viewer (e.g. C<GTKWave>):
+
+.. figure:: figures/fig_gantt_min.png
+
+   Example verilator_gantt output, as viewed with GTKWave.
+
+The viewed waveform chart has time on the X-axis, with one unit for each
+time tick of the system's high-performance counter.
+
+
+Gantt Chart VCD Signals
+-----------------------
+
+In waveforms there are the following signals. In GTKWave, using a data
+format of "decimal" will remove the leading zeros and make the traces
+easier to read.
+
+evals
+  Increments each time when eval_step was measured to be active.  This
+  allow visualization of how much time eval_step was active.
+
+eval_loop
+  Increments each time when the evaluation loop within eval_step was
+  measured to be active.  For best performance there is only a single
+  evaluation loop within each eval_step call, that is the eval_loop
+  waveform looks identical to the evals waveform.
+
+measured_parallelism
+  The number of mtasks active at this time, for best performance this will
+  match the thread count. In GTKWave, use a data format of "analog step" to
+  view this signal.
+
+predicted_parallelism
+  The number of mtasks Verilator predicted would be active at this time,
+  for best performance this will match the thread count. In GTKWave, use a
+  data format of "analog step" to view this signal.
+
+cpu#_thread
+  For the given CPU number, the thread number measured to be executing.
+
+mtask#_cpu
+  For the given mtask id, the CPU it was measured to execute on.
+
+thread#_mtask
+  For the given thread number, the mtask id it was executing.
+
+predicted_thread#_mtask
+  For the given thread number, the mtask id Verilator predicted would be
+  executing.
+
+
+verilator_gantt Arguments
+-------------------------
+
+.. program:: verilator_gantt
+
+.. option:: <filename>
+
+The filename to read data from, defaults to "profile_threads.dat".
+
+.. option:: --help
+
+Displays a help summary, the program version, and exits.
+
+.. option:: --no-vcd
+
+Disables creating a .vcd file.
+
+.. option:: --vcd <filename>
+
+Sets the output filename for vcd dump. Default is "verilator_gantt.vcd".

docs/guide/exe_verilator_profcfunc.rst

@@ -0,0 +1,29 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+verilator_profcfunc
+===================
+
+Verilator_profcfunc reads a profile report created by gprof.  The names of
+the functions are then transformed, assuming the user used Verilator's
+--prof-cfuncs, and a report printed showing the percentage of time, etc, in
+each Verilog block.
+
+Due to rounding errors in gprof reports, the input report's percentages may
+not total to 100%.  In the verilator_profcfunc report this will get
+reported as a rounding error.
+
+For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
+
+verilator_profcfunc Arguments
+-----------------------------
+
+.. program:: verilator_profcfunc
+
+.. option:: <filename>
+
+The :command:`gprof`-generated filename to read data from. Typically "gprof.out".
+
+.. option:: --help
+
+Displays a help summary, the program version, and exits.

docs/guide/executables.rst

@@ -0,0 +1,19 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+*********************************
+Executable and Argument Reference
+*********************************
+
+This section describes the executables that are part of Verilator, and the
+options to each executable.
+
+.. toctree::
+   :maxdepth: 1
+   :hidden:
+
+   exe_verilator.rst
+   exe_verilator_coverage.rst
+   exe_verilator_gantt.rst
+   exe_verilator_profcfunc.rst
+   exe_sim.rst

docs/guide/extensions.rst

@@ -0,0 +1,495 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+*******************
+Language Extensions
+*******************
+
+The following additional constructs are the extensions Verilator supports
+on top of standard Verilog code.  Using these features outside of comments
+or "`ifdef`"'s may break other tools.
+
+.. option:: `__FILE__
+
+   The :option:`\`__FILE__` define expands to the current filename as a
+   string, like C++'s __FILE__.  This Verilator feature added in 2006 was
+   incorporated into the IEEE 1800-2009 standard.
+
+.. option:: `__LINE__
+
+   The :option:`\`__LINE__` define expands to the current filename as a
+   string, like C++'s __LINE__.  This Verilator feature added in 2006 was
+   incorporated into the IEEE 1800-2009 standard.
+
+.. option:: `error [string]
+
+   This will report an error when encountered, like C++'s #error.
+
+.. option:: $c([string], ...);
+
+   The string will be embedded directly in the output C++ code at the point
+   where the surrounding Verilog code is compiled.  It may either be a
+   standalone statement (with a trailing ; in the string), or a function
+   that returns up to a 32-bit number (without a trailing ;). This can be
+   used to call C++ functions from your Verilog code.
+
+   String arguments will be put directly into the output C++ code, except
+   the word 'this' (i.e.: the object pointer) might be replaced with a
+   different pointer as Verilator might implement logic with non-member
+   functions. For this reason, any references to class members must be made
+   via an explicit 'this->' pointer dereference.
+
+   Expression arguments will have the code to evaluate the expression
+   inserted.  Thus to call a C++ function, :code:`$c("func(",a,")")` will
+   result in :code:`func(a)` in the output C++ code.  For input arguments,
+   rather than hard-coding variable names in the string
+   :code:`$c("func(a)")`, instead pass the variable as an expression
+   ::code:`$c("func(",a,")")`.  This will allow the call to work inside
+   Verilog functions where the variable is flattened out, and also enable
+   other optimizations.
+
+   If you will be reading or writing any Verilog variables inside the C++
+   functions, the Verilog signals must be declared with
+   :option:`/*verilator&32;public*/` metacomments.
+
+   You may also append an arbitrary number to $c, generally the width of
+   the output; :code:`signal_32_bits = $c32("...");`.  This allows for
+   compatibility with other simulators which require a differently named
+   PLI function name for each different output width.
+
+.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
+
+   Format arguments may use C fprintf sizes after the % escape.  Per the
+   Verilog standard, %x prints a number with the natural width, and %0x
+   prints a number with minimum width.  Verilator extends this so %5x
+   prints 5 digits per the C standard (this is unspecified in Verilog, but
+   was incorporated into the 1800-2009).
+
+.. option:: `coverage_block_off
+
+   Specifies the entire begin/end block should be ignored for coverage
+   analysis.  Must be inside a code block, e.g. within a begin/end pair.
+   Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
+
+.. option:: `systemc_header
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the output .h file's header.  Must be placed as a module
+   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   this macro, this also works in pure C++ code.
+
+.. option:: `systemc_ctor
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class constructor.  Must be placed as a module
+   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   this macro, this also works in pure C++ code.
+
+.. option:: `systemc_dtor
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class destructor.  Must be placed as a module
+   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   this macro, this also works in pure C++ code.
+
+.. option:: `systemc_interface
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the C++ class interface.  Must be placed as a module item,
+   e.g. directly inside a module/endmodule pair. Despite the name of this
+   macro, this also works in pure C++ code.
+
+.. option:: `systemc_imp_header
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into the header of all files for this C++ class implementation.
+   Must be placed as a module item, e.g. directly inside a module/endmodule
+   pair. Despite the name of this macro, this also works in pure C++ code.
+
+.. option:: `systemc_implementation
+
+   Take remaining text up to the next :option:`\`verilog` or
+   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
+   verbatim into a single file of the C++ class implementation.  Must be
+   placed as a module item, e.g. directly inside a module/endmodule
+   pair. Despite the name of this macro, this also works in pure C++ code.
+
+   If you will be reading or writing any Verilog variables in the C++
+   functions, the Verilog signals must be declared with a
+   :option:`/*verilator&32;public*/` metacomment.  See also the public task
+   feature; writing an accessor may result in cleaner code.
+
+.. option:: `SYSTEMVERILOG
+
+   The SYSTEMVERILOG, SV_COV_START and related standard defines are set by
+   default when :vlopt:`--language <--language>` is "1800-\*".
+
+.. option:: `VERILATOR
+
+.. option:: `verilator
+
+.. option:: `verilator3
+
+   The VERILATOR, verilator and verilator3 defines are set by default so
+   you may "\`ifdef" around tool specific constructs.
+
+.. option:: `verilator_config
+
+   Take remaining text up to the next :option:`\`verilog` mode switch and
+   treat it as Verilator configuration commands.  See :ref:`Configuration Files`.
+
+.. option:: `verilog
+
+   Switch back to processing Verilog code after a
+   :option:`\`systemc_... <\`systemc_header>` mode switch.  The Verilog
+   code returns to the last language mode specified with
+   "\`begin_keywords", or SystemVerilog if none was specified.
+
+.. option:: /*verilator&32;clock_enable*/
+
+   Used after a signal declaration to indicate the signal is used to gate a
+   clock, and the user takes responsibility for insuring there are no races
+   related to it. (Typically by adding a latch, and running static timing
+   analysis.) For example:
+
+   .. code-block:: sv
+
+         reg enable_r /*verilator clock_enable*/;
+         wire gated_clk = clk & enable_r;
+         always_ff @(posedge clk)
+            enable_r <= enable_early;
+
+   The clock_enable attribute will cause the clock gate to be ignored in
+   the scheduling algorithm, sometimes required for correct clock behavior,
+   and always improving performance.  It's also a good idea to enable the
+   :option:`IMPERFECTSCH` warning, to ensure all clock enables are properly
+   recognized.
+
+   Same as :option:`clock_enable` configuration file option.
+
+.. option:: /*verilator&32;clocker*/
+
+.. option:: /*verilator&32;no_clocker*/
+
+   Used after a signal declaration to indicate the signal is used as clock
+   or not. This information is used by Verilator to mark the signal as
+   clocker and propagate the clocker attribute automatically to derived
+   signals. See :vlopt:`--clk`.
+
+   Same as :option:`clocker` and :option:`no_clocker` in configuration
+   files.
+
+.. option:: /*verilator&32;coverage_block_off*/
+
+   Specifies the entire begin/end block should be ignored for coverage
+   analysis purposes.
+
+   Same as :option:`coverage_block_off` configuration file option.
+
+.. option:: /*verilator&32;coverage_off*/
+
+   Specifies that following lines of code should have coverage disabled.
+   Often used to ignore an entire module for coverage analysis purposes.
+
+.. option:: /*verilator&32;coverage_on*/
+
+   Specifies that following lines of code should have coverage re-enabled
+   (if appropriate :vlopt:`--coverage` flags are passed) after being
+   disabled earlier with :option:`/*verilator&32;coverage_off*/`.
+
+
+.. _verilator_hier_block:
+
+.. option:: /*verilator&32;hier_block*/
+
+   Specifies that the module is a unit of hierarchical Verilation.  This
+   metacomment must be between :code:`module module_name(...);` and
+   :code:`endmodule`.  The module will not be inlined nor uniquified for
+   each instance in hierarchical Verilation.  Note that the metacomment is
+   ignored unless the :vlopt:`--hierarchical` option is specified.
+
+   See :ref:`Hierarchical Verilation`.
+
+.. option:: /*verilator&32;inline_module*/
+
+   Specifies the module the comment appears in may be inlined into any
+   modules that use this module.  This is useful to speed up simulation
+   runtime.  Note if using :vlopt:`--public` that signals under inlined
+   submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++
+   does not allow "." in signal names.
+
+   Same as :option:`inline` configuration file option.
+
+.. option:: /*verilator&32;isolate_assignments*/
+
+   Used after a signal declaration to indicate the assignments to this
+   signal in any blocks should be isolated into new blocks.  When there is
+   a large combinatorial block that is resulting in an ``UNOPTFLAT``
+   warning, attaching this to the signal causing a false loop may clear up
+   the problem.
+
+   IE, with the following:
+
+   .. code-block:: sv
+
+         reg splitme /* verilator isolate_assignments*/;
+         // Note the placement of the semicolon above
+         always_comb begin
+           if (....) begin
+              splitme = ....;
+              other assignments
+           end
+         end
+
+   Verilator will internally split the block that assigns to "splitme" into
+   two blocks:
+
+   It would then internally break it into (sort of):
+
+   .. code-block:: sv
+
+         // All assignments excluding those to splitme
+         always_comb begin
+           if (....) begin
+              other assignments
+           end
+         end
+         // All assignments to splitme
+         always_comb begin
+           if (....) begin
+              splitme = ....;
+           end
+         end
+
+   Same as :option:`isolate_assignments` configuration file option.
+
+.. option:: /*verilator&32;lint_off <msg>*/
+
+   Disable the specified warning message for any warnings following the
+   comment.
+
+.. option:: /*verilator&32;lint_on <msg>*/
+
+   Re-enable the specified warning message for any warnings following the
+   comment.
+
+.. option:: /*verilator&32;lint_restore*/
+
+   After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint
+   message state.  Often this is useful at the bottom of include files.
+
+.. option:: /*verilator&32;lint_save*/
+
+   Push the current state of what lint messages are turned on or turned off
+   to a stack.  Later meta-comments may then lint_on or lint_off specific
+   messages, then return to the earlier message state by using
+   :code:`/*verilator&32;lint_restore*/`.  For example:
+
+   .. code-block:: sv
+
+         // verilator lint_save
+         // verilator lint_off WIDTH
+         ...  // code needing WIDTH turned off
+         // verilator lint_restore
+
+   If WIDTH was on before the lint_off, it will now be restored to on, and
+   if it was off before the lint_off it will remain off.
+
+.. option:: /*verilator&32;no_inline_module*/
+
+   Specifies the module the comment appears in should not be inlined into
+   any modules that use this module.
+
+   Same as :option:`no_inline` configuration file option.
+
+.. option:: /*verilator&32;no_inline_task*/
+
+   Used in a function or task variable definition section to specify the
+   function or task should not be inlined into where it is used.  This may
+   reduce the size of the final executable when a task is used a very large
+   number of times.  For this flag to work, the task and tasks below it
+   must be pure; they cannot reference any variables outside the task
+   itself.
+
+   Same as :option:`no_inline` configuration file option.
+
+.. option:: /*verilator&32;public*/ (on parameter)
+
+   Used after a parameter declaration to indicate the emitted C code should
+   have the parameter values visible. Due to C++ language restrictions,
+   this may only be used on 64-bit or narrower integral enumerations.
+
+   .. code-block:: sv
+
+         parameter [2:0] PARAM /*verilator public*/ = 2'b0;
+
+.. option:: /*verilator&32;public*/ (on typedef enum)
+
+   Used after an enum typedef declaration to indicate the emitted C code
+   should have the enum values visible. Due to C++ language restrictions,
+   this may only be used on 64-bit or narrower integral enumerations.
+
+   .. code-block:: sv
+
+         typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/;
+
+.. option:: /*verilator&32;public*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared so that C code may read or write the value
+   of the signal.  This will also declare this module public, otherwise use
+   :code:`/*verilator&32;public_flat*/`.
+
+   Instead of using public variables, consider instead making a DPI or
+   public function that accesses the variable.  This is nicer as it
+   provides an obvious entry point that is also compatible across
+   simulators.
+
+   Same as :option:`public` configuration file option.
+
+.. option:: /*verilator&32;public*/ (on task/function)
+
+   Used inside the declaration section of a function or task declaration to
+   indicate the function or task should be made into a C++ function, public
+   to outside callers.  Public tasks will be declared as a void C++
+   function, public functions will get the appropriate non-void (bool,
+   uint32_t, etc) return type.  Any input arguments will become C++
+   arguments to the function.  Any output arguments will become C++
+   reference arguments.  Any local registers/integers will become function
+   automatic variables on the stack.
+
+   Wide variables over 64 bits cannot be function returns, to avoid
+   exposing complexities.  However, wide variables can be input/outputs;
+   they will be passed as references to an array of 32-bit numbers.
+
+   Generally, only the values of stored state (flops) should be written, as
+   the model will NOT notice changes made to variables in these functions.
+   (Same as when a signal is declared public.)
+
+   You may want to use DPI exports instead, as it's compatible with other
+   simulators.
+
+   Same as :option:`public` configuration file option.
+
+.. option:: /*verilator&32;public_flat*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared so that C code may read or write the value
+   of the signal.  This will not declare this module public, which means
+   the name of the signal or path to it may change based upon the module
+   inlining which takes place.
+
+   Same as :option:`public_flat` configuration file option.
+
+.. option:: /*verilator&32;public_flat_rd*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared public_flat (see above), but read-only.
+
+   Same as :option:`public_flat_rd` configuration file option.
+
+.. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
+
+   Used after an input, output, register, or wire declaration to indicate
+   the signal should be declared public_flat_rd (see above), and also
+   writable, where writes should be considered to have the timing specified
+   by the given sensitivity edge list.  Set for all variables, ports and
+   wires using the :vlopt:`--public-flat-rw` option.
+
+   Same as :option:`public_flat_rw` configuration file option.
+
+.. option:: /*verilator&32;public_module*/
+
+   Used after a module statement to indicate the module should not be
+   inlined (unless specifically requested) so that C code may access the
+   module.  Verilator automatically sets this attribute when the module
+   contains any public signals or \`systemc_ directives.  Also set for all
+   modules when using the :vlopt:`--public` option.
+
+   Same as :option:`public` configuration file option.
+
+.. option:: /*verilator&32;sc_clock*/
+
+   Deprecated and ignored.  Previously used after an input declaration to
+   indicate the signal should be declared in SystemC as a sc_clock instead
+   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
+   and later do not require clock pins to be sc_clocks and this is no
+   longer needed and is ignored.
+
+.. option:: /*verilator&32;sc_bv*/
+
+   Used after a port declaration.  It sets the port to be of
+   :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t.
+   This may be useful if the port width is parameterized and the
+   instantiating C++ code wants to always have a sc_bv so it can accept any
+   width.  In general you should avoid using this attribute when not
+   necessary as with increasing usage of sc_bv the performance decreases
+   significantly.
+
+   Same as :option:`sc_bv` configuration file option.
+
+.. option:: /*verilator&32;sformat*/
+
+   Attached to the final argument of type "input string" of a function or
+   task to indicate the function or task should pass all remaining
+   arguments through $sformatf.  This allows creation of DPI functions with
+   $display like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
+   file for an example.
+
+   Same as :option:`sformat` configuration file option.
+
+.. option:: /*verilator&32;split_var*/
+
+   Attached to a variable or a net declaration to break the variable into
+   multiple pieces typically to resolve ``UNOPTFLAT`` performance issues.
+   Typically the variables to attach this to are recommended by Verilator
+   itself, see :option:`UNOPTFLAT`.
+
+   For example, Verilator will internally convert a variable with the
+   metacomment such as:
+
+   .. code-block:: sv
+
+         logic [7:0] x [0:1]  /*verilator split_var*/;
+
+   To:
+
+   .. code-block:: sv
+
+         logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
+         logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
+
+   Note that the generated packed variables retain the split_var
+   metacomment because they may be split into further smaller pieces
+   according to the access patterns.
+
+   This only supports unpacked arrays, packed arrays, and packed structs of
+   integer types (reg, logic, bit, byte, int...); otherwise if a split was
+   requested but cannot occur a SPLITVAR warning is issued.  Splitting
+   large arrays may slow down the Verilation speed, so use this only on
+   variables that require it.
+
+   Same as :option:`split_var` configuration file option.
+
+.. option:: /*verilator&32;tag <text...>*/
+
+   Attached after a variable or structure member to indicate opaque (to
+   Verilator) text that should be passed through to the XML output as a tag,
+   for use by downstream applications.
+
+.. option:: /*verilator&32;tracing_off*/
+
+   Disable waveform tracing for all future signals that are declared in
+   this module, or instances below this module.  Often this is placed just
+   after a primitive's module statement, so that the entire module and
+   instances below it are not traced.
+
+.. option:: /*verilator&32;tracing_on*/
+
+   Re-enable waveform tracing for all future signals or instances that are
+   declared.

docs/guide/faq.rst

@@ -0,0 +1,497 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+******************************
+FAQ/Frequently Asked Questions
+******************************
+
+.. Extra heading level here so sidebar index looks nice
+
+Questions
+=========
+
+Can I contribute?
+"""""""""""""""""
+
+Please contribute!  Just submit a pull request, or raise an issue to
+discuss if looking for something to help on.  For more information see our
+contributor agreement.
+
+
+How widely is Verilator used?
+"""""""""""""""""""""""""""""
+
+Verilator is used by many of the largest silicon design companies, large
+organizations such as CERN, and even by college student projects.
+
+Verilator is one of the "big 4" simulators, meaning one of the 4 main
+SystemVerilog simulators available, namely the closed-source products Synopsys
+VCS (tm), Mentor Questa/ModelSim (tm), Cadence
+Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
+The three closed-source offerings are often collectively called the "big 3"
+simulators.
+
+
+Does Verilator run under Windows?
+"""""""""""""""""""""""""""""""""
+
+Yes, using Cygwin.  Verilated output also compiles under Microsoft Visual
+C++, but this is not tested every release.
+
+
+Can you provide binaries?
+"""""""""""""""""""""""""
+
+You can install Verilator via the system package manager (apt, yum, etc.)
+on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and
+others.  These packages are provided by the Linux distributions and
+generally will lag the version of the mainline Verilator repository.  If no
+binary package is available for your distribution, how about you set one
+up?
+
+
+How can it be faster than (name-a-big-3-closed-source-simulator)?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Generally, the implied part of the question is "... with all of the
+manpower they can put into developing it."
+
+Most simulators have to be compliant with the complete IEEE 1364 (Verilog)
+and IEEE 1800 (SystemVerilog) standards, meaning they have to be event
+driven.  This prevents them from being able to reorder blocks and make
+netlist-style optimizations, which are where most of the gains come from.
+
+You should not be scared by non-compliance.  Your synthesis tool isn't
+compliant with the whole standard to start with, so your simulator need not
+be either.  Verilator is closer to the synthesis interpretation, so this is
+a good thing for getting working silicon.
+
+
+Will Verilator output remain under my own license/copyright?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Yes, it's just like using GCC on your programs; this is why Verilator uses
+the "GNU **Lesser** Public License Version 3" instead of the more typical
+"GNU Public License".  See the licenses for details, but in brief, if you
+change Verilator itself or the header files Verilator includes, you must
+make the source code available under the GNU Lesser Public License.
+However, Verilator output (the Verilated code) only "include"s the licensed
+files, and so you are **not** required to open-source release any output
+from Verilator.
+
+You also have the option of using the Perl Artistic License, which again
+does not require you to release your Verilog or generated code, and also
+allows you to modify Verilator for internal use without distributing the
+modified version.  But please contribute back to the community!
+
+One limit is that you cannot under either license release a closed-source
+Verilog simulation product incorporating Verilator. That is you can have a
+commercial product, but must make the source code available.
+
+As is standard with Open Source, contributions back to Verilator will be
+placed under the Verilator copyright and LGPL/Artistic license.  Small test
+cases will be released into the public domain so they can be used anywhere,
+and large tests under the LGPL/Artistic, unless requested otherwise.
+
+
+Why is running Verilator (to create a model) so slow?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Verilator may require more memory than the resulting simulator will
+require, as Verilator internally creates all of the state of the resulting
+generated simulator in order to optimize it.  If it takes more than a few
+minutes or so (and you're not using :vlopt:`--debug` since debug mode is
+disk bound), see if your machine is paging; most likely you need to run it
+on a machine with more memory. Very large designs are known to have topped
+64 GB resident set size.  Alternatively, see :ref:`Hierarchical Verilation`.
+
+
+How do I generate waveforms (traces) in C++?
+""""""""""""""""""""""""""""""""""""""""""""
+
+See also the next question for tracing in SystemC mode.
+
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C
+   code, call ``Verilated::traceEverOn(true)``.  Then you may use
+   ``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any
+   Verilog simulator. See ``examples/make_tracing_c`` in the distribution.
+
+B. Or, for finer-grained control, or C++ files with multiple Verilated
+   modules you may also create the trace purely from C++.  Create a
+   VerilatedVcdC object, and in your main loop right after ``eval()`` call
+   ``trace_object->dump(contextp->time())`` every time step, and finally
+   call ``trace_object->close()``.
+
+   .. code-block:: C++
+      :emphasize-lines: 1,5-8,12
+
+      #include "verilated_vcd_c.h"
+      ...
+      int main(int argc, char** argv, char** env) {
+          const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+          ...
+          Verilated::traceEverOn(true);
+          VerilatedVcdC* tfp = new VerilatedVcdC;
+          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+          tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
+          ...
+          while (contextp->time() < sim_time && !contextp->gotFinish()) {
+              contextp->timeInc(1);
+              topp->eval();
+              tfp->dump(contextp->time());
+          }
+          tfp->close();
+      }
+
+You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
+link, preferably by adding the dependencies in your Makefile's
+:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if using the
+Verilator :vlopt:`--exe` option.
+
+you can call :code:`trace_object->trace()` on multiple Verilated objects
+with the same trace file if you want all data to land in the same output
+file.
+
+
+How do I generate waveforms (traces) in SystemC?
+""""""""""""""""""""""""""""""""""""""""""""""""
+
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top level
+   :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
+   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as
+   with any Verilog simulator, see the non-SystemC example in
+   :file:`examples/make_tracing_c`. This will trace only the module
+   containing the :code:`$dumpvar`.
+
+B. Or, you may create a trace purely from SystemC, which may trace all
+   Verilated designs in the SystemC model. Create a VerilatedVcdSc object
+   as you would create a normal SystemC trace file.  For an example, see
+   the call to ``VerilatedVcdSc`` in the
+   :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
+   and below.
+
+C. Alternatively you may use the C++ trace mechanism described in the
+   previous question, note the timescale and timeprecision will be
+   inherited from your SystemC settings.
+
+   .. code-block:: C++
+      :emphasize-lines: 1,5-8
+
+      #include "verilated_vcd_sc.h"
+      ...
+      int main(int argc, char** argv, char** env) {
+          ...
+          Verilated::traceEverOn(true);
+          VerilatedVcdSc* tfp = new VerilatedVcdSc;
+          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+          tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
+          ...
+          sc_start(1);
+          ...
+          tfp->close();
+      }
+
+
+
+You also need to compile :file:`verilated_vcd_sc.cpp` and
+:file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
+the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
+This is done for you if using the Verilator :vlopt:`--exe` option.
+
+You can call :code:`->trace()` on multiple Verilated objects with the same
+trace file if you want all data to land in the same output file.
+
+When using SystemC 2.3, the SystemC library must have been built with the
+experimental simulation phase callback based tracing disabled. This is
+disabled by default when building SystemC with its configure based build
+system, but when building SystemC with CMake, you must pass
+``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature.
+
+
+How do I generate FST waveforms (traces) in C++ or SystemC?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+FST is a trace file format developed by GTKWave.  Verilator provides basic
+FST support.  To dump traces in FST format, add the :vlopt:`--trace-fst`
+option to Verilator and either A. use :code:`$dumpfile & $dumpvars` in
+Verilog as described in the VCD example above,
+
+Or, in C++ change the include described in the VCD example above:
+
+.. code-block:: C++
+
+      #include "verilated_fst_c.h"
+      VerilatedFstC* tfp = new VerilatedFstC;
+
+
+Or, in SystemC change the include described in the VCD example above:
+
+.. code-block:: C++
+
+      #include "verilated_fst_sc.h"
+      VerilatedFstC* tfp = new VerilatedFstSc;
+
+
+Note that currently supporting both FST and VCD in a single simulation is
+impossible, but such requirement should be rare.  You can however ifdef
+around the trace format in your C++ main loop, and select VCD or FST at
+build time, should you require.
+
+
+How do I view waveforms (aka dumps or traces)?
+""""""""""""""""""""""""""""""""""""""""""""""
+
+Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
+files are viewable with the open source GTKWave (recommended) or Dinotrace
+(legacy) programs, or any of the many closed-source offerings; FST is
+supported only by GTKWave.
+
+
+How do I speed up writing large waveform (trace) files?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the
+   beginning of time, delay calling it until the time stamp where you want
+   tracing to begin.
+
+B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very
+   low level modules you never want to trace (such as perhaps library
+   cells).
+
+C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for
+   example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top
+   level signals.
+
+D. You can also consider using FST tracing instead of VCD. FST dumps are a
+   fraction of the size of the equivalent VCD. FST tracing can be slower
+   than VCD tracing, but it might be the only option if the VCD file size
+   is prohibitively large.
+
+E. Be sure you write your trace files to a local solid-state drive, instead
+   of to a network drive.  Network drives are generally far slower.
+
+
+Where is the translate_off command?  (How do I ignore a construct?)
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Translate on/off pragmas are generally a bad idea, as it's easy to have
+mismatched pairs, and you can't see what another tool sees by just
+preprocessing the code.  Instead, use the preprocessor; Verilator defines
+the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef
+region:
+
+ .. code-block:: sv
+    :emphasize-lines: 1
+
+    `ifndef VERILATOR
+       Something_Verilator_Dislikes;
+    `endif
+
+Most synthesis tools similarly define SYNTHESIS for you.
+
+
+Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
+are reserved keywords in SystemVerilog.  Older Verilog code might use these
+as identifiers.  You should change your code to not use them to ensure it
+works with newer tools.  Alternatively, surround them by the Verilog
+2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
+
+.. code-block:: sv
+   :emphasize-lines: 1
+
+   `begin_keywords "1364-2001"
+      integer bit; initial bit = 1;
+   `end_keywords
+
+
+If you want the whole design to be parsed as Verilog 2001, see the
+:vlopt:`--default-language` option.
+
+
+How do I prevent my assertions from firing during reset?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Call :code:`Verilated::assertOn(false)` before you first call the model,
+then turn it back on after reset.  It defaults to true.  When false, all
+assertions controlled by :vlopt:`--assert` are disabled.
+
+
+Why do I get "undefined reference to sc_time_stamp()?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+In Verilator 4.200 and later, using the timeInc function is recommended
+instead.  See the :ref:`Connecting to C++` examples.  Some linkers (MSVC++)
+still require :code:`sc_time_stamp()` to be defined, either define this
+with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
+code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
+
+Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
+defined in C++ (non SystemC) to return the current simulation time.
+
+
+Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+You need to link your compiled Verilated code against the
+:code:`verilated.cpp` file found in the include directory of the Verilator
+kit.  This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which
+should be part of your Makefile's link rule.  If you use :vlopt:`--exe`,
+this is done for you.
+
+
+Is the PLI supported?
+"""""""""""""""""""""
+
+Only somewhat.  More specifically, the common PLI-ish calls $display,
+$finish, $stop, $time, $write are converted to C++ equivalents.  You can
+also use the "import DPI" SystemVerilog feature to call C code (see the
+chapter above).  There is also limited VPI access to public signals.
+
+If you want something more complex, since Verilator emits standard C++
+code, you can simply write your own C++ routines that can access and modify
+signal values without needing any PLI interface code, and call it with
+$c("{any_c++_statement}").
+
+See the :ref:`Connecting` section.
+
+
+How do I make a Verilog module that contain a C++ object?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+You need to add the object to the structure that Verilator creates, then
+use $c to call a method inside your object.  The
+:file:`test_regress/t/t_extend_class` files in the distribution show an
+example of how to do this.
+
+
+How do I get faster build times?
+""""""""""""""""""""""""""""""""
+
+* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that
+  builds occur in parallel. Note this is now set by default if an output
+  file was large enough to be split due to the :vlopt:`--output-split`
+  option.
+
+* Verilator emits any infrequently executed "cold" routines into separate
+  __Slow.cpp files. This can accelerate compilation as optimization can be
+  disabled on these routines. See the OPT_FAST and OPT_SLOW make variables
+  and :ref:`Benchmarking & Optimization`.
+
+* Use a recent compiler.  Newer compilers tend to be faster.
+
+* Compile in parallel on many machines and use caching; see the web for the
+  ccache, distcc and icecream packages. ccache will skip GCC runs between
+  identical source builds, even across different users.  If ccache was
+  installed when Verilator was built it is used, or see OBJCACHE
+  environment variable to override this. Also see the
+  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`
+
+* To reduce the compile time of classes that use a Verilated module (e.g. a
+  top CPP file) you may wish to add a
+  :option:`/*verilator&32;no_inline_module*/` metacomment to your top level
+  module. This will decrease the amount of code in the model's Verilated
+  class, improving compile times of any instantiating top level C++ code,
+  at a relatively small cost of execution performance.
+
+* Use :ref:`hierarchical verilation`.
+
+
+Why do so many files need to recompile when I add a signal?
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+Adding a new signal requires the symbol table to be recompiled.  Verilator
+uses one large symbol table, as that results in 2-3 less assembly
+instructions for each signal access.  This makes the execution time 10-15%
+faster, but can result in more compilations when something changes.
+
+
+How do I access Verilog functions/tasks in C?
+"""""""""""""""""""""""""""""""""""""""""""""
+
+Use the SystemVerilog Direct Programming Interface.  You write a Verilog
+function or task with input/outputs that match what you want to call in
+with C.  Then mark that function as a DPI export function.  See the DPI
+chapter in the IEEE Standard.
+
+
+How do I access C++ functions/tasks in Verilog?
+"""""""""""""""""""""""""""""""""""""""""""""""
+
+Use the SystemVerilog Direct Programming Interface.  You write a Verilog
+function or task with input/outputs that match what you want to call in
+with C.  Then mark that function as a DPI import function.  See the DPI
+chapter in the IEEE Standard.
+
+
+How do I access signals in C?
+"""""""""""""""""""""""""""""
+
+The best thing to do is to make a SystemVerilog "export DPI" task or
+function that accesses that signal, as described in the DPI chapter in the
+manual and DPI tutorials on the web.  This will allow Verilator to better
+optimize the model and should be portable across simulators.
+
+If you really want raw access to the signals, declare the signals you will
+be accessing with a :option:`/*verilator&32;public*/` metacomment before
+the closing semicolon.  Then scope into the C++ class to read the value of
+the signal, as you would any other member variable.
+
+Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
+16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
+64-bit unsigned long longs (uint64_t) that fits the width of the signal.
+Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for
+1 to 64 bits, and the compiler will properly up-convert smaller entities.
+Note even signed ports are declared as unsigned; you must sign extend
+yourself to the appropriate signal width.
+
+Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
+Thus to read bits 31:0, access signal[0], and for bits 63:32, access
+signal[1].  Unused bits (for example bit numbers 65-96 of a 65-bit vector)
+will always be zero.  If you change the value you must make sure to pack
+zeros in the unused bits or core-dumps may result, because Verilator strips
+array bound checks where it believes them to be unnecessary to improve
+performance.
+
+In the SYSTEMC example above, if you had in our.v:
+
+ .. code-block:: sv
+
+      input clk /*verilator public*/;
+      // Note the placement of the semicolon above
+
+From the sc_main.cpp file, you'd then:
+
+ .. code-block:: C++
+
+      #include "Vour.h"
+      #include "Vour_our.h"
+      cout << "clock is " << top->our->clk << endl;
+
+
+In this example, clk is a bool you can read or set as any other variable.
+The value of normal signals may be set, though clocks shouldn't be changed
+by your code or you'll get strange results.
+
+
+Should a module be in Verilog or SystemC?
+"""""""""""""""""""""""""""""""""""""""""
+
+Sometimes there is a block that just interconnects instances, and have a
+choice as to if you write it in Verilog or SystemC.  Everything else being
+equal, best performance is when Verilator sees all of the design.  So, look
+at the hierarchy of your design, labeling instances as to if they are
+SystemC or Verilog.  Then:
+
+* A module with only SystemC instances below must be SystemC.
+
+* A module with a mix of Verilog and SystemC instances below must be
+  SystemC. (As Verilator cannot connect to lower-level SystemC instances.)
+
+* A module with only Verilog instances below can be either, but for best
+  performance should be Verilog.  (The exception is if you have a design
+  that is instantiated many times; in this case Verilating one of the lower
+  modules and instantiating that Verilated instances multiple times into a
+  SystemC module *may* be faster.)

docs/guide/files.rst

@@ -0,0 +1,167 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+*****
+Files
+*****
+
+.. _Files in the Distribution:
+
+Files in the Git Tree
+=====================
+
+The following is a summary of the files in the Git Tree (distribution) of
+Verilator:
+
+::
+
+   Changes                     => Version history
+   README.rst                  => This document
+   bin/verilator               => Compiler wrapper invoked to Verilate code
+   docs/                       => Additional documentation
+   examples/                   => Examples (see manual for descriptions)
+   include/                    => Files that should be in your -I compiler path
+   include/verilated*.cpp      => Global routines to link into your simulator
+   include/verilated*.h        => Global headers
+   include/verilated.mk        => Common Makefile
+   src/                        => Translator source code
+   test_regress                => Internal tests
+
+
+.. _Files Read/Written:
+
+Files Read/Written
+==================
+
+All output files are placed in the output directory specified with the
+:vlopt:`--Mdir` option, or "obj_dir" if not specified.
+
+Verilator creates the following files in the output directory:
+
+For --cc/--sc, it creates:
+
+.. list-table::
+
+   * - *{prefix}*\ .cmake
+     - CMake include script for compiling (from --make cmake)
+   * - *{prefix}*\ .mk
+     - Make include file for compiling (from --make gmake)
+   * - *{prefix}*\ _classes.mk
+     - Make include file with class names (from --make gmake)
+   * - *{prefix}*\ _hier.mk
+     - Make file for hierarchy blocks (from --make gmake)
+   * - *{prefix|*\ _hierMkArgs.f
+     - Arguments for hierarchical Verilation (from --make gmake)
+   * - *{prefix}*\ _hierCMakeArgs.f
+     - Arguments for hierarchical Verilation (from --make cmake)
+   * - *{prefix}*\ .h
+     - Model header
+   * - *{prefix}*\ .cpp
+     - Model C++ file
+   * - *{prefix}*\ ___024root.h
+     - Top level (SystemVerilog $root) internal header file
+   * - *{prefix}*\ ___024root.cpp
+     - Top level (SystemVerilog $root) internal C++ file
+   * - *{prefix}*___024root*{__n}*\ .cpp
+     - Additional top level internal C++ files (from --output-split)
+   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
+     - Infrequent cold routines
+   * - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
+     - Wave file generation code (from --trace)
+   * - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
+     - Wave file generation code (from --trace)
+   * - *{prefix}*\ __Dpi.h
+     - DPI import and export declarations (from --dpi)
+   * - *{prefix}*\ __Dpi.cpp
+     - Global DPI export wrappers (from --dpi)
+   * - *{prefix}*\ __Dpi_Export\ *{__n}*\ .cpp
+     - DPI export wrappers scoped to this particular model (from --dpi)
+   * - *{prefix}*\ __Inlines.h
+     - Inline support functions
+   * - *{prefix}*\ __Syms.h
+     - Global symbol table header
+   * - *{prefix}*\ __Syms.cpp
+     - Global symbol table C++
+   * - *{prefix}{each_verilog_module}*\ .h
+     - Lower level internal header files
+   * - *{prefix}{each_verilog_module}*\ .cpp
+     - Lower level internal C++ files
+   * - *{prefix}{each_verilog_module}{__n}*\ .cpp
+     - Additional lower C++ files (from --output-split)
+
+For --hierarchy mode, it creates:
+
+.. list-table::
+
+   * - V\ *{hier_block}*\ /
+     - Directory to Verilate each hierarchy block (from --hierarchy)
+   * - *{prefix}*\ __hierVer.d
+     - Make dependencies of the top module (from --hierarchy)
+   * - *{prefix}*\ __hier.dir
+     - Directory to store .dot, .vpp, .tree of top module (from --hierarchy)
+
+In certain debug and other modes, it also creates:
+
+.. list-table::
+
+   * - *{prefix}*\ .xml
+     - XML tree information (from --xml)
+   * - *{prefix}*\ __cdc.txt
+     - Clock Domain Crossing checks (from --cdc)
+   * - *{prefix}*\ __stats.txt
+     - Statistics (from --stats)
+   * - *{prefix}*\ __idmap.txt
+     - Symbol demangling (from --protect-ids)
+   * - *{prefix}*\ __ver.d
+     - Make dependencies (from -MMD)
+   * - *{prefix}*\ __verFiles.dat
+     - Timestamps (from --skip-identical)
+   * - *{prefix}{misc}*\ .dot
+     - Debugging graph files (from --debug)
+   * - *{prefix}{misc}*\ .tree
+     - Debugging files (from --debug)
+   * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp
+     - Pre-processed verilog (from --debug)
+
+After running Make, the C++ compiler may produce the following:
+
+.. list-table::
+
+   * - verilated{misc}*\ .d
+     - Intermediate dependencies
+   * - verilated{misc}*\ .o
+     - Intermediate objects
+   * - {mod_prefix}{misc}*\ .d
+     - Intermediate dependencies
+   * - {mod_prefix}{misc}*\ .o
+     - Intermediate objects
+   * - *{prefix}*\
+     - Final executable (from --exe)
+   * - *{prefix}*\ __ALL.a
+     - Library of all Verilated objects
+   * - *{prefix}*\ __ALL.cpp
+     - Include of all code for single compile
+   * - *{prefix}{misc}*\ .d
+     - Intermediate dependencies
+   * - *{prefix}{misc}*\ .o
+     - Intermediate objects
+
+The Verilated executable may produce the following:
+
+.. list-table::
+
+   * - coverage.dat
+     - Code coverage output, and default input filename for :command:`verilator_coverage`
+   * - gmon.out
+     - GCC/clang code profiler output, often fed into :command:`verilator_profcfunc`
+   * - profile.vlt
+     - -profile data file for :ref:`Thread PGO`
+   * - profile_threads.dat
+     - -profile-threads data file for :command:`verilator_gnatt`
+
+Verilator_gantt may produce the following:
+
+.. list-table::
+
+   * - profile_threads.vcd
+     - Gantt report waveform output

docs/guide/index.rst

@@ -0,0 +1,41 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+######################
+Verilator User's Guide
+######################
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Getting Started
+
+   overview.rst
+   examples.rst
+   install.rst
+
+
+.. toctree::
+   :maxdepth: 2
+   :caption: User's Guide
+
+   verilating.rst
+   connecting.rst
+   simulating.rst
+   contributing.rst
+   faq.rst
+
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Reference Guide
+
+   languages.rst
+   extensions.rst
+   executables.rst
+   warnings.rst
+   files.rst
+   environment.rst
+   deprecations.rst
+   contributors.rst
+   changes.rst
+   copyright.rst

docs/guide/install.rst

@@ -0,0 +1,322 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Installation:
+
+************
+Installation
+************
+
+This section discusses how to install Verilator.
+
+.. _Package Manager Quick Install:
+
+Package Manager Quick Install
+=============================
+
+Using a distribution's package manager is the easiest way to get
+started. (Note packages are unlikely to have the most recent version, so
+:ref:`Git Install`, might be a better alternative.) To install as a
+package:
+
+::
+
+   apt-get install verilator   # On Ubuntu
+
+For other distributions refer to `Repology Verilator Distro Packages
+<https://repology.org/project/verilator>`__.
+
+.. _Git Install:
+
+Git Quick Install
+=================
+
+Installing Verilator from Git provides the most flexibility. For additional
+options and details see :ref:`Detailed Build Instructions` below.
+
+In brief, to install from git:
+
+::
+
+   # Prerequisites:
+   #sudo apt-get install git perl python3 make autoconf g++ flex bison ccache
+   #sudo apt-get install libgoogle-perftools-dev numactl perl-doc
+   #sudo apt-get install libfl2  # Ubuntu only (ignore if gives error)
+   #sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
+   #sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
+
+   git clone https://github.com/verilator/verilator   # Only first time
+
+   # Every time you need to build:
+   unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
+   unset VERILATOR_ROOT  # For bash
+   cd verilator
+   git pull         # Make sure git repository is up-to-date
+   git tag          # See what versions exist
+   #git checkout master      # Use development branch (e.g. recent bug fixes)
+   #git checkout stable      # Use most recent stable release
+   #git checkout v{version}  # Switch to specified release version
+
+   autoconf         # Create ./configure script
+   ./configure      # Configure and create Makefile
+   make -j `nproc`  # Build Verilator itself (if error, try just 'make')
+   sudo make install
+
+
+.. _Detailed Build Instructions:
+
+Detailed Build Instructions
+===========================
+
+This section describes details of the build process, and assumes you are
+building from Git. For using a pre-built binary for your Linux
+distribution, see instead :ref:`Package Manager Quick Install`.
+
+
+OS Requirements
+---------------
+
+Verilator is developed and has primary testing on Ubuntu, with additional
+testing on FreeBSD and Apple OS-X. Versions have also built on Redhat
+Linux, HPUX and Solaris. It should run with minor porting on any
+GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and
+Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator
+itself) compiles under all the options above, plus using MSVC++.
+
+
+Install Prerequisites
+---------------------
+
+To build or run Verilator you need these standard packages:
+
+::
+
+   sudo apt-get install git perl python3 make
+   sudo apt-get install g++  # Alternatively, clang
+   sudo apt-get install libgz  # Non-Ubuntu (ignore if gives error)
+   sudo apt-get install libfl2  # Ubuntu only (ignore if gives error)
+   sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
+   sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
+
+To build or run the following are optional but should be installed for good
+performance:
+
+::
+
+   sudo apt-get install ccache  # If present at build, needed for run
+   sudo apt-get install libgoogle-perftools-dev numactl perl-doc
+
+To build Verilator you will need to install these packages; these do not
+need to be present to run Verilator:
+
+::
+
+   sudo apt-get install git autoconf flex bison
+
+Those developing Verilator itself may also want these (see internals.rst):
+
+::
+
+   sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
+   sudo pip3 install sphinx sphinx_rtd_theme breathe
+   cpan install Pod::Perldoc
+   cpan install Parallel::Forker
+
+
+Install SystemC
+^^^^^^^^^^^^^^^
+
+If you will be using SystemC (vs straight C++ output), download `SystemC
+<https://www.accellera.org/downloads/standards/systemc>`__.  Follow their
+installation instructions. You will need to set the
+:option:`SYSTEMC_INCLUDE` environment variable to point to the include
+directory with ``systemc.h`` in it, and set the :option:`SYSTEMC_LIBDIR`
+environment variable to point to the directory with ``libsystemc.a`` in it.
+
+
+Install GTKWave
+^^^^^^^^^^^^^^^
+
+To make use of Verilator FST tracing you will want `GTKwave
+<http://gtkwave.sourceforge.net/>`__ installed, however this is not
+required at Verilator build time.
+
+
+Obtain Sources
+--------------
+
+Get the sources from the git repository: (You need do this only once,
+ever.)
+
+::
+
+   git clone https://github.com/verilator/verilator   # Only first time
+   ## Note the URL above is not a page you can see with a browser, it's for git only
+
+Enter the checkout and determine what version/branch to use:
+
+::
+
+   cd verilator
+   git pull        # Make sure we're up-to-date
+   git tag         # See what versions exist
+   #git checkout master      # Use development branch (e.g. recent bug fix)
+   #git checkout stable      # Use most recent release
+   #git checkout v{version}  # Switch to specified release version
+
+
+Auto Configure
+--------------
+
+Create the configuration script:
+
+::
+
+   autoconf        # Create ./configure script
+
+
+Eventual Installation Options
+-----------------------------
+
+Before configuring the build, you have to decide how you're going to
+eventually install Verilator onto your system. Verilator will be compiling
+the current value of the environment variables :option:`VERILATOR_ROOT`,
+:option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into
+the executable, so they must be correct before configuring.
+
+These are the installation options:
+
+
+1. Run-in-Place from VERILATOR_ROOT
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Our personal favorite is to always run Verilator in-place from its Git
+directory. This allows the easiest experimentation and upgrading, and
+allows many versions of Verilator to co-exist on a system.
+
+::
+
+   export VERILATOR_ROOT=`pwd`   # if your shell is bash
+   setenv VERILATOR_ROOT `pwd`   # if your shell is csh
+   ./configure
+   # Running will use files from $VERILATOR_ROOT, so no install needed
+
+Note after installing (below steps), a calling program or shell must set
+the environment variable :option:`VERILATOR_ROOT` to point to this Git
+directory, then execute ``$VERILATOR_ROOT/bin/verilator``, which will find
+the path to all needed files.
+
+
+2. Install into a specific location
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+You may eventually be installing onto a project/company-wide "CAD" tools
+disk that may support multiple versions of every tool. Tell configure the
+eventual destination directory name.  We recommend the destination location
+include the Verilator version name:
+
+::
+
+   unset VERILATOR_ROOT      # if your shell is bash
+   unsetenv VERILATOR_ROOT   # if your shell is csh
+   # For the tarball, use the version number instead of git describe
+   ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"`
+
+Note after installing (below steps), if you use `modulecmd
+<http://modules.sourceforge.net/>`__, you'll want a module file like the
+following:
+
+::
+
+   set install_root /CAD_DISK/verilator/{version-number-used-above}
+   unsetenv VERILATOR_ROOT
+   prepend-path PATH $install_root/bin
+   prepend-path MANPATH $install_root/man
+   prepend-path PKG_CONFIG_PATH $install_root/share/pkgconfig
+
+
+3. Install into a Specific Path
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+You may eventually install Verilator into a specific installation prefix,
+as most GNU tools support:
+
+::
+
+   unset VERILATOR_ROOT      # if your shell is bash
+   unsetenv VERILATOR_ROOT   # if your shell is csh
+   ./configure --prefix /opt/verilator-VERSION
+
+Then after installing (below steps) you will need to add
+``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable.
+
+
+4. Install System Globally
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The final option is to eventually install Verilator globally, using
+configure's default system paths:
+
+::
+
+   unset VERILATOR_ROOT      # if your shell is bash
+   unsetenv VERILATOR_ROOT   # if your shell is csh
+   ./configure
+
+Then after installing (below) the binaries should be in a location that is
+already in your ``$PATH`` environment variable.
+
+
+Configure
+---------
+
+The command to configure the package was described in the previous step.
+Developers should configure to have more complete developer tests.
+Additional packages may be required for these tests.
+
+::
+
+   export VERILATOR_AUTHOR_SITE=1    # Put in your .bashrc
+   ./configure --enable-longtests  ...above options...
+
+
+Compile
+-------
+
+Compile Verilator:
+
+::
+
+   make -j `nproc`  # Or if error on `nproc`, the number of CPUs in system
+
+
+Test
+----
+
+Check the compilation by running self-tests:
+
+::
+
+   make test
+
+
+Install
+-------
+
+If you used any install option other than the `1. Run-in-Place from
+VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install
+the files:
+
+::
+
+   make install
+
+
+.. Docker Build Environment
+
+.. include:: ../../ci/docker/buildenv/README.rst
+
+
+.. Docker Run Environment
+
+.. include:: ../../ci/docker/run/README.rst

docs/guide/languages.rst

@@ -0,0 +1,477 @@
+.. Copyright 2003-2021 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+***************
+Input Languages
+***************
+
+This section describes the languages Verilator takes as input.  See also
+:ref:`Configuration Files`.
+
+
+Language Standard Support
+=========================
+
+Verilog 2001 (IEEE 1364-2001) Support
+-------------------------------------
+
+Verilator supports most Verilog 2001 language features.  This includes
+signed numbers, "always @\*", generate statements, multidimensional arrays,
+localparam, and C-style declarations inside port lists.
+
+
+Verilog 2005 (IEEE 1364-2005) Support
+-------------------------------------
+
+Verilator supports most Verilog 2005 language features.  This includes the
+\`begin_keywords and \`end_keywords compiler directives, $clog2, and the
+uwire keyword.
+
+
+SystemVerilog 2005 (IEEE 1800-2005) Support
+-------------------------------------------
+
+Verilator supports ==? and !=? operators, ++ and -- in some contexts,
+$bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot,
+$onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte,
+chandle, const, do-while, enum, export, final, import, int, interface,
+logic, longint, modport, package, program, shortint, struct, time, typedef,
+union, var, void, priority case/if, and unique case/if.
+
+It also supports .name and .\* interconnection.
+
+Verilator partially supports concurrent assert and cover statements; see
+the enclosed coverage tests for the syntax which is allowed.
+
+Verilator has limited support for class and related object-oriented
+constructs.
+
+
+SystemVerilog 2012 (IEEE 1800-2012) Support
+-------------------------------------------
+
+Verilator implements a full SystemVerilog-compliant preprocessor, including
+function call-like preprocessor defines, default define arguments,
+\`__FILE__, \`__LINE__ and \`undefineall.
+
+
+SystemVerilog 2017 (IEEE 1800-2017) Support
+-------------------------------------------
+
+Verilator supports the 2017 "for" loop constructs, and several minor
+cleanups IEEE made in 1800-2017.
+
+
+Verilog AMS Support
+-------------------
+
+Verilator implements a very small subset of Verilog AMS (Verilog Analog and
+Mixed-Signal Extensions) with the subset corresponding to those VMS
+keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
+languages.
+
+AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
+:vlopt:`--language 1800+VAMS <--language>`.
+
+At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
+string, and wreal.
+
+
+Synthesis Directive Assertion Support
+-------------------------------------
+
+With the :vlopt:`--assert` option, Verilator reads any :code:`//synopsys
+full_case` or :code:`//synopsys parallel_case` directives.  The same
+applies to any :code:`//ambit synthesis`, :code:`//cadence` or
+:code:`//pragma` directives of the same form.
+
+When these synthesis directives are discovered, Verilator will either
+formally prove the directive to be true, or failing that, will insert the
+appropriate code to detect failing cases at simulation runtime and print an
+"Assertion failed" error message.
+
+Verilator likewise also asserts any "unique" or "priority" SystemVerilog
+keywords on case statement, as well as "unique" on if statements.  However,
+"priority if" is currently simply ignored.
+
+
+.. _Language Limitations:
+
+Language Limitations
+====================
+
+This section describes the language limitations of Verilator. Many of these
+restrictions are by intent.
+
+Synthesis Subset
+----------------
+
+Verilator supports the Synthesis subset with other verification constructs
+being added over time. Verilator also simulates events as Synopsys's Design
+Compiler would; namely given a block of the form:
+
+.. code-block:: sv
+
+        always @(x) y = x & z;
+
+This will recompute y when there is even a potential for change in x or a
+change in z, that is when the flops computing x or z evaluate (which is
+what Design Compiler will synthesize.)  A compliant simulator would only
+calculate y if x changes.  We recommend using always_comb to make the code
+run the same everywhere.  Also avoid putting $displays in combo blocks, as
+they may print multiple times when not desired, even on compliant
+simulators as event ordering is not specified.
+
+
+Signal Naming
+-------------
+
+To avoid conflicts with C symbol naming, any character in a signal name
+that is not alphanumeric nor a single underscore will be replaced by __0hh
+where hh is the hex code of the character. To avoid conflicts with
+Verilator's internal symbols, any double underscore are replaced with
+___05F (5F is the hex code of an underscore.)
+
+
+Bind
+----
+
+sVerilator only supports bind to a target module name, not to an
+instance path.
+
+
+Class
+-----
+
+Verilator class support is limited but in active development.  Verilator
+supports members, and methods. Verilator does not support class static
+members, class extend, or class parameters.
+
+
+Dotted cross-hierarchy references
+---------------------------------
+
+Verilator supports dotted references to variables, functions and tasks in
+different modules. The portion before the dot must have a constant value;
+for example a[2].b is acceptable, while a[x].b is generally not.
+
+References into generated and arrayed instances use the instance names
+specified in the Verilog standard; arrayed instances are named
+``{instanceName}[{instanceNumber}]`` in Verilog, which becomes
+``{instanceName}__BRA__{instanceNumber}__KET__`` inside the generated C++
+code.
+
+
+Latches
+-------
+
+Verilator is optimized for edge sensitive (flop based) designs.  It will
+attempt to do the correct thing for latches, but most performance
+optimizations will be disabled around the latch.
+
+
+Structures and Unions
+---------------------
+
+Presently Verilator only supports packed structs and packed unions.  Rand
+and randc tags on members are simply ignored.  All structures and unions
+are represented as a single vector, which means that generating one member
+of a structure from blocking, and another from non-blocking assignments is
+unsupported.
+
+
+Time
+----
+
+All delays (#) are ignored, as they are in synthesis.
+
+
+.. _Unknown States:
+
+Unknown States
+--------------
+
+Verilator is mostly a two state simulator, not a four state simulator.
+However, it has two features which uncover most initialization bugs
+(including many that a four state simulator will miss.)
+
+Identity comparisons (=== or !==) are converted to standard ==/!= when
+neither side is a constant.  This may make the expression yield a different
+result compared to a four state simulator.  An === comparison to X will
+always be false, so that Verilog code which checks for uninitialized logic
+will not fire.
+
+Assigning X to a variable will actually assign a constant value as
+determined by the :vlopt:`--x-assign` option.  This allows runtime
+randomization, thus if the value is actually used, the random value should
+cause downstream errors.  Integers also get randomized, even though the
+Verilog 2001 specification says they initialize to zero.  Note however that
+randomization happens at initialization time and hence during a single
+simulation run, the same constant (but random) value will be used every
+time the assignment is executed.
+
+All variables, depending on :vlopt:`--x-initial` setting, are typically
+randomly initialized using a function.  By running several random
+simulation runs you can determine that reset is working correctly.  On the
+first run, have the function initialize variables to zero.  On the second,
+have it initialize variables to one.  On the third and following runs have
+it initialize them randomly.  If the results match, reset works.  (Note
+this is what the hardware will really do.)  In practice, just setting all
+variables to one at startup finds most problems (since typically control
+signals are active-high).
+
+:vlopt:`--x-assign` applies to variables explicitly initialized or assigned
+an X. Uninitialized clocks are initialized to zero, while all other state
+holding variables are initialized to a random value.  Event driven
+simulators will generally trigger an edge on a transition from X to 1
+(posedge) or X to 0 (negedge). However, by default, since clocks are
+initialized to zero, Verilator will not trigger an initial negedge. Some
+code (particularly for reset) may rely on X->0 triggering an edge. The
+:vlopt:`--x-initial-edge` option enables this behavior. Comparing runs with
+and without this option will find such problems.
+
+
+Tri/Inout
+---------
+
+Verilator converts some simple tristate structures into two state.  Pullup,
+pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are
+also supported.  Simple comparisons with :code:`=== 1'bz` are also
+supported.
+
+An assignment of the form:
+
+.. code-block:: sv
+
+        inout driver;
+        wire driver = (enable) ? output_value : 1'bz;
+
+Will be converted to:
+
+.. code-block:: sv
+
+        input driver;       // Value being driven in from "external" drivers
+        output driver__en;  // True if driven from this module
+        output driver__out; // Value being driven from this module
+
+External logic will be needed to combine these signals with any external
+drivers.
+
+Tristate drivers are not supported inside functions and tasks; an inout
+there will be considered a two state variable that is read and written
+instead of a four state variable.
+
+
+Functions & Tasks
+-----------------
+
+All functions and tasks will be inlined (will not become functions in C.)
+The only support provided is for simple statements in tasks (which may
+affect global variables).
+
+Recursive functions and tasks are not supported.  All inputs and outputs
+are automatic, as if they had the Verilog 2001 "automatic" keyword
+prepended.  (If you don't know what this means, Verilator will do what you
+probably expect, what C does. The default behavior of Verilog is
+different.)
+
+
+Generated Clocks
+----------------
+
+Verilator attempts to deal with generated and gated clocks correctly,
+however some cases cause problems in the scheduling algorithm which is
+optimized for performance.  The safest option is to have all clocks as
+primary inputs to the model, or wires directly attached to primary inputs.
+For proper behavior clock enables may also need the
+:option:`/*verilator&32;clock_enable*/` metacomment.
+
+
+Gate Primitives
+---------------
+
+The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are
+directly converted to behavioral equivalents.  The 3-state and MOS gate
+primitives are not supported.  Tables are not supported.
+
+
+Specify blocks
+--------------
+
+All specify blocks and timing checks are ignored. All min:typ:max delays
+use the typical value.
+
+
+Array Initialization
+--------------------
+
+When initializing a large array, you need to use non-delayed assignments.
+Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT
+error for more information.
+
+
+Array Out of Bounds
+-------------------
+
+Writing a memory element that is outside the bounds specified for the array
+may cause a different memory element inside the array to be written
+instead.  For power-of-2 sized arrays, Verilator will give a width warning
+and the address.  For non-power-of-2-sizes arrays, index 0 will be written.
+
+Reading a memory element that is outside the bounds specified for the array
+will give a width warning and wrap around the power-of-2 size.  For
+non-power-of-2 sizes, it will return a unspecified constant of the
+appropriate width.
+
+
+Assertions
+----------
+
+Verilator is beginning to add support for assertions.  Verilator currently
+only converts assertions to simple :code:`if (...) error` statements, and
+coverage statements to increment the line counters described in the
+coverage section.
+
+Verilator does not support SEREs yet.  All assertion and coverage
+statements must be simple expressions that complete in one cycle.
+
+
+Encrypted Verilog
+-----------------
+
+Open source simulators like Verilator are unable to use encrypted RTL
+(i.e. IEEE P1735).  Talk to your IP vendor about delivering IP blocks via
+Verilator's :vlopt:`--protect-lib` feature.
+
+
+Language Keyword Limitations
+============================
+
+This section describes specific limitations for each language keyword.
+
+.. Hack to get long definition list:
+.. |cmdslong1| replace:: \`__FILE__, \`__LINE__, \`begin_keywords,
+   \`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords,
+   \`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef,
+   \`ifndef, \`include, \`line, \`systemc_ctor, \`systemc_dtor,
+   \`systemc_header, \`systemc_imp_header, \`systemc_implementation,
+   \`systemc_interface, \`undef, \`verilog
+
+|cmdslong1|
+  Fully supported.
+
+
+.. Hack to get long definition list:
+
+.. |cmdslong2| replace:: always, always_comb, always_ff, always_latch, and,
+   assign, begin, buf, byte, case, casex, casez, default, defparam,
+   do-while, else, end, endcase, endfunction, endgenerate, endmodule,
+   endspecify, endtask, final, for, function, generate, genvar, if,
+   initial, inout, input, int, integer, localparam, logic, longint,
+   macromodule, module, nand, negedge, nor, not, or, output, parameter,
+   posedge, reg, scalared, shortint, signed, supply0, supply1, task, time,
+   tri, typedef, var, vectored, while, wire, xnor, xor
+
+|cmdslong2|
+  Generally supported.
+
+++, -- operators
+  Increment/decrement can only be used as standalone statements or in
+  certain limited cases.
+
+'{} operator
+  Assignment patterns with order based, default, constant integer (array)
+  or member identifier (struct/union) keys are supported.  Data type keys
+  and keys which are computed from a constant expression are not supported.
+
+\`uselib
+  Uselib, a vendor specific library specification method, is ignored along
+  with anything following it until the end of that line.
+
+cast operator
+  Casting is supported only between simple scalar types, signed and
+  unsigned, not arrays nor structs.
+
+chandle
+  Treated as a "longint"; does not yet warn about operations that are
+  specified as illegal on chandles.
+
+disable
+  Disable statements may be used only if the block being disabled is a
+  block the disable statement itself is inside.  This was commonly used to
+  provide loop break and continue functionality before SystemVerilog added
+  the break and continue keywords.
+
+inside
+  Inside expressions may not include unpacked array traversal or $ as an
+  upper bound.  Case inside and case matches are also unsupported.
+
+interface
+  Interfaces and modports, including with generated data types are
+  supported.  Generate blocks around modports are not supported, nor are
+  virtual interfaces nor unnamed interfaces.
+
+shortreal
+  Short floating point (shortreal) numbers are converted to real. Most
+  other simulators either do not support float, or convert likewise.
+
+specify specparam
+  All specify blocks and timing checks are ignored.
+
+uwire
+  Verilator does not perform warning checking on uwires, it treats the
+  uwire keyword as if it were the normal wire keyword.
+
+$bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned,
+  Generally supported.
+
+$dump/$dumpports and related
+  $dumpfile or $dumpports will create a VCD or FST file (which is based on
+  the :vlopt:`--trace` option given when the model was Verilated). This
+  will take effect starting at the next eval() call.  If you have multiple
+  Verilated designs under the same C model, then this will dump signals
+  only from the design containing the $dumpvars.
+
+  $dumpvars and $dumpports module identifier is ignored; the traced
+  instances will always start at the top of the design. The levels argument
+  is also ignored, use tracing_on/tracing_off pragmas instead.
+
+  $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
+  argument is ignored, only a single trace file may be active at once.
+
+  $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
+  $dumplimit/$dumpportlimit are currently ignored.
+
+$error, $fatal, $info, $warning.
+  Generally supported.
+
+$exit, $finish, $stop
+  The rarely used optional parameter to $finish and $stop is ignored. $exit
+  is aliased to $finish.
+
+$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
+  Generally supported.
+
+$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width
+  All specify blocks and timing checks are ignored.
+
+$random, $urandom, $urandom_range
+  Use :vlopt:`+verilator+seed+\<value\>` runtime option to set the seed if
+  there is no $random nor $urandom optional argument to set the seed.
+  There is one random seed per C thread, not per module for $random, nor
+  per object for random stability of $urandom/$urandom_range.
+
+$readmemb, $readmemh
+  Read memory commands are supported.  Note Verilator and the Verilog
+  specification does not include support for readmem to multi-dimensional
+  arrays.
+
+$test$plusargs, $value$plusargs
+  Supported, but the instantiating C++/SystemC wrapper must call
+
+  .. code-block:: C++
+
+        Verilated::commandArgs(argc, argv);
+
+  to register the command line before calling $test$plusargs or
+  $value$plusargs.