Add check for rand_mode/constraint_mode.

src/V3Width.cpp

@@ -4186,6 +4186,13 @@ private:
             nodep->didWidth(true);
             return;
         }
+        if (nodep->classMethod() && nodep->name() == "rand_mode") {
+            nodep->v3error("The 'rand_mode' method is built-in and cannot be overridden"
+                           " (IEEE 1800-2017 18.8)");
+        } else if (nodep->classMethod() && nodep->name() == "constraint_mode") {
+            nodep->v3error("The 'constraint_mode' method is built-in and cannot be overridden"
+                           " (IEEE 1800-2017 18.9)");
+        }
         // Function hasn't been widthed, so make it so.
         // Would use user1 etc, but V3Width called from too many places to spend a user
         nodep->doingWidth(true);

test_regress/t/t_class_builtin_bad.out

@@ -0,0 +1,9 @@
+%Error: t/t_class_builtin_bad.v:8:17: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2017 18.8)
+                                    : ... In instance t
+    8 |    function int rand_mode(bit onoff);
+      |                 ^~~~~~~~~
+%Error: t/t_class_builtin_bad.v:11:17: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2017 18.9)
+                                     : ... In instance t
+   11 |    function int constraint_mode(bit onoff);
+      |                 ^~~~~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_class_builtin_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_class_builtin_bad.v

@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   function int rand_mode(bit onoff);
+      return 1;
+   endfunction
+   function int constraint_mode(bit onoff);
+      return 1;
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+   initial begin
+      Cls c;
+   end
+endmodule