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Fix capitalization

This commit is contained in:
Wilson Snyder 2020-10-22 17:13:42 -04:00
parent 5d3dd52f13
commit 25593c0ee2
4 changed files with 11 additions and 5 deletions
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4
src/V3Width.cpp
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@ -4782,7 +4782,7 @@ private:
new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
linker.relink(newp);
} else if (!underp->dtypep()->basicp()) {
nodep->v3error("Logical Operator " << nodep->prettyTypeName()
nodep->v3error("Logical operator " << nodep->prettyTypeName()
<< " expects a non-complex data type on the "
<< side << ".");
underp->replaceWith(new AstConst(nodep->fileline(), AstConst::LogicFalse()));
@ -4792,7 +4792,7 @@ private:
if (bad) {
{ // if (warnOn), but not needed here
if (debug() > 4) nodep->backp()->dumpTree(cout, " back: ");
nodep->v3warn(WIDTH, "Logical Operator "
nodep->v3warn(WIDTH, "Logical operator "
<< nodep->prettyTypeName() << " expects 1 bit on the "
<< side << ", but " << side << "'s "
<< underp->prettyTypeName() << " generates "

8
test_regress/t/t_lint_width_bad.out
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@ -3,9 +3,9 @@
17 | localparam [3:0] XS = 'hx;
| ^~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_lint_width_bad.v:45:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
: ... In instance t.p4
45 | wire [4:0] out = in;
47 | wire [4:0] out = in;
| ^
%Warning-WIDTH: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
: ... In instance t
@ -39,4 +39,8 @@
: ... In instance t
38 | initial for (a = 0; a >= THREE; ++a) $display(a);
| ^~
%Warning-WIDTH: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits.
: ... In instance t
40 | initial if (THREE) $stop;
| ^~
%Error: Exiting due to

2
test_regress/t/t_lint_width_bad.v
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@ -37,6 +37,8 @@ module t ();
initial for (a = 0; a > THREE; ++a) $display(a);
initial for (a = 0; a >= THREE; ++a) $display(a);
initial if (THREE) $stop;
endmodule
module p

2
test_regress/t/t_param_noval_bad.out
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@ -2,7 +2,7 @@
: ... In instance t
7 | module t #(parameter P);
| ^
%Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical Operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits.
%Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits.
: ... In instance t
10 | for (j=0; P; j++)
| ^~~