Version bump

converting to pure C printf call.  This makes the resulting code smaller,
and allows sharing code with future $sprintf support.

.gitignore

@@ -7,7 +7,7 @@
 *.1
 *.tmp
 *.tex
-Makefile
+/Makefile
 README
 config.cache
 config.status

MANIFEST.SKIP

@@ -0,0 +1,27 @@
+^CVS/
+/CVS/
+\.git/
+\.svn/
+\.(bak|old)/
+\.(bak|old)$
+\bMakefile$
+\.tar\.
+.*\.tgz
+.*\.log
+.*\.tmp
+.*\.tex
+.*\.key
+.*\.vcd
+/obj_dir/
+/obj_dbg/
+/obj_opt/
+/INCA_libs/
+/logs/
+Makefile
+src/Makefile_obj
+include/verilated.mk
+config.cache
+config.status
+verilator_bin.*
+autom4te\.cache/
+nodist/

Makefile.in

@@ -1,24 +1,23 @@
-# $Id$
 #*****************************************************************************
 # DESCRIPTION: Verilator top level: Makefile pre-configure version
-# 
+#
-# This file is part of Verilator.  
+# This file is part of Verilator.
-# 
+#
-# Author: Wilson Snyder <[email protected]> or <[email protected]>
+# Author: Wilson Snyder <[email protected]>
-# 
+#
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
-# 
+#
 #*****************************************************************************
-# 
+#
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
-# 
+#
 # Verilator is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 #****************************************************************************/
 #
 # make all	to compile and build Verilator.
@@ -38,7 +37,7 @@
 #      source and built the program without creating any other files,
 #      `make distclean' should leave only the files that were in the
 #      distribution.
-# 
+#
 # make maintainer-clean
 #      Delete everything from the current directory that can be
 #      reconstructed with this Makefile.  This typically includes
@@ -61,6 +60,9 @@ MAKEINFO = makeinfo
 TEXI2DVI = texi2dvi
 PERL = @PERL@
 
+# Destination prefix for RPMs
+DESTDIR =
+
 #### Don't edit: You're much better using configure switches to set these
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -78,8 +80,12 @@ datadir = @datadir@
 infodir = @infodir@
 
 # Directory in which to install package specific files
+# Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
 
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 #### End of system configuration section. ####
 ######################################################################
 
@@ -94,21 +100,28 @@ DISTDEP = info Makefile
 # Files to distribute.
 DISTBIN = $(wildcard bin/verilator-*)
 
-DISTFILES_INC = $(INFOS) .cvsignore COPYING *.in *.ac \
+DISTFILES_INC = $(INFOS) .gitignore COPYING *.in *.ac \
 	Changes README TODO \
+	MANIFEST.SKIP \
 	bin/* \
 	install-sh configure mkinstalldirs *.texi \
 	include/verilated.[chv]* \
 	include/verilatedos.[chv]* \
 	include/*.in \
-	src/.cvsignore src/*.in src/*.cpp src/*.[chly] src/astgen src/flexfix \
+	include/.*ignore \
+	.*attributes */.*attributes  */*/.*attributes \
+	src/.*ignore src/*.in src/*.cpp src/*.[chly] src/astgen src/*fix \
 	src/*.pl \
-	test_*/.cvsignore test_*/Makefile* test_*/*.cpp \
+	test_*/.*ignore test_*/Makefile* test_*/*.cpp \
 	test_*/*.pl test_*/*.v test_*/*.vc test_*/vlint \
 	test_verilated/vgen*.pl \
-	test_regress/t/*.v* \
+	test_regress/t/*.cpp \
-	test_regress/t/*.pl \
+	test_regress/t/*.h \
+	test_regress/t/*.dat \
+	test_regress/t/*.mem \
 	test_regress/t/*.out \
+	test_regress/t/*.pl \
+	test_regress/t/*.v* \
 	verilator.* \
 
 INST_PROJ_FILES = \
@@ -124,8 +137,10 @@ INST_PROJ_BIN_FILES = \
 
 DISTFILES := $(DISTFILES_INC)
 
+VL_INST_MAN_FILES = verilator.1
+
 all: all_nomsg msg_test
-all_nomsg: verilator_exe
+all_nomsg: verilator_exe $(VL_INST_MAN_FILES)
 
 .PHONY:verilator_exe
 verilator_exe verilator_bin verilator_bin_dbg:
@@ -140,6 +155,7 @@ msg_test:
 	@echo "Type 'make test' to test."
 	@echo
 
+.PHONY:test
 ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
 test: test_vcs test_c test_sc test_sp test_verilated test_regress
 else
@@ -184,16 +200,18 @@ verilator.html: bin/verilator
 verilator.pdf: bin/verilator $(DISTCONFIG)
 	pod2latex --full --out verilator.tex bin/verilator
 	cat < verilator.tex \
+	   | sed 's/\\begin{document}/\\usepackage[left=1.7in,right=1.7in,top=1.3in,bottom=1.3in]{geometry}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\usepackage[pdftex,bookmarks=true,bookmarksnumbered=true,hypertexnames=false,breaklinks=true,linkbordercolor={0 0 1}]{hyperref}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\usepackage{fancyhdr} \\pagestyle{fancy}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n\\begin{document}/' \
-	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.com}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.org}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\lhead[$(DISTTITLE)]{$(DISTTITLE)}\n\\begin{document}/' \
 	   | sed 's/\\tableofcontents/\\begin{titlepage} \\maketitle \\end{titlepage}\n\\tableofcontents/' \
 	   > verilator2.tex
 	mv verilator2.tex verilator.tex
 	pdflatex verilator.tex
 	pdflatex verilator.tex
-	-rm -f verilator.toc verilator.aux verilator.idx
+	-rm -f verilator.toc verilator.aux verilator.idx verilator.out
 
 INSTALL: install.texi
 	$(MAKEINFO) -I$(srcdir) $(srcdir)/install.texi --output=$@ \
@@ -203,21 +221,38 @@ README: readme.texi
 	$(MAKEINFO) -I$(srcdir) $(srcdir)/readme.texi --output=$@ \
 	--no-headers --no-validate
 
-installdirs:
-	$(SHELL) ${srcdir}/mkinstalldirs $(bindir) $(infodir)
-
 # See uninstall also
-VL_INST_BIN_FILES = verilator
+VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg \
+	verilator_includer verilator_profcfunc
+# Some scripts go into both the search path and pkgdatadir,
+# so they can be found by the user, and under $VERILATOR_ROOT.
 installbin:
-	( cd bin ; $(INSTALL_PROGRAM) verilator $(bindir)/verilator )
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(bindir)
+	( cd bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(bindir)/verilator_includer )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc )
+	( $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
+	( $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/bin
+	( cd bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer )
 
-VL_INST_MAN_FILES = verilator.1
 installman:
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(mandir)/man1
 	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_PROGRAM) $$p $(mandir)/man1/$$p; \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(mandir)/man1/$$p; \
 	done
 
-install: all_nomsg installdirs installbin installman install-msg
+installdata:
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples
+	cp -r include $(DESTDIR)$(pkgdatadir)
+	cp -r src     $(DESTDIR)$(pkgdatadir)
+	cp -r test_c  $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sc $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sp $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_v  $(DESTDIR)$(pkgdatadir)/examples
+
+VL_INST_DATA_FILES = verilator.1
+install: all_nomsg installbin installman installdata install-msg
 
 install-here: installman ftp
 
@@ -232,8 +267,8 @@ install-project: dist
 	for p in verilator.1 ; do \
 	  $(INSTALL_PROGRAM) -m 0666 $$p $(DIRPROJECT_PREFIX)/man/man1/$$p; \
 	done
-	$(INST_PROJ_CVS) $(DISTNAME).tar.gz $(DIRPROJECT)/hw/utils/verilator/verilator.tgz
+	$(INST_PROJ_CVS) $(DISTNAME).tgz $(DIRPROJECT)/hw/utils/verilator/verilator.tgz
-	rm $(DISTNAME).tar.gz
+	rm $(DISTNAME).tgz
 
 install-project-quick:
 	@echo "Install-project-quick (no strip) to $(DIRPROJECT)"
@@ -246,9 +281,6 @@ install-project-quick:
 endif
 
 ftp: info
-	echo "http://www.veripool.com/verilator3.html"
-	cp verilator.html verilator_man.html
-	ftp_tree --password $(VERIPOOL_PW) --user $(VERIPOOL_USER) verilator_man.html webftp.veripool.com:/web
 
 install-msg:
 	@echo "Installed!"
@@ -261,8 +293,9 @@ install-msg:
 	@echo
 
 uninstall:
-	-cd $(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
+	-cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
-	-cd $(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-rm -f $(DESTDIR)$(pkgdatadir)
 
 # autoheader might not change config_build.h.in, so touch a stamp file.
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in ${srcdir}/*/*/*.in \
@@ -287,7 +320,7 @@ configure: configure.ac
 maintainer-clean::
 	@echo "This command is intended for maintainers to use;"
 	@echo "rebuilding the deleted files requires makeinfo."
-	rm -f *.info* $(INFOS) faq.html verilator.html configure bin/*
+	rm -f *.info* $(INFOS) faq.html verilator.html configure
 
 clean mostlyclean distclean maintainer-clean maintainer-copy::
 	for dir in $(SUBDIRS); do \
@@ -296,7 +329,7 @@ clean mostlyclean distclean maintainer-clean maintainer-copy::
 	done
 
 clean mostlyclean distclean maintainer-clean::
-	rm -f $(SCRIPTS) *.tmp 
+	rm -f $(SCRIPTS) *.tmp
 	rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
 	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
 	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
@@ -312,6 +345,13 @@ TAGFILES=${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/[a-z]*.in \
 TAGS:	$(TAGFILES)
 	etags $(TAGFILES)
 
+######################################################################
+# Test targets
+
+dist-file-list:
+	@echo "begin-dist-file-list:";  # Scripts look for this
+	@echo $(wildcard $(DISTFILES))
+	@echo "end-dist-file-list:";  # Scripts look for this
 
 ######################################################################
 # Distributions
@@ -320,7 +360,7 @@ DISTCONFIG = src/config_build.h.in
 
 DISTTITLE := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e 's/v/V/' -e q $(DISTCONFIG))
 DISTNAME := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e q $(DISTCONFIG))
-DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([0-3]\?[0-9].[0-3]\?[0-9].[1-2][0-9][0-9][0-9]\).*/\1/' -e q $(DISTCONFIG))
+DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([1-2][0-9][0-9][0-9].[0-9]*[0-9].[0-9]*[0-9]\).*/\1/' -e q $(DISTCONFIG))
 
 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
@@ -339,14 +379,14 @@ dist: $(DISTDEP) maintainer-copy
 	chmod -R a+r $(DISTNAME)
 	tar chf $(DISTNAME).tar $(DISTNAME)
 	gzip --force --best $(DISTNAME).tar
+	mv $(DISTNAME).tar.gz $(DISTNAME).tgz
 	rm -fr $(DISTNAME)
 
 maintainer-diff:
 	svnorcvs diff $(DISTTAGNAME)
 
 preexist:
-	test ! -r ~/src/kits/$(DISTNAME).tar.gz
+	svnorcvs nexists $(DISTTAGNAME)
 
 maintainer-dist: preexist dist tag
-	cp *.gz ~/backpack
+	svnorcvs release $(DISTNAME).tgz
-	cp *.gz ~/src/kits

README

@@ -1,167 +0,0 @@
-1 Verilator
-***********
-
-This is the Verilator Package.
-
-1.1 Copyright
-=============
-
-This package is Copyright 2003-2007 by Wilson Snyder
-<[email protected]>.
-
-   You may distribute under the terms of either the GNU General Public
-License or the Artistic License, as specified in the Perl README file.
-
-   This code is provided with no warranty of any kind, and is used
-entirely at your own risk.
-
-1.2 Description
-===============
-
-Verilator converts synthesizable (not behavioral) Verilog code into C++
-or SystemC code.  It is not a complete simulator, just a translator.
-
-   Verilator is invoked with parameters similar to GCC or Synopsys's
-VCS.  It reads the specified Verilog code, lints it, and optionally
-adds coverage code.  For C++ format, it outputs .cpp and .h files.  For
-SystemC format, it outputs .sp files for the SystemPerl preprocessor
-available at http://veripool.com.
-
-   The resulting files are then compiled with C++.  The user writes a
-little C++ wrapper file, which instantiates the top level module.  This
-is compiled in C++, and linked with the Verilated files.
-
-   The resulting executable will perform the actual simulation.
-
-1.3 Obtaining Distribution
-==========================
-
-The latest version is available at `http://veripool.com/verilator.htm'
-
-   Download the latest package from that site, and decompress.  `gunzip
-verilator_version.tar.gz ; tar xvf verilator_version.tar'
-
-1.4 Directory Structure
-=======================
-
-The directories after de-taring are as follows:
-
-   * bin/verilator	     => Compiler Wrapper invoked on user Verilog code
-
-   * include/		     => Files that should be in your -I compiler
-     path
-
-   * include/verilated.cpp   => Global routines to link into your
-     simulator
-
-   * include/verilated.h     => Global headers
-
-   * include/verilated.v     => Stub defines for linting
-
-   * include/verilated.mk    => Common makefile
-
-   * src/		     => Translator source code
-
-   * test_v		     => Example Verilog code for other test dirs
-
-   * test_c		     => Example Verilog->C++ conversion
-
-   * test_sc		     => Example Verilog->SystemC conversion
-
-   * test_sp		     => Example Verilog->SystemPerl conversion
-
-   * test_vcs		     => Example Verilog->VCS conversion (test the
-     test)
-
-   * test_verilated	     => Internal tests
-
-   * test_regress	     => Internal tests
-
-1.5 Supported Systems
-=====================
-
-This version of verilator has been built and tested on:
-
-   * SuSE AMD64 i686-linux-2.6.5
-
-   Other users report success with Redhat Linux 2.4, Windows under
-Cygwin, HPUX and Solaris.  It should run with minor porting on any Unix
-system.
-
-1.6 Installation
-================
-
-  1. If you will be using SystemC (vs straight C++ output), download
-     SystemC 2.0.1 from `http://www.systemc.org'.  Follow their
-     installation instructions.  As described in the System-Perl README,
-     you will need to set SYSTEMC and/or SYSTEMC_KIT to point to this
-     download.  Also, set SYSTEMC_ARCH to the architecture name you used
-     with SystemC, generally 'linux' or 'cygwin'.
-
-  2. If you will be using SystemC, download and install Verilog-Perl,
-     `http://search.cpan.org/search?module=Verilog::Language'.
-
-  3. If you will be using SystemC, download and install System-Perl,
-     `http://search.cpan.org/search?module=SystemC::Netlist'.  Note
-     you'll need to set a `SYSTEMPERL' environment variable to point to
-     the downloaded kit (not the installed files.)  Also, make sure to
-     do a `make sc_patch'.
-
-  4. `cd' to the Verilator directory containing this README.
-
-  5. Type `./configure' to configure Verilator for your system.
-
-  6. Type `make' to compile Verilator.
-
-     On Cygwin (Windows) you may get a error about libperl.a not being
-     found.  You need to copy your perl libraries as follows.
-
-       1.   Type `perl -MExtUtils::Embed -e ldopts'
-
-       2.   It will show a directory name ending in /CORE.  cd to that
-          directory.
-
-       3.   `cp libperl5_6_1.a libperl.a'
-
-       4.   `cp libperl5_6_1.dll libperl.dll'
-
-       5.   `cp libperl5_6_1.def libperl.def'
-
-  7. Type `make test' to check the compilation.
-
-     You may get a error about the Bit::Vector perl package.  You will
-     need to install it if you want the tests to pass.  (Try `make
-     test_c' for a smaller test that doesn't require it.)
-
-     You may get a error about a typedef conflict for uint32_t.  Edit
-     verilated.h to change the typedef to work, probably to `typedef
-     unsigned long uint32_t;'.
-
-     If you get warnings, you might want to edit `include/verilated.mk'
-     to delete the lines that define VK_CPPFLAGS_WALL.
-
-  8.  There is no installation at present; this package runs from the
-     distribution directory.  Programs should set the environment
-     variable VERILATOR_ROOT to point to this distribution, then execute
-     $VERILATOR_ROOT/bin/verilator, which will find the path to all
-     needed files.
-
-     Verilator assumes you did a make in the SystemC kit directory.  If
-     not, you will need to populate `$SYSTEMC/include' and
-     `$SYSTEMC/lib-linux' appropriately.
-
-     If you will be modifying Verilator, you will probably want a second
-     stable copy of this kit for others to use while you experiment.
-
-  9. Detailed documentation and the man page can be seen by running:
-
-     bin/verilator -help
-
-     or reading verilator.txt in the same directory as this README.
-
-
-1.7 Limitations
-===============
-
-See verilator.txt (or execute `bin/verilator --help') for limitations.
-

TODO

@@ -1,13 +1,12 @@
-// $Id$
 // DESCRIPTION: Verilator: List of To Do issues.
 //
-// Copyright 2004-2007 by Wilson Snyder. This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 
 
 Features:
- 	Finish 3.400 new ordering fixes
+	Finish 3.400 new ordering fixes
 	Latch optimizations {Need here}
 	Task I/Os connecting to non-simple variables.
 	Fix nested casez statements expanding into to huge C++. [JeanPaul Vanitegem]
@@ -25,12 +24,13 @@ Features:
 	Coverage
 		Points should be per-scope like everything else rather then per-module
 		Expression coverage (see notes)
+	Constant functions for widths, etc, IE   "input [log2(PARAM):0] xx;"
 	More Verilog 2001 Support
-		C-style function and task arguments.  [Wim Michiels]
 		(* *) Attributes  (just ignore -- preprocessor?)
 		Real numbers (NEVER)
 		Recursive functions (NEVER)
 		Verilog configuration files (NEVER)
+	DPI to define C/C++ calls from Verilog
 
 Long-term Features
 	Assertions
@@ -49,7 +49,11 @@ Testing:
 
 Usability:
 	Better reporting of unopt problems, including what lines of code
-	Report more errors (all of them?) before exiting [Eugene Weber]	
+	Report more errors (all of them?) before exiting [Eugene Weber]
+
+Internal Code:
+	Eliminate the AstNUser* passed to all visitors; its only needed in V3Width,
+	and removing it will speed up and simplify all the other code.
 
 Performance:
 	Constant propagation
@@ -64,7 +68,7 @@ Performance:
 	Multithreaded execution
 	Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings.
 	Move _last sets and all other combo logic inside master
-		if() that triggers on all possible sense items 
+		if() that triggers on all possible sense items
 	Rewrite and combine V3Life, V3Subst
 		If block temp only ever set in one place to constant, propagate it
 			Used in t_mem for array delayed assignments
@@ -103,6 +107,12 @@ Performance:
 	If floped(a) & flopped(b) and no other a&b, then instead flop(a&b).
 	Sort by output bitselects so can combine more assignments (see DDP example dx_dm signal)
 
+	All of the temp vars that get set, exp pre_ vars and never feedback
+	(not flops) don't need to be stored in the structs, but instead can
+	be per-invocation, and even better register-colored-like to reuse
+	the space.  This will greatly reduce the data footprint.
+
+
 //**********************************************************************
 //* Detailed notes on 'todo' features
 
@@ -128,15 +138,15 @@ Selectable SystemC types based on widths (see notes below)
        c) a conditional whose possible values are (a) or (b)
 
  2) One can lose that fact that a node is a tristate node.  This happens
-    if a tristate node is assigned to a 'standard' node, or is used on 
+    if a tristate node is assigned to a 'standard' node, or is used on
     RHS of a conditional. The following infer tristate signals:
-       a) inout <SIGNAL> 
+       a) inout <SIGNAL>
-       b) tri <SIGNAL> 
+       b) tri <SIGNAL>
        c) assigning to 'Z' (maybe through a conditional)
     Note: tristate-ness of an output port determined only by
           statements in the module (not the instances it calls)
-  
+
  4) Tristate variables can't be multidimensional arrays
- 5) Only check tristate contention between modules (not within!)	
+ 5) Only check tristate contention between modules (not within!)
  6) Only simple compares with 'Z' are allowed (===)
 

bin/verilator

@@ -1,10 +1,9 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 ######################################################################
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 #
@@ -34,27 +33,7 @@ use Config;
 use Cwd qw(abs_path getcwd);
 
 use strict;
-use vars qw ($Debug %Vars $Opt $Opt_Make_Dir $Opt_Sp @Opt_Verilator_Sw
+use vars qw ($Debug @Opt_Verilator_Sw);
-	     $Opt_Trace
-	     %Modules
-	     );
-
-#######################################################################
-# Global constants -- Configuration info
-
-# Where to find real executables
-# We could find it by using $RealBin, but we require this path
-# so that when the user runs make, they will have it and not get strange error.
-$ENV{VERILATOR_ROOT} or die "%Error: verilator: VERILATOR_ROOT needs to be in environment\n";
-print "export VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n" if $Debug;
-
-# Read by verilator for populating makefile
-if (!defined $ENV{SYSTEMC_ARCH}) {
-    $ENV{SYSTEMC_ARCH} ||= (($Config{osname} =~ /solaris/i && "gccsparcOS5")
-			    || ($Config{osname} =~ /cygwin/i && "cygwin")
-			    || "linux");
-    print "export SYSTEMC_ARCH=$ENV{SYSTEMC_ARCH}\n" if $Debug;
-}
 
 #######################################################################
 #######################################################################
@@ -65,7 +44,6 @@ autoflush STDERR 1;
 
 $Debug = 0;
 my $opt_gdb;
-$Opt_Sp = undef;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -84,33 +62,15 @@ if (! GetOptions (
 		  # Major operating modes
 		  "help"	=> \&usage,
 		  "debug:s"	=> \&debug,
-		  "version!"	=> \&version,
+		  # "version!"	=> \&version,	# Also passthru'ed
 		  # Switches
 		  "gdb=s"	=> \$opt_gdb,	# Undocumented debugging
-		  "trace!"	=> \$Opt_Trace,
-		  "sp!"		=> sub {$Opt_Sp = 'sp';},
-		  "sc!"		=> sub {$Opt_Sp = 'sc';},
-		  "cc!"		=> sub {$Opt_Sp = 0;},
-		  #"ignc!"	=> ...,		# Undocumented debugging, disable $c but don't complain
 		  # Additional parameters
 		  "<>"		=> sub {},	# Ignored
 		  )) {
     pod2usage(-exitstatus=>2, -verbose=>0);
 }
 
-# Check configuration
-if ($Opt_Sp) {
-    (defined $ENV{SYSTEMC}) or die "%Error: verilator: Need \$SYSTEMC in environment\nProbably System-C isn't installed, see http://www.systemc.org\n";
-}
-if ($Opt_Sp eq 'sp' || $Opt_Trace) {
-    if (!defined $ENV{SYSTEMPERL}) {
-	my $try = "$ENV{W}/hw/utils/perltools/SystemC";
-	$ENV{SYSTEMPERL} = $try if -d $try;
-    }
-    (defined $ENV{SYSTEMPERL}) or die "%Error: verilator: Need \$SYSTEMPERL in environment for --sp or --trace\nProbably System-Perl isn't installed, see http://www.veripool.com/systemperl.html\n";
-    (-d "$ENV{SYSTEMPERL}/src") or die "%Error: verilator: \$SYSTEMPERL environment var doesn't seem to point to System-Perl kit\n";
-}
-
 # Determine runtime flags
 my $vcmd =(($opt_gdb?"$opt_gdb ":"")
 	   .verilator_bin()
@@ -123,8 +83,6 @@ run ($vcmd);
 #----------------------------------------------------------------------
 
 sub usage {
-    bin_version();
-    print '$Revision$$Date$ ', "\n";
     pod2usage(-exitstatus=>2, -verbose=>2);
 }
 
@@ -134,23 +92,16 @@ sub debug {
     $Debug = $level||3;
 }
 
-sub version {
-    bin_version();
-    exit (0);
-}
-
-sub bin_version {
-    ($ENV{VERILATOR_ROOT}) or print "%Warning: Unknown rev: VERILATOR_ROOT undefined\n";
-    run (verilator_bin()." --version");
-}
-
 #######################################################################
 #######################################################################
 # Builds
 
 sub verilator_bin {
-    my $bin = "$ENV{VERILATOR_ROOT}/".($ENV{VERILATOR_BIN}||"verilator_bin");
+    my $bin = "";
-    if ($Debug && -x "${bin}_dbg") { $bin = "${bin}_dbg"; }
+    # Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path
+    $bin .= $ENV{VERILATOR_ROOT}."/" if defined($ENV{VERILATOR_ROOT});
+    $bin .= ($ENV{VERILATOR_BIN}||"verilator_bin");
+    if ($Debug) { $bin = "${bin}_dbg"; }
     return $bin;
 }
 
@@ -165,8 +116,11 @@ sub run {
     system($command);
     my $status = $?;
     if ($status) {
+	if ($! =~ /no such file or directory/i) {
+	    warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
+	}
 	if ($Debug) {  # For easy rerunning
-	    warn "%Error: export VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n";
+	    warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
 	    warn "%Error: $command\n";
 	}
 	die "%Error: Command Failed $command\n";
@@ -205,7 +159,7 @@ code, lints it, and optionally adds coverage and waveform tracing code.
 For C++ and SystemC formats, it outputs .cpp and .h files.  For SystemPerl
 format, it outputs .sp files for the SystemPerl preprocessor, which greatly
 simplifies writing SystemC code and is available at
-L<http://www.veripool.com>.
+L<http://www.veripool.org>.
 
 The files created by Verilator are then compiled with C++.  The user writes
 a little C++ wrapper file, which instantiates the top level module, and
@@ -214,6 +168,71 @@ C++, and linked with the Verilated files.
 
 The resulting executable will perform the actual simulation.
 
+=head1 ARGUMENT SUMMARY
+
+This is a short summary of the arguments to Verilator.  See the detailed
+descriptions in the next sections for more information.
+
+    {file.v}                    Verilog top level filenames
+    {file.c/cc/cpp}             Optional C++ files to link in
+
+    --assert                    Enable all assertions
+    --autoflush                 Flush streams after all $displays
+    --bin <filename>            Override Verilator binary
+    --cc                        Create C++ output
+    --compiler <compiler-name>  Tune for specified C++ compiler
+    --coverage                  Enable all coverage
+    --coverage-line             Enable line coverage
+    --coverage-user             Enable PSL/SVL user coverage
+    -D<var>[=<value>]           Set preprocessor define
+    --debug                     Enable debugging
+    --debug-check               Enable debugging assertions
+    --dump-tree                 Enable dumping .tree files
+    -E                          Preprocess, but do not compile
+    --error-limit <value>	Abort after this number of errors
+    --exe                       Link to create executable
+    -f <file>                   Parse options from a file
+    --help                      Display this help.
+    -I<dir>                     Directory to search for includes
+    --inhibit-sim               Create function to turn off sim
+    --inline-mult <value>       Tune module inlining
+    --language <lang>           Language standard to parse
+    --lint-only                 Lint, but do not make output
+    --MMD                       Create .d dependency files
+    --MP                        Create phony dependency targets
+    --Mdir <directory>          Name of output object directory
+    --mod-prefix <topname>      Name to prepend to lower classes
+    --no-skip-identical         Disable skipping identical output
+    -O0                         Disable optimizations
+    -O3                         High performance optimizations
+    -O<optimization-letter>     Selectable optimizations
+    --output-split <bytes>      Split .cpp files into pieces
+    --output-split-cfuncs <statements>   Split .ccp functions
+    --pins64                    Use uint64_t's for 33-64 bit sigs
+    --prefix <topname>          Name of top level class
+    --profile-cfuncs            Name functions for profiling
+    --private                   Debugging; see docs
+    --psl                       Enable PSL parsing
+    --public                    Debugging; see docs
+    --sc                        Create SystemC output
+    --sp                        Create SystemPerl output
+    --stats                     Create statistics file
+    --top-module <topname>      Name of top level input module
+    --trace                     Enable waveform creation
+    --trace-depth <levels>      Depth of tracing
+    -U<var>                     Undefine preprocessor define
+    --underline-zero            Zero signals with leading _'s
+    -v <filename>               Verilog library
+    -Werror-<message>           Convert warning to error
+    -Wfuture-<message>          Disable unknown message warnings
+    -Wno-<message>              Disable warning
+    -x-assign <mode>            Initially assign Xs to this value
+    -y <dir>                    Directory to search for modules
+
+    +define+<var>+<value>       Set preprocessor define
+    +incdir+<dir>               Directory to search for includes
+    +libext+<ext>+[ext]...      Extensions for finding modules
+
 =head1 ARGUMENTS
 
 =over 4
@@ -235,6 +254,14 @@ linking with make rules you write yourself.
 Enable all assertions, includes enabling the --psl flag.  (If psl is not
 desired, but other assertions are, use --assert --nopsl.)
 
+See also --x-assign; setting "--x-assign unique" may be desirable.
+
+=item --autoflush
+
+After every $display or $fdisplay, flush the output stream.  This insures
+that messages will appear immediately but may reduce performance.  Defaults
+off, which will buffer output as provided by the normal C stdio calls.
+
 =item --bin I<filename>
 
 Rarely needed.  Override the default filename for Verilator itself.  When a
@@ -320,12 +347,23 @@ internal assertions, debugging messages, and intermediate form dump files.
 Rarely needed.  Enable internal debugging assertion checks, without
 changing debug verbosity.  Enabled automatically when --debug specified.
 
+=item --dump-tree
+
+Rarely needed.  Enable writing .tree debug files.  This is enabled with
+--debug, so "--debug --no-dump-tree" may be useful if the dump files are
+large and not desired.
+
 =item -E
 
 Preprocess the source code, but do not compile, as with 'gcc -E'.  Output
 is written to standard out.  Beware of enabling debugging messages, as they
 will also go to standard out.
 
+=item --error-limit <value>
+
+After this number of errors or warnings are encountered, exit.  Defaults to
+50.
+
 =item --exe
 
 Generate a executable.  You will also need to pass additional .cpp files on
@@ -345,12 +383,20 @@ change the SystemC modules instantiated.
 =item --inline-mult I<value>
 
 Tune the inlining of modules.  The default value of 2000 specifies that up
-to 2000 new operations may be added to the model by inlining, if more then
+to 2000 new operations may be added to the model by inlining, if more than
 this number of operations would result, the module is not inlined.  Larger
 values, or a value <= 1 will inline everything, will lead to longer compile
 times, but potentially faster runtimes.  This setting is ignored for very
 small modules; they will always be inlined, if allowed.
 
+=item --language I<value>
+
+Select the language to be used when first processing each Verilog file.
+The language value must be "1364-1995", "1364-2001", "1364-2001",
+"1364-2005", or "1800-2005".  This should only be used for legacy code, as
+the preferable option is to edit the code to repair new keywords, or add
+appropriate `begin_keywords.
+
 =item --lint-only
 
 Check the files for lint violations only, do not create any other output.
@@ -368,7 +414,7 @@ to gcc -MP option.
 =item --Mdir I<directory>
 
 Specifies the name of the Make object directory.  All generated files will
-be placed in this directory.
+be placed in this directory.  If not specified, "obj_dir" is used.
 
 =item --mod-prefix I<topname>
 
@@ -423,8 +469,9 @@ the backward-compatible default of sc_bv's.
 
 =item --prefix I<topname>
 
-Specifies the name of the top level class.  Defaults to the name of the top
+Specifies the name of the top level class and makefile.  Defaults to V
-level Verilog module.
+prepended to the name of the --top-module switch, or V prepended to the
+first Verilog filename passed on the command line.
 
 =item --profile-cfuncs
 
@@ -470,11 +517,25 @@ Specifies SystemPerl output mode; see also --cc and -sc.
 
 Creates a dump file with statistics on the design in {prefix}__stats.txt.
 
+=item --top-module I<topname>
+
+When the input Verilog contains more than one top level module, specifies
+the name of the top level Verilog module to become the top, and sets the
+default for if --prefix is not used.  This is not needed with standard
+designs with only one top.
+
 =item --trace
 
-Adds waveform tracing code to the model.  Having tracing compiled in may
+Adds waveform tracing code to the model.  Verilator will generate
-result in some small performance losses, even when waveforms are not turned
+additional {prefix}__Trace*.cpp files that will need to be compiled.  In
-on during model execution.
+addition Sp.cpp (for SystemC traces) or SpTraceVcdC.c (for C++ only) from
+the SystemPerl kit's src directory must be compiled and linked in.  If
+using the Verilator generated Makefiles, these will be added as source
+targets for you.  If you're not using the Verilator makefiles, you will
+need to add these to your Makefile manually.
+
+Having tracing compiled in may result in some small performance losses,
+even when waveforms are not turned on during model execution.
 
 =item --trace-depth I<levels>
 
@@ -496,22 +557,45 @@ Convert the specified warning message into a error message.  This is
 generally to discourage users from violating important site-wide rules, for
 example C<-Werror-NOUNOPTFLAT>.
 
+=item -Wfuture-I<message>
+
+Suppress unknown Verilator comments or warning messages with the given
+message code.  This is used to allow code written with pragmas for a later
+version of Verilator to run under a older version; add -Wfuture- arguments
+for each message code or comment that the new version supports which the
+older version does not support.
+
 =item -Wno-I<message>
 
 Disable the specified warning message.
 
+=item -Wno-lint
+
+Disable all lint related warning messages.  This is equivelent to
+"-Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASEZWITHX
+-Wno-CMPCONST -Wno-IMPLICIT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED
+-Wno-VARHIDDEN -Wno-WIDTH".
+
+It is strongly recommended you cleanup your code rather than using this
+option, it is only intended to be use when running test-cases of code
+received from third parties.
+
 =item -x-assign 0
 
 =item -x-assign 1
 
-=item -x-assign unique  (default)
+=item -x-assign fast (default)
+
+=item -x-assign unique
 
 Controls the two-state value that is replaced when an assignment to X is
-encountered.  -x-assign=0 converts all Xs to 0s, this is the fastest.
+encountered.  -x-assign=fast, the default, converts all Xs to whatever is
--x-assign=1 converts all Xs to 1s, this is nearly as fast, but more likely
+best for performance.  -x-assign=0 converts all Xs to 0s, and is also fast.
-to find reset bugs as active high logic will fire.  The default,
+-x-assign=1 converts all Xs to 1s, this is nearly as fast as 0, but more
--x-assign=func will call a function to determine the value, this allows
+likely to find reset bugs as active high logic will fire.  -x-assign=unique
-randomization of all Xs and is the slowest, but safest.
+will call a function to determine the value, this allows randomization of
+all Xs to find reset bugs and is the slowest, but safest for finding reset
+bugs in code.
 
 =back
 
@@ -577,7 +661,7 @@ We'll compile this example into C++.
       int main(int argc, char **argv, char **env) {
           Vour* top = new Vour;
           while (!Verilated::gotFinish()) { top->eval(); }
-          exit(0);	
+          exit(0);
       }
     EOF
 
@@ -637,7 +721,7 @@ This is an example similar to the above, but using SystemPerl.
           top = new Vour("top");   // SP_CELL (top, Vour);
           top->clk(clk);           // SP_PIN  (top, clk, clk);
           while (!Verilated::gotFinish()) { sc_start(1); }
-          exit(0);	
+          exit(0);
       }
     EOF
 
@@ -685,10 +769,10 @@ the test_sp directory in the distribution for an example.
 
 =head1 BENCHMARKING & OPTIMIZATION
 
-For best performance, run Verilator with the "-O3 -x-assign=0 --noassert"
+For best performance, run Verilator with the "-O3 -x-assign=fast
-flags.  The -O3 flag will require longer compile times, and -x-assign=0 may
+--noassert" flags.  The -O3 flag will require longer compile times, and
-increase the risk of reset bugs in trade for performance; see the above
+-x-assign=fast may increase the risk of reset bugs in trade for
-documentation for these flags.
+performance; see the above documentation for these flags.
 
 Minor Verilog code changes can also give big wins.  You should not have any
 UNOPTFLAT warnings from Verilator.  Fixing these warnings can result in
@@ -730,9 +814,9 @@ feedback driven compilation.  With GCC, using -fprofile-arcs, then
 
 You may uncover further tuning possibilities by profiling the Verilog code.
 Use Verilator's --profile-cfuncs, then GCC's -g -pg.  You can then run
-either oprofile or gprof to see where in the C++ code, and by looking at
+either oprofile or gprof to see where in the C++ code the time is spent.
-the mangled function name where in the Verilog code most of the time is
+Run the gprof output through verilator_profcfunc and it will tell you what
-being spent.
+Verilog line numbers on which most of the time is being spent.
 
 When done, please let the author know the results.  I like to keep tabs on
 how Verilator compares, and may be able to suggest additional improvements.
@@ -761,6 +845,7 @@ For -sp mode, instead of .cpp and .h it creates:
 
 In certain optimization modes, it also creates:
 
+    {prefix}__Inlines.h			// Inline support functions
     {prefix}__Slow.cpp			// Constructors and infrequent routines
     {prefix}__Syms.cpp			// Global symbol table C++
     {prefix}__Syms.h			// Global symbol table header
@@ -790,14 +875,16 @@ After running Make, the C++ compiler should produce the following:
 
 Required for SystemC output mode.  If set, specifies the directory
 containing the SystemC distribution.  This is used to find the SystemC
-include files.
+include files.  If not specified, it will come from a default optionally
+specified at configure time (before Verilator was compiled).
 
 =item SYSTEMC_ARCH
 
 Specifies the architecture name used by the SystemC kit.  This is the part
 after the dash in the lib-{...} directory name created by a 'make' in the
 SystemC distribution.  If not set, Verilator will try to intuit the proper
-setting.
+setting, or use the default optionally specified at configure time (before
+Verilator was compiled).  .
 
 =item SYSTEMC_CXX_FLAGS
 
@@ -807,7 +894,9 @@ building the SystemC model.
 =item SYSTEMPERL
 
 Specifies the directory containing the Verilog-Perl distribution kit.  This
-is used to find the Verilog-Perl library and include files.
+is used to find the Verilog-Perl library and include files.  If not
+specified, it will come from a default optionally specified at configure
+time (before Verilator was compiled).
 
 =item VCS_HOME
 
@@ -823,7 +912,9 @@ for debugging and selecting between multiple operating system builds.
 =item VERILATOR_ROOT
 
 Specifies the directory containing the distribution kit.  This is used to
-find the executable, Perl library, and include files.
+find the executable, Perl library, and include files.  If not specified, it
+will come from a default optionally specified at configure time (before
+Verilator was compiled).
 
 =back
 
@@ -848,7 +939,7 @@ example:
 	unsigned int main_time = 0;	// Current simulation time
 
 	double sc_time_stamp () {	// Called by $time in Verilog
-    	    return main_time;
+	    return main_time;
 	}
 
 	int main() {
@@ -917,7 +1008,7 @@ To support this, none of the files that Verilator produces will reference
 any configure generated build-system specific files, such as config.h
 (which is renamed in Verilator to config_build.h to reduce confusion.)  The
 disadvantage of this approach is that include/verilatedos.h must
-self-detect the requirements of the target system, rather then using
+self-detect the requirements of the target system, rather than using
 configure.
 
 The target system may also require edits to the Makefiles, the simple
@@ -936,6 +1027,8 @@ declarations inside port lists.
 Verilator supports the `begin_keywords and `end_keywords compiler
 directives.
 
+Verilator supports $clog2.
+
 Verilator partially supports the uwire keyword.
 
 =head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
@@ -944,12 +1037,14 @@ Verilator currently has very minimal support for SystemVerilog. As
 SystemVerilog features enter common usage they will be added.  Contact the
 author if a feature you need is missing.
 
-Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
+Verilator implements the full SystemVerilog 1800-2005 preprocessor,
 including function call-like preprocessor defines.
 
-Verilator supports $bits, $countones, $error, $fatal, $info, $isunknown,
+Verilator supports ==? and !=? operators, $bits, $countones, $error,
-$onehot, $onehot0, $warning, always_comb, always_ff, always_latch,
+$fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb,
-do-while, and final.  It also supports .name and .* interconnection.
+always_ff, always_latch, do-while, and final.
+
+It also supports .name and .* interconnection.
 
 Verilator partially supports assert.
 
@@ -1030,7 +1125,7 @@ call C++ functions from your Verilog code.
 String arguments will be put directly into the output C++ code.  Expression
 arguments will have the code to evaluate the expression inserted.  Thus to
 call a C++ function, $c("func(",a,")") will result in 'func(a)' in the
-output C++ code.  For input arguments, rather then hard-coding variable
+output C++ code.  For input arguments, rather than hard-coding variable
 names in the string $c("func(a)"), instead pass the variable as an
 expression $c("func(",a,")").  This will allow the call to work inside
 Verilog functions where the variable is flattened out, and also enable
@@ -1195,7 +1290,7 @@ lint_restore*/.  For example:
 If SOME_WARNING was on before the lint_off, it will now be restored to on,
 and if it was off before the lint_off it will remain off.
 
-=item /*verilator no_inline_task*/ 
+=item /*verilator no_inline_task*/
 
 Used in a function or task variable definition section to specify the
 function or task should not be inlined into where it is used.  This may
@@ -1225,10 +1320,9 @@ Wide variables over 64 bits cannot be function returns, to avoid exposing
 complexities.  However, wide variables can be input/outputs; they will be
 passed as references to an array of 32 bit numbers.
 
-This feature is still somewhat experimental.  Generally, only the values of
+Generally, only the values of stored state (flops) should be written, as
-stored state (flops) should be written, as the model will NOT notice
+the model will NOT notice changes made to variables in these functions.
-changes made to variables in these functions.  (Same as when a signal is
+(Same as when a signal is declared public.)
-declared public.)
 
 =item /*verilator public_flat*/ (variable)
 
@@ -1397,7 +1491,7 @@ When initializing an array, you need to use non-delayed assignments.  This
 is done in the interest of speed; if delayed assignments were used, the
 simulator would have to copy large arrays every cycle.  (In smaller loops,
 loop unrolling allows the delayed assignment to work, though it's a bit
-slower then a non-delayed assignment.)  Here's an example
+slower than a non-delayed assignment.)  Here's an example
 
 	always @ (posedge clk)
             if (~reset_l) begin
@@ -1434,6 +1528,14 @@ This section describes specific limitations for each language keyword.
 
 =over 4
 
+=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords,
+`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords,
+`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor,
+`systemc_dtor, `systemc_header, `systemc_imp_header,
+`systemc_implementation, `systemc_interface, `timescale, `undef, `verilog
+
+Fully supported.
+
 =item always, always_comb, always_ff, always_latch, and, assign, begin,
 buf, case, casex, casez, default, defparam, do-while, else, end, endcase,
 endfunction, endgenerate, endmodule, endspecify, endtask, final, for,
@@ -1453,8 +1555,9 @@ All specify blocks and timing checks are ignored.
 Verilator does not perform warning checking on uwires, it treats the uwire
 keyword as if it were the normal wire keyword.
 
-=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
+=item $bits, $countones, $error, $fatal, $finish, $info, $isunknown,
-$readmemh, $signed, $stop, $time, $unsigned
+$onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time,
+$unsigned, $warning.
 
 Generally supported.
 
@@ -1468,21 +1571,36 @@ argument (as with C's printf), you cannot simply list variables standalone.
 The sized display functions are rarely used and so not supported.  Replace
 them with a $write with the appropriate format specifier.
 
-=item $fopen, $fclose, $fdisplay, $fwrite
+=item $finish, $stop
+
+The rarely used optional parameter to $finish and $stop is ignored.
+
+=item $fopen, $fclose, $fdisplay, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite
 
 File descriptors passed to the file PLI calls must be file descriptors, not
 MCDs, which includes the mode parameter to $fopen being mandatory.
 Verilator will convert the integer used to hold the file descriptor into a
 internal FILE*. To prevent core dumps due to mis-use, and because integers
 are 32 bits while FILE*s may be 64 bits, the descriptor must be stored in a
-reg [63:0] rather then an integer.  The define `verilator_file_descriptor in
+reg [63:0] rather than an integer.  The define `verilator_file_descriptor in
 verilated.v can be used to hide this difference.
 
+=item $fscanf, $sscanf
+
+Only integer formats are supported; %e, %f, %m, %r, %v, and %z are not
+supported.
+
 =item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
 $setup, $setuphold, $skew, $timeskew, $width
 
 All specify blocks and timing checks are ignored.
 
+=item $random
+
+$random does not support the optional argument to set the seed.  Use the
+srand function in C to accomplish this, and note there is only one random
+number generator (not one per module).
+
 =item $readmemb, $readmemh
 
 Read memory commands should work properly.  Note Verilator and the Verilog
@@ -1567,6 +1685,16 @@ L<http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
 
+=item CASEWITHX
+
+Warns that a case statement contains a constant with a C<x>.  Verilator is
+two-state so interpret such items as always false.  Note a common error is
+to use a C<X> in a case or casez statement item; often what the user
+instead insteaded is to use a casez with C<?>.
+
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CMPCONST
 
 Warns that you are comparing a value in a way that will always be constant.
@@ -1607,7 +1735,7 @@ output from a sub-module.)  While legal in Verilog, implicit declarations
 only work for single bit wide signals (not buses), do not allow using a
 signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
-Emacs, available from L<http://www.veripool.com/>
+Emacs, available from L<http://www.veripool.org/>
 
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
@@ -1641,6 +1769,33 @@ not really needed.  The best solution is to insure that each module is in a
 unique file by the same name.  Otherwise, make sure all library files are
 read in as libraries with -v, instead of automatically with -y.
 
+=item REDEFMACRO
+
+Warns that you have redefined the same macro with a different value, for
+example:
+
+    `define MACRO def1
+    //...
+    `define MACRO otherdef
+
+The best solution is to use a different name for the second macro.  If this
+is not possible, add a undef to indicate the code is overriding the value:
+
+    `define MACRO def1
+    //...
+    `undef MACRO
+    `define MACRO otherdef
+
+=item STMTDLY
+
+Warns that you have a statement with a delayed time in front of it, for
+example:
+
+    #100 $finish;
+
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item TASKNSVAR
 
 Error when a call to a task or function has a output from that task tied to
@@ -1772,7 +1927,7 @@ correctly.
 Warns that based on width rules of Verilog, two operands have different
 widths.  Verilator generally can intuit the common usages of widths, and
 you shouldn't need to disable this message like you do with most lint
-programs.  Generally other then simple mistakes, you have two solutions:
+programs.  Generally other than simple mistakes, you have two solutions:
 
 If it's a constant 0 that's 32 bits or less, simply leave it
 unwidthed. Verilator considers zero to be any width needed.
@@ -1788,6 +1943,24 @@ The best fix, which clarifies intent and will also make all tools happy is:
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
 
+=item WIDTHCONCAT
+
+Warns that based on width rules of Verilog, a concatenate or replication
+has a undeterminate width.  In most cases this violates the Verilog rule
+that widths inside concatenates and replicates must be sized, and should be
+fixed in the code.
+
+    wire [63:0] concat = {1,2};
+
+An example where this is technically legal (though still bad form) is:
+
+    parameter PAR = 1;
+    wire [63:0] concat = {PAR,PAR};
+
+The correct fix is to either size the 1 ("32'h1"), or add the width to the
+parameter definition ("parameter [31:0]"), or add the width to the
+parameter usage ("{PAR[31:0],PAR[31:0]}".
+
 =back
 
 The following describes the less obvious errors:
@@ -1841,13 +2014,16 @@ Visual C++ Version 7 or newer, but this is not tested by the author.
 
 =item Can you provide binaries?
 
-At this time I'd prefer to get patches out quickly then have to generate
+Verilator is available as a RPM for SuSE and perhaps other systems; this is
-myriad binaries for many different OS flavors.  People have generally
+done by porters and may slightly lag the primary distribution.  If there
-requested binaries when they are having problems with their C++
+isn't a binary build for your distribution, how about you set one up?
-compiler. Alas, binaries won't help this, as in the end a fully working C++
+Please contact the authors for assistance.
-compiler is required to compile the output of Verilator.
 
-=item How can it be faster then (name-the-simulator)?
+Note people sometimes request binaries when they are having problems with
+their C++ compiler. Alas, binaries won't help this, as in the end a fully
+working C++ compiler is required to compile the output of Verilator.
+
+=item How can it be faster than (name-the-simulator)?
 
 Generally, the implied part of the question is "... with all of their
 manpower they can put into it."
@@ -1861,9 +2037,28 @@ so your simulator shouldn't have to be -- and Verilator is closer to the
 synthesis interpretation, so this is a good thing for getting working
 silicon.
 
-=item How do I generate waveforms (traces) in C++?
+=item May programs I create with Verilator remain under my own copyright?
 
-See the next question for SystemC mode.
+Yes, it's just like using GCC on your programs.  If you change Verilator
+itself, you must make the source code available under the GNU Public
+License.  However, the include and generated files use the GNU Lesser
+Public License, which means that files using them are NOT required to be released.
+
+You also have the option of using the Perl Artistic License, which again
+does not require you release your Verilog or generated code.
+
+=item Why is running Verilator so slow?
+
+Verilator needs more memory than the resulting simulator will require, as
+Verilator creates internally all of the state of the resulting simulator in
+order to optimize it.  If it takes more than a minute or so (and you're not
+using --debug), see if your machine is paging; most likely you need to run
+it on a machine with more memory.  Verilator is a full 64 bit application
+and may use more than 4GB, but about 1GB is the maximum typically needed.
+
+=item How do I generate waveforms (traces) in C++ or SystemC?
+
+See the next question for tracing in SystemPerl mode.
 
 Add the --trace switch to Verilator, and make sure the SystemPerl package
 is installed. SystemC itself does not need to be installed for C++ only
@@ -1872,13 +2067,15 @@ the SystemPerl kit and point the SYSTEMPERL environment variable to the
 untarred directory.
 
 In your top level C code, call Verilated::traceEverOn(true).  Then create a
-SpTraceVcdC object.  For an example, see the call to SpTraceVcdC in the
+SpTraceVcdC object, and in your main loop call "trace_object->dump(time)"
-test_c/sc_main.cpp file of the distribution.
+every time step, and finally call "trace_object->close()".  For an example,
+see the call to SpTraceVcdC in the test_c/sim_main.cpp file of the
+distribution.
 
 You also need to compile SpTraceVcdC.cpp and add it to your link.  This is
 done for you if using the Verilator --exe flag.
 
-=item How do I generate waveforms (traces) in SystemC?
+=item How do I generate waveforms (traces) in SystemPerl?
 
 Add the --trace switch to Verilator, and make sure the SystemPerl package
 is installed.
@@ -1905,6 +2102,26 @@ the "verilator" define for you, so just wrap the code in a ifndef region:
       Something_Verilator_Dislikes;
    `endif
 
+=item Why do I get "unexpected `do'" or "unexpected `bit'" errors?
+
+Do, bit, ref, return, and other words are now SystemVerilog keywords.  You
+should change your code to not use them to insure it works with newer
+tools.  Alternatively, surround them by the Verilog 2005/SystemVerilog
+begin_keywords pragma to indicate Verilog 2001 code.
+
+   `begin_keywords "1364-2001"
+      integer bit; initial bit = 1;
+   `end_keywords
+
+If you want the whole file to be parsed as Verilog 2001, just create a
+file with
+
+   `begin_keywords "1364-2001"
+
+and add it before other Verilog files on the command line.  (Note this will
+also change the default for --prefix, so if you're not using --prefix, you
+will now need to.)
+
 =item How do I prevent my assertions from firing during reset?
 
 Call Verilated::assertOn(false) before you first call the model, then turn
@@ -1944,7 +2161,7 @@ use GCC 2.95, or GCC 3.4 you'll have faster builds.  Two ways to cheat are
 to compile on parallel machines and avoid compilations altogether.  See the
 --output-split option, and the web for the ccache, distcc and icecream
 packages, and the Make::Cache package available from
-L<http://www.veripool.com/>. Make::Cache will skip GCC runs between
+L<http://www.veripool.org/>. Make::Cache will skip GCC runs between
 identical source builds, even across different users.
 
 =item Why do so many files need to recompile when I add a signal?
@@ -1954,18 +2171,56 @@ uses one large symbol table, as that results in 2-3 less assembly
 instructions for each signal access.  This makes the execution time 10-15%
 faster, but can result in more compilations when something changes.
 
+=item How do I access functions/tasks in C?
+
+Write a Verilog function or task with input/outputs that match what you
+want to call in with C.  Then mark that function public.
+
+Verilog inputs of one bit become C++ bool inputs.  Inputs 32 bits or
+smaller become C uint32_t inputs, 64-32 bits become C uint64_t inputs, and
+wider signals become arrays of 32 bits.  Outputs are passed as references
+to bool, uint32_t, uint64_t or uint32_t[] arrays.
+
+Signals wider than 64 bits are passed as an array of 32-bit uint32_t's.
+Thus to read bits 31:0, access signal[0], and for bits 63:32, access
+signal[1].  Unused bits (for example bit numbers 65-96 of a 65 bit vector)
+will always be zero.  if you change the value you must make sure to pack
+zeros in the unused bits or core-dumps may result.  (Because Verilator
+strips array bound checks where it believes them to be unnecessary.)
+
+In the SYSTEMC example above, if you had in our.v:
+
+   task publicSetBool;
+      // verilator public
+      input in_bool;
+      var_bool = in_bool;
+   endtask
+
+From the sc_main.cpp file, you'd then:
+
+    #include "Vour.h"
+    #include "Vour_our.h"
+    top->v.publicSetBool(value);
+
+See additional notes under the /*verilator public*/ section.
+
 =item How do I access signals in C?
 
-First, declare the signals you will be accessing with a /*verilator
+The best thing is to make a Verilator public task or function accessor that
-public*/ comment before the closing semicolon.  Then scope into the C++
+can read or write that signal, as described in the previous FAQ.  This will
-class to read the value of the signal, as you would any other member variable.
+allow Verilator to better optimize the model.
+
+If you really want raw access to the signals, declare the signals you will
+be accessing with a /*verilator public*/ comment before the closing
+semicolon.  Then scope into the C++ class to read the value of the signal,
+as you would any other member variable.
 
 Signals are the smallest of 8 bit chars, 16 bit shorts, 32 bit longs, or 64
 bit long longs that fits the width of the signal.  Generally, you can use
 just uint32_t's for 1 to 32 bits, or uint64_t for 1 to 64 bits, and the
 compiler will properly up-convert smaller entities.
 
-Signals wider then 64 bits are stored as an array of 32-bit uint32_t's.
+Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
 Thus to read bits 31:0, access signal[0], and for bits 63:32, access
 signal[1].  Unused bits (for example bit numbers 65-96 of a 65 bit vector)
 will always be zero.  if you change the value you must make sure to pack
@@ -2029,7 +2284,10 @@ outputs.  Now, the following should fail:
     cd test_regress
     t/t_BUG.pl
 
-Finally, Mail the bug report to C<[email protected]>.
+Finally, report the bug using the bug tracker at
+L<http://www.veripool.org/verilator>.  The bug will become publicly
+visible; if this is unacceptable, mail the bug report to
+C<[email protected]>.
 
 =head1 HISTORY
 
@@ -2056,8 +2314,8 @@ scratch in C++.  This added many optimizations, yielding about a 2-5x
 performance gain.
 
 Currently, various language features and performance enhancements are added
-as the need arises.  Verilator is now about 2x faster then in 2002, and is
+as the need arises.  Verilator is now about 2x faster than in 2002, and is
-faster then many popular commercial simulators.
+faster than many popular commercial simulators.
 
 =head1 CONTRIBUTORS
 
@@ -2069,7 +2327,7 @@ Communications, Sun Microsystems, Nauticus Networks, and SiCortex.
 
 The people who have contributed code or other major functionality are Paul
 Wasson, Duane Galbi, and Wilson Snyder.  Major testers include Jeff Dutton,
-Ralf Karge and Wim Michiels.
+Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
 
 Some of the people who have provided ideas and feedback for Verilator
 include Hans Van Antwerpen, Jens Arm, David Black, Gregg Bouchard, Chris
@@ -2082,9 +2340,9 @@ Eugene Weber, Leon Wildman, and Mat Zeno.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/>.
 
-Copyright 2003-2007 by Wilson Snyder.  Verilator is free software; you can
+Copyright 2003-2008 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License or the Perl Artistic License.
 
@@ -2096,7 +2354,7 @@ Major concepts by Paul Wasson and Duane Galbi.
 
 =head1 SEE ALSO
 
-L<systemperl>, L<vcoverage>, L<make>
+L<verilator_profcfunc>, L<systemperl>, L<vcoverage>, L<make>
 
 =cut
 

bin/verilator_difftree

@@ -1,10 +1,9 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 ######################################################################
 #
-# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
 # program is free software; you can redistribute it and/or modify it under
 # the terms of either the GNU Lesser General Public License or the Perl
 # Artistic License.
@@ -35,12 +34,13 @@ my $Opt_A;
 my $Opt_B;
 autoflush STDOUT 1;
 autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
 if (! GetOptions (
 		  "help"	=> \&usage,
 		  "debug"	=> \&debug,
 		  "<>"		=> \&parameter,
 		  )) {
-    usage();
+    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
 }
 
 defined $Opt_A or die "%Error: No old diff filename\n";
@@ -114,7 +114,6 @@ sub filter {
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -129,7 +128,7 @@ sub parameter {
 	$Opt_A = $param;
     } elsif (!defined $Opt_B) {
 	$Opt_B = $param;
-    } else {	
+    } else {
 	die "%Error: Unknown parameter: $param\n";
     }
 }
@@ -177,9 +176,9 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/verilator>.
 
-Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License or the Perl Artistic License.
 

bin/verilator_includer

@@ -1,10 +1,9 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 # DESCRIPTION: Print include statements for each ARGV
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 ######################################################################

bin/verilator_profcfunc

@@ -0,0 +1,209 @@
+: # -*-Mode: perl;-*- use perl, wherever it is
+eval 'exec perl -wS $0 ${1+"$@"}'
+  if 0;
+######################################################################
+#
+# Copyright 2007-2008 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use warnings;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+
+
+#======================================================================
+# main
+
+$Debug = 0;
+my $Opt_File;
+autoflush STDOUT 1;
+autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
+if (! GetOptions (
+		  "help"	=> \&usage,
+		  "debug"	=> \&debug,
+		  "<>"		=> \&parameter,
+		  )) {
+    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
+}
+
+defined $Opt_File or die "%Error: No filename given\n";
+
+profcfunc($Opt_File);
+
+#----------------------------------------------------------------------
+
+sub usage {
+    pod2usage(-verbose=>2, -exitval => 2);
+    exit (1);
+}
+
+sub debug {
+    $Debug = 1;
+}
+
+sub parameter {
+    my $param = shift;
+    if (!defined $Opt_File) {
+	$Opt_File = $param;
+    } else {
+	die "%Error: Unknown parameter: $param\n";
+    }
+}
+
+#######################################################################
+
+sub profcfunc {
+    my $filename = shift;
+    # Remove hex numbers before diffing
+    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
+
+    my %funcs;
+
+    while (defined (my $line=$fh->getline())) {
+	if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+.*\s+(\S+)\s*$/) {
+	    my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
+	    $funcs{$func}{pct} += $pct;
+	    $funcs{$func}{sec} += $sec;
+	    $funcs{$func}{calls} += $calls;
+	}
+    }
+    $fh->close;
+
+    # Find modules
+    my %verilated_mods;
+    foreach my $func (keys %funcs) {
+	if ($func =~ /(.*)::_eval\(.*__Syms.*\)$/) {
+	    $verilated_mods{$1} = qr/^$1/;
+	}
+    }
+
+    # Resort by Verilog name
+    my %vfuncs;
+    my %groups;
+    foreach my $func (keys %funcs) {
+	my $vfunc = $func;
+	my $design;
+	foreach my $vde (keys %verilated_mods) {
+	    if ($func =~ /$verilated_mods{$vde}/) {
+		$design=$vde;
+		last;
+	    }
+	}
+	if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__([0-9]+)\(/) {
+	    $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
+	    $groups{"Verilog Blocks under $design"} += $funcs{$func}{pct};
+	} else {
+	    if ($design) {
+		$vfunc = sprintf("VCommon   %s", $func);
+		$groups{"Common code under $design"} += $funcs{$func}{pct};
+	    } else {
+		$vfunc = sprintf("C++       %s", $func);
+		$groups{'C++'} += $funcs{$func}{pct};
+	    }
+	}
+	$vfuncs{$vfunc} = $funcs{$func};
+    }
+
+    print("Overall summary:\n");
+    print("  % time\n");
+    foreach (sort (keys %groups)) {
+	printf("  %6.2f  In all %s\n", $groups{$_}, $_);
+    }
+    print("\n");
+
+
+    print("Verilog code profile:\n");
+    print("   These are split into three categories:\n");
+    print("      C++:     Time in non-Verilated C++ code\n");
+    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
+    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
+    print("\n");
+
+    print("  %   cumulative   self              \n");
+    print(" time   seconds   seconds    calls   type      filename and line number\n");
+
+    my $cume = 0;
+    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
+			    || $a cmp $b}
+		      (keys %vfuncs)) {
+	$cume += $vfuncs{$func}{sec};
+	printf +("%6.2f %9.2f %8.2f %8d   %s\n",
+		 $vfuncs{$func}{pct},
+		 $cume, $vfuncs{$func}{sec},
+		 $vfuncs{$func}{calls},
+		 $func);
+    }
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+verilator_profcfunc - Read gprof report created with --profile-cfuncs
+
+=head1 SYNOPSIS
+
+  verilator --profile-cfuncs ....
+  gcc --ggdb -pg ....
+  {run executable}
+  gprof
+  verilator_profcfuncs gprof.out
+
+=head1 DESCRIPTION
+
+Verilator_profcfunc reads a profile report created by gprof.  The names of
+the functions are then transformed, assuming the user used verilator's
+--profile-cfuncs, and a report printed showing the percentage of time, etc,
+in each Verilog block.
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+The latest version is available from L<http://www.veripool.org/>.
+
+Copyright 2007-2008 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+C<verilator>
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
+### End:

configure.ac

@@ -1,23 +1,48 @@
-dnl $Id$
 dnl DESCRIPTION: Process this file with autoconf to produce a configure script.
-dnl Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+dnl Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 dnl redistribute it and/or modify it under the terms of either the GNU
 dnl General Public License or the Perl Artistic License.
 
-AC_REVISION($Revision$)dnl
 AC_INIT(src/Verilator.cpp)
 AC_CONFIG_HEADER(src/config_build.h)
 
 dnl Special Substitutions
+AC_ARG_ENABLE(defenv,
+   [AS_HELP_STRING([--disable-defenv], [disable hardcoded default environment variables])],
+   CFG_WITH_DEFENV=$enableval,
+   CFG_WITH_DEFENV=yes)
+AC_SUBST(CFG_WITH_DEFENV)
+
+dnl Compiler flags
+CXX=g++
+CFLAGS=-I${includedir}
+CPPFLAGS=-I${includedir}
+CXXFLAGS=-I${includedir}
+LDFLAGS=-L${libdir}
 
 dnl Checks for programs.
-CXX=g++
 AC_PROG_CC
 AC_PROG_CXX
 AC_PROG_INSTALL
+
+AC_LANG_PUSH(C++)
+AC_MSG_CHECKING([that C++ compiler can compile simple program])
+AC_TRY_RUN([int main() { return 0; }],
+           AC_MSG_RESULT(yes),
+           AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]))
+
 AC_PATH_PROG(PERL,perl)
-AC_PATH_PROG(YACC,bison)
+if test "x$PERL" = "x" ; then
+   AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
+fi
 AC_PATH_PROG(LEX,flex)
+if test "x$LEX" = "x" ; then
+   AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it])
+fi
+AC_PATH_PROG(YACC,bison)
+if test "x$YACC" = "x" ; then
+   AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it])
+fi
 
 dnl Checks for libraries.
 

include/verilated.cpp

@@ -1,15 +1,15 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //=========================================================================
 ///
 /// \file
@@ -18,20 +18,19 @@
 ///	This file must be compiled and linked against all objects
 ///	created from Verilator.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //=========================================================================
 
 #include "verilated.h"
-#include <string.h>
+#include <cctype>
-#include <ctype.h>
 
 #define VL_VALUE_STRING_MAX_WIDTH 1024	///< Max static char array for VL_VALUE_STRING
 
 //===========================================================================
 // Global variables
 
-int  Verilated::s_randReset = false;
+int  Verilated::s_randReset = 0;
 int  Verilated::s_debug = 1;
 bool Verilated::s_calcUnusedSigs = false;
 bool Verilated::s_gotFinish = false;
@@ -80,23 +79,43 @@ IData VL_RAND32() {
 #endif
 }
 
-IData VL_RAND_RESET_I(int outBits) {
+IData VL_RANDOM_I(int obits) {
+    return VL_RAND32() & VL_MASK_I(obits);
+}
+
+QData VL_RANDOM_Q(int obits) {
+    QData data = ((QData)VL_RAND32()<<VL_ULL(32)) | (QData)VL_RAND32();
+    return data & VL_MASK_Q(obits);
+}
+
+WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) {
+    for (int i=0; i<VL_WORDS_I(obits); i++) {
+	if (i<(VL_WORDS_I(obits)-1)) {
+	    outwp[i] = VL_RAND32();
+	} else {
+	    outwp[i] = VL_RAND32() & VL_MASK_I(obits);
+	}
+    }
+    return outwp;
+}
+
+IData VL_RAND_RESET_I(int obits) {
     if (Verilated::randReset()==0) return 0;
     IData data = ~0;
     if (Verilated::randReset()!=1) {	// if 2, randomize
-	data = VL_RAND32();
+	data = VL_RANDOM_I(obits);
     }
-    if (outBits<32) data &= VL_MASK_I(outBits); 
+    if (obits<32) data &= VL_MASK_I(obits);
     return data;
 }
 
-QData VL_RAND_RESET_Q(int outBits) {
+QData VL_RAND_RESET_Q(int obits) {
     if (Verilated::randReset()==0) return 0;
     QData data = VL_ULL(~0);
     if (Verilated::randReset()!=1) {	// if 2, randomize
-	data = ((QData)VL_RAND32()<<VL_ULL(32)) | (QData)VL_RAND32();
+	data = VL_RANDOM_Q(obits);
     }
-    if (outBits<64) data &= VL_MASK_Q(outBits); 
+    if (obits<64) data &= VL_MASK_Q(obits);
     return data;
 }
 
@@ -119,94 +138,351 @@ WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) {
 //===========================================================================
 // Formatting
 
-const char* VL_VALUE_FORMATTED_Q(int obits, char fmt, bool drop0, QData ld) {
+// Do a va_arg returning a quad, assuming input argument is anything less than wide
-    // Convert value into %b/%o/%x/%s/%u/%d formatted string
+#define _VL_VA_ARG_Q(ap, bits) (((bits) <= VL_WORDSIZE) ? va_arg(ap,IData) : va_arg(ap,QData))
-    // Note uses a single buffer; presumes only one call per printf
+
-    static VL_THREAD char str[VL_VALUE_STRING_MAX_WIDTH];
+void _vl_vsformat(string& output, const char* formatp, va_list ap) {
-    char* strp = &str[0];
+    // Format a Verilog $write style format into the output list
-    int lsb=obits-1;
+    // The format must be pre-processed (and lower cased) by Verilator
-    if (drop0) while (lsb && !VL_BITISSET_Q(ld,lsb)) lsb--;
+    // Arguments are in "width, arg-value (or WDataIn* if wide)" form
-    switch (fmt) {
+    //
-    case 'd':
+    // Note uses a single buffer internally; presumes only one usage per printf
-	sprintf(str,"%lld",(vlsint64_t)(VL_EXTENDS_QQ(obits,obits,ld)));
+    // Note also assumes variables < 64 are not wide, this assumption is
-	return str;
+    // sometimes not true in low-level routines written here in verilated.cpp
-    case 'u':
+    static VL_THREAD char tmp[VL_VALUE_STRING_MAX_WIDTH];
-	sprintf(str,"%llu",ld);
+    bool inPct = false;
-	return str;
+    bool widthSet = false;
-    case 's':
+    int width = 0;
-	for (; lsb>=0; lsb--) {
+    const char* pos = formatp;
-	    lsb = (lsb / 8) * 8; // Next digit
+    for (; *pos; ++pos) {
-	    IData charval = (ld>>VL_BITBIT_Q(lsb)) & 0xff;
+	if (!inPct && pos[0]=='%') {
-	    *strp++ = (charval==0)?' ':charval;
+	    inPct = true;
+	    widthSet = false;
+	    width = 0;
+	} else if (!inPct) {   // Normal text
+	    // Fast-forward to next escape and add to output
+	    const char *ep = pos;
+	    while (ep[0] && ep[0]!='%') ep++;
+	    if (ep != pos) {
+		output += string(pos, ep-pos);
+		pos += ep-pos-1;
+	    }
+	} else { // Format character
+	    inPct = false;
+	    char fmt = pos[0];
+	    switch (fmt) {
+	    case '0': case '1': case '2': case '3': case '4':
+	    case '5': case '6': case '7': case '8': case '9':
+		inPct = true;  // Get more digits
+		widthSet = true;
+		width = width*10 + (fmt - '0');
+		break;
+	    case '%':
+		output += '%';
+		break;
+	    case 'S': { // "C" string
+		const char* cstrp = va_arg(ap, const char*);
+		output += cstrp;
+		break;
+	    }
+	    default: {
+		// Deal with all read-and-print somethings
+		const int lbits = va_arg(ap, int);
+		QData ld = 0;
+		WDataInP lwp;
+		if (lbits <= VL_QUADSIZE) {
+		    WData qlwp[2];
+		    ld = _VL_VA_ARG_Q(ap, lbits);
+		    VL_SET_WQ(qlwp,ld);
+		    lwp = qlwp;
+		} else {
+		    lwp = va_arg(ap,WDataInP);
+		    ld = lwp[0];
+		    if (fmt == 'u' || fmt == 'd') fmt = 'x';  // Not supported, but show something
+		}
+		int lsb=lbits-1;
+		if (widthSet && width==0) while (lsb && !VL_BITISSET_W(lwp,lsb)) lsb--;
+		switch (fmt) {
+		case 'c': {
+		    IData charval = ld & 0xff;
+		    output += charval;
+		    break;
+		}
+		case 's':
+		    for (; lsb>=0; lsb--) {
+			lsb = (lsb / 8) * 8; // Next digit
+			IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xff;
+			output += (charval==0)?' ':charval;
+		    }
+		    break;
+		case 'd': { // Signed decimal
+		    int digits=sprintf(tmp,"%lld",(vlsint64_t)(VL_EXTENDS_QQ(lbits,lbits,ld)));
+		    int needmore = width-digits;
+		    if (needmore>0) output.append(needmore,' '); // Pre-pad spaces
+		    output += tmp;
+		    break;
+		}
+		case 'u': { // Unsigned decimal
+		    int digits=sprintf(tmp,"%llu",ld);
+		    int needmore = width-digits;
+		    if (needmore>0) output.append(needmore,' '); // Pre-pad spaces
+		    output += tmp;
+		    break;
+		}
+		case 'b':
+		    for (; lsb>=0; lsb--) {
+			output += ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 1) + '0';
+		    }
+		    break;
+		case 'o':
+		    for (; lsb>=0; lsb--) {
+			lsb = (lsb / 3) * 3; // Next digit
+			// Octal numbers may span more than one wide word,
+			// so we need to grab each bit separately and check for overrun
+			// Octal is rare, so we'll do it a slow simple way
+			output += ('0'
+				   + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb+0)) ? 1 : 0)
+				   + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb+1)) ? 2 : 0)
+				   + ((VL_BITISSETLIMIT_W(lwp, lbits, lsb+2)) ? 4 : 0));
+		    }
+		    break;
+		case 'x':
+		    for (; lsb>=0; lsb--) {
+			lsb = (lsb / 4) * 4; // Next digit
+			IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xf;
+			output += "0123456789abcdef"[charval];
+		    }
+		    break;
+		default:
+		    string msg = string("%%Error: Unknown _vl_vsformat code: ")+pos[0]+"\n";
+		    vl_fatal(__FILE__,__LINE__,"",msg.c_str());
+		    break;
+		} // switch
+	    }
+	    } // switch
 	}
-	*strp++ = '\0';
-	return str;
-    case 'b':
-	for (; lsb>=0; lsb--) {
-	    *strp++ = ((ld>>VL_BITBIT_Q(lsb)) & 1) + '0';
-	}
-	*strp++ = '\0';
-	return str;
-    case 'o':
-	for (; lsb>=0; lsb--) {
-	    lsb = (lsb / 3) * 3; // Next digit
-	    *strp++ = ((ld>>VL_BITBIT_Q(lsb)) & 7) + '0';
-	}
-	*strp++ = '\0';
-	return str;
-    default:
-	for (; lsb>=0; lsb--) {
-	    lsb = (lsb / 4) * 4; // Next digit
-	    IData charval = (ld>>VL_BITBIT_Q(lsb)) & 0xf;
-	    *strp++ = (charval + ((charval < 10) ? '0':('a'-10)));
-	}
-	*strp++ = '\0';
-	return str;
     }
-    *strp++ = '\0';
-    return str;
 }
 
-const char* VL_VALUE_FORMATTED_W(int obits, char fmt, bool drop0, WDataInP lwp) {
+static inline bool _vl_vsss_eof(FILE* fp, int& floc) {
-    // Convert value into %b/%o/%x/%s/%u/%d formatted string
+    return fp ? feof(fp) : (floc<0);
-    // Note uses a single buffer; presumes only one call per printf
+}
-    static VL_THREAD char str[VL_VALUE_STRING_MAX_WIDTH];
+static inline void _vl_vsss_advance(FILE* fp, int& floc) {
-    char* strp = &str[0];
+    if (fp) fgetc(fp);
-    int lsb=obits-1;
+    else floc -= 8;
-    if (drop0) while (lsb && !VL_BITISSET_W(lwp,lsb)) lsb--;
+}
-    switch (fmt) {
+static inline int  _vl_vsss_peek(FILE* fp, int& floc, WDataInP fromp) {
-    case 's':
+    // Get a character without advancing
-	for (; lsb>=0; lsb--) {
+    if (fp) {
-	    lsb = (lsb / 8) * 8; // Next digit
+	int data = fgetc(fp);
-	    IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xff;
+	if (data == EOF) return EOF;
-	    *strp++ = (charval==0)?' ':charval;
+	ungetc(data,fp);
-	}
+	return data;
-	*strp++ = '\0';
+    } else {
-	return str;
+	if (floc < 0) return EOF;
-    case 'b':
+	floc = floc & ~7;	// Align to closest character
-	for (; lsb>=0; lsb--) {
+	int data = (fromp[VL_BITWORD_I(floc)] >> VL_BITBIT_I(floc)) & 0xff;
-	    *strp++ = ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 1) + '0';
+	return data;
-	}
-	*strp++ = '\0';
-	return str;
-    case 'o':
-	for (; lsb>=0; lsb--) {
-	    lsb = (lsb / 3) * 3; // Next digit
-	    *strp++ = ((lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 7) + '0';
-	}
-	*strp++ = '\0';
-	return str;
-    default:
-	for (; lsb>=0; lsb--) {
-	    lsb = (lsb / 4) * 4; // Next digit
-	    IData charval = (lwp[VL_BITWORD_I(lsb)]>>VL_BITBIT_I(lsb)) & 0xf;
-	    *strp++ = (charval + ((charval < 10) ? '0':('a'-10)));
-	}
-	*strp++ = '\0';
-	return str;
     }
-    *strp++ = '\0';
+}
-    return str;
+static inline void _vl_vsss_skipspace(FILE* fp, int& floc, WDataInP fromp) {
+    while (1) {
+	int c = _vl_vsss_peek(fp, floc, fromp);
+	if (c==EOF || !isspace(c)) return;
+	_vl_vsss_advance(fp, floc);
+    }
+}
+static inline void _vl_vsss_read(FILE* fp, int& floc, WDataInP fromp,
+				 char* tmpp, const char* acceptp) {
+    // Read into tmp, consisting of characters from acceptp list
+    char* cp = tmpp;
+    while (1) {
+	int c = _vl_vsss_peek(fp, floc, fromp);
+	if (c==EOF || isspace(c)) break;
+	if (acceptp!=NULL // String - allow anything
+	    && NULL==strchr(acceptp, c)) break;
+	if (acceptp!=NULL) c = tolower(c); // Non-strings we'll simplify
+	*cp++ = c;
+	_vl_vsss_advance(fp, floc);
+    }
+    *cp++ = '\0';
+    //VL_PRINTF("\t_read got='%s'\n", tmpp);
+}
+static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits, IData ld) {
+    for (; nbits && lsb<obits; nbits--, lsb++, ld>>=1) {
+	VL_ASSIGNBIT_WI(0, lsb, owp, ld & 1);
+    }
+}
+
+IData _vl_vsscanf(FILE* fp,  // If a fscanf
+		  int fbits, WDataInP fromp,  // Else if a sscanf
+		  const char* formatp, va_list ap) {
+    // Read a Verilog $sscanf/$fscanf style format into the output list
+    // The format must be pre-processed (and lower cased) by Verilator
+    // Arguments are in "width, arg-value (or WDataIn* if wide)" form
+    static VL_THREAD char tmp[VL_VALUE_STRING_MAX_WIDTH];
+    int floc = fbits - 1;
+    IData got = 0;
+    bool inPct = false;
+    const char* pos = formatp;
+    for (; *pos && !_vl_vsss_eof(fp,floc); ++pos) {
+	//VL_PRINTF("_vlscan fmt='%c' floc=%d file='%c'\n", pos[0], floc, _vl_vsss_peek(fp,floc,fromp));
+	if (!inPct && pos[0]=='%') {
+	    inPct = true;
+	} else if (!inPct && isspace(pos[0])) {   // Format spaces
+	    while (isspace(pos[1])) pos++;
+	    _vl_vsss_skipspace(fp,floc,fromp);
+	} else if (!inPct) {   // Expected Format
+	    _vl_vsss_skipspace(fp,floc,fromp);
+	    int c = _vl_vsss_peek(fp,floc,fromp);
+	    if (c != pos[0]) goto done;
+	    else _vl_vsss_advance(fp,floc);
+	} else { // Format character
+	    // Skip loading spaces
+	    inPct = false;
+	    char fmt = pos[0];
+	    switch (fmt) {
+	    case '%': {
+		int c = _vl_vsss_peek(fp,floc,fromp);
+		if (c != '%') goto done;
+		else _vl_vsss_advance(fp,floc);
+		break;
+	    }
+	    default: {
+		// Deal with all read-and-scan somethings
+		// Note LSBs are preserved if there's an overflow
+		const int obits = va_arg(ap, int);
+		int lsb = 0;
+		WData qowp[2];
+		WDataOutP owp = qowp;
+		if (obits > VL_QUADSIZE) {
+		    owp = va_arg(ap,WDataOutP);
+		}
+		for (int i=0; i<VL_WORDS_I(obits); i++) owp[i] = 0;
+		switch (fmt) {
+		case 'c': {
+		    int c = _vl_vsss_peek(fp,floc,fromp);
+		    if (c==EOF) goto done;
+		    else _vl_vsss_advance(fp,floc);
+		    owp[0] = c;
+		    break;
+		}
+		case 's': {
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, NULL);
+		    if (!tmp[0]) goto done;
+		    int pos = strlen(tmp)-1;
+		    for (int i=0; i<obits && pos>=0; pos--) {
+			_vl_vsss_setbit(owp,obits,lsb, 8, tmp[pos]); lsb+=8;
+		    }
+		    break;
+		}
+		case 'd': { // Signed decimal
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, "0123456789+-xz?_");
+		    if (!tmp[0]) goto done;
+		    vlsint64_t ld;
+		    sscanf(tmp,"%lld",&ld);
+		    VL_SET_WQ(owp,ld);
+		    break;
+		}
+		case 'u': { // Unsigned decimal
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, "0123456789+-xz?_");
+		    if (!tmp[0]) goto done;
+		    QData ld;
+		    sscanf(tmp,"%llu",&ld);
+		    VL_SET_WQ(owp,ld);
+		    break;
+		}
+		case 'b': {
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, "01xz?_");
+		    if (!tmp[0]) goto done;
+		    int pos = strlen(tmp)-1;
+		    for (int i=0; i<obits && pos>=0; pos--) {
+			switch(tmp[pos]) {
+			case 'x': case 'z': case '?': //FALLTHRU
+			case '0': lsb++; break;
+			case '1': _vl_vsss_setbit(owp,obits,lsb, 1, 1); lsb++; break;
+			case '_': break;
+			}
+		    }
+		    break;
+		}
+		case 'o': {
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, "01234567xz?_");
+		    if (!tmp[0]) goto done;
+		    int pos = strlen(tmp)-1;
+		    for (int i=0; i<obits && pos>=0; pos--) {
+			switch(tmp[pos]) {
+			case 'x': case 'z': case '?': //FALLTHRU
+			case '0': lsb+=3; break;
+			case '1': _vl_vsss_setbit(owp,obits,lsb, 3, 1); lsb+=3; break;
+			case '2': _vl_vsss_setbit(owp,obits,lsb, 3, 2); lsb+=3; break;
+			case '3': _vl_vsss_setbit(owp,obits,lsb, 3, 3); lsb+=3; break;
+			case '4': _vl_vsss_setbit(owp,obits,lsb, 3, 4); lsb+=3; break;
+			case '5': _vl_vsss_setbit(owp,obits,lsb, 3, 5); lsb+=3; break;
+			case '6': _vl_vsss_setbit(owp,obits,lsb, 3, 6); lsb+=3; break;
+			case '7': _vl_vsss_setbit(owp,obits,lsb, 3, 7); lsb+=3; break;
+			case '_': break;
+			}
+		    }
+		    break;
+		}
+		case 'x': {
+		    _vl_vsss_skipspace(fp,floc,fromp);
+		    _vl_vsss_read(fp,floc,fromp, tmp, "0123456789abcdefxz?_");
+		    if (!tmp[0]) goto done;
+		    int pos = strlen(tmp)-1;
+		    for (int i=0; i<obits && pos>=0; pos--) {
+			switch(tmp[pos]) {
+			case 'x': case 'z': case '?': //FALLTHRU
+			case '0': lsb+=4; break;
+			case '1': _vl_vsss_setbit(owp,obits,lsb, 4,  1); lsb+=4; break;
+			case '2': _vl_vsss_setbit(owp,obits,lsb, 4,  2); lsb+=4; break;
+			case '3': _vl_vsss_setbit(owp,obits,lsb, 4,  3); lsb+=4; break;
+			case '4': _vl_vsss_setbit(owp,obits,lsb, 4,  4); lsb+=4; break;
+			case '5': _vl_vsss_setbit(owp,obits,lsb, 4,  5); lsb+=4; break;
+			case '6': _vl_vsss_setbit(owp,obits,lsb, 4,  6); lsb+=4; break;
+			case '7': _vl_vsss_setbit(owp,obits,lsb, 4,  7); lsb+=4; break;
+			case '8': _vl_vsss_setbit(owp,obits,lsb, 4,  8); lsb+=4; break;
+			case '9': _vl_vsss_setbit(owp,obits,lsb, 4,  9); lsb+=4; break;
+			case 'a': _vl_vsss_setbit(owp,obits,lsb, 4, 10); lsb+=4; break;
+			case 'b': _vl_vsss_setbit(owp,obits,lsb, 4, 11); lsb+=4; break;
+			case 'c': _vl_vsss_setbit(owp,obits,lsb, 4, 12); lsb+=4; break;
+			case 'd': _vl_vsss_setbit(owp,obits,lsb, 4, 13); lsb+=4; break;
+			case 'e': _vl_vsss_setbit(owp,obits,lsb, 4, 14); lsb+=4; break;
+			case 'f': _vl_vsss_setbit(owp,obits,lsb, 4, 15); lsb+=4; break;
+			case '_': break;
+			}
+		    }
+		    break;
+		}
+		default:
+		    string msg = string("%%Error: Unknown _vl_vsscanf code: ")+pos[0]+"\n";
+		    vl_fatal(__FILE__,__LINE__,"",msg.c_str());
+		    break;
+		} // switch
+
+		got++;
+		// Reload data if non-wide (if wide, we put it in the right place directly)
+		if (obits <= VL_BYTESIZE) {
+		    CData* p = va_arg(ap,CData*); *p = owp[0];
+		} else if (obits <= VL_SHORTSIZE) {
+		    SData* p = va_arg(ap,SData*); *p = owp[0];
+		} else if (obits <= VL_WORDSIZE) {
+		    IData* p = va_arg(ap,IData*); *p = owp[0];
+		} else if (obits <= VL_QUADSIZE) {
+		    QData* p = va_arg(ap,QData*); *p = VL_SET_QW(owp);
+		}
+	    }
+	    } // switch
+	}
+    }
+  done:
+    return got;
 }
 
 //===========================================================================
@@ -228,6 +504,40 @@ void _VL_VINT_TO_STRING(int obits, char* destoutp, WDataInP sourcep) {
     while (isspace(*(destp-1)) && destp>destoutp) *--destp = '\0';  // Drop trailing spaces
 }
 
+void _VL_STRING_TO_VINT(int obits, void* destp, int srclen, const char* srcp) {
+    // Convert C string to Verilog format
+    int bytes = VL_BYTES_I(obits);
+    char* op = ((char*)(destp));
+    if (srclen > bytes) srclen = bytes;  // Don't overflow destination
+    int i;
+    for (i=0; i<srclen; i++) { *op++ = srcp[srclen-1-i]; }
+    for (; i<bytes; i++) { *op++ = 0; }
+}
+
+IData VL_FGETS_IXQ(int obits, void* destp, QData fpq) {
+    FILE* fp = VL_CVT_Q_FP(fpq);
+    if (VL_UNLIKELY(!fp)) return 0;
+
+    // The string needs to be padded with 0's in unused spaces in front of
+    // any read data.  This means we can't know in what location the first
+    // character will finally live, so we need to copy.  Yuk.
+    IData bytes = VL_BYTES_I(obits);
+    char buffer[bytes];
+
+    // We don't use fgets, as we must read \0s.
+    IData got = 0;
+    char* cp = buffer;
+    while (got < bytes) {
+	int c = getc(fp);
+	if (c==EOF) break;
+	*cp++ = c;  got++;
+	if (c=='\n') break;
+    }
+
+    _VL_STRING_TO_VINT(obits, destp, got, buffer);
+    return got;
+}
+
 QData VL_FOPEN_QI(QData filename, IData mode) {
     IData fnw[2];  VL_SET_WQ(fnw, filename);
     return VL_FOPEN_WI(2, fnw, mode);
@@ -240,6 +550,67 @@ QData VL_FOPEN_WI(int fnwords, WDataInP filenamep, IData mode) {
     return VL_CVT_FP_Q(fopen(filenamez,modez));
 }
 
+void VL_WRITEF(const char* formatp, ...) {
+    va_list ap;
+    va_start(ap,formatp);
+    string output;
+    _vl_vsformat(output, formatp, ap);
+    va_end(ap);
+
+    // Users can redefine VL_PRINTF if they wish.
+    VL_PRINTF("%s", output.c_str());
+}
+
+void VL_FWRITEF(QData fpq, const char* formatp, ...) {
+    FILE* fp = VL_CVT_Q_FP(fpq);
+    if (VL_UNLIKELY(!fp)) return;
+
+    va_list ap;
+    va_start(ap,formatp);
+    string output;
+    _vl_vsformat(output, formatp, ap);
+    va_end(ap);
+
+    fputs(output.c_str(), fp);
+}
+
+IData VL_FSCANF_IX(QData fpq, const char* formatp, ...) {
+    FILE* fp = VL_CVT_Q_FP(fpq);
+    if (VL_UNLIKELY(!fp)) return 0;
+
+    va_list ap;
+    va_start(ap,formatp);
+    IData got = _vl_vsscanf(fp, 0, NULL, formatp, ap);
+    va_end(ap);
+    return got;
+}
+
+IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...) {
+    IData fnw[2];  VL_SET_WI(fnw, ld);
+
+    va_list ap;
+    va_start(ap,formatp);
+    IData got = _vl_vsscanf(NULL, lbits, fnw, formatp, ap);
+    va_end(ap);
+    return got;
+}
+IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...) {
+    IData fnw[2];  VL_SET_WQ(fnw, ld);
+
+    va_list ap;
+    va_start(ap,formatp);
+    IData got = _vl_vsscanf(NULL, lbits, fnw, formatp, ap);
+    va_end(ap);
+    return got;
+}
+IData VL_SSCANF_IWX(int lbits, WDataInP lwp, const char* formatp, ...) {
+    va_list ap;
+    va_start(ap,formatp);
+    IData got = _vl_vsscanf(NULL, lbits, lwp, formatp, ap);
+    va_end(ap);
+    return got;
+}
+
 void VL_READMEM_Q(bool hex, int width, int depth, int array_lsb, int,
 		  QData ofilename, void* memp, IData start, IData end) {
     IData fnw[2];  VL_SET_WQ(fnw, ofilename);
@@ -276,7 +647,7 @@ void VL_READMEM_W(bool hex, int width, int depth, int array_lsb, int fnwords,
 	else if (c=='\t' || c==' ' || c=='\r' || c=='\f') { if (innum) reading_addr=false; innum=false; }
 	// Skip // comments and detect /* comments
 	else if (ignore_to_cmt && lastc=='*' && c=='/') {
-	    ignore_to_cmt = false; if (innum) reading_addr=false; innum=false; 
+	    ignore_to_cmt = false; if (innum) reading_addr=false; innum=false;
 	} else if (!ignore_to_eol && !ignore_to_cmt) {
 	    if (lastc=='/' && c=='*') { ignore_to_cmt = true; }
 	    else if (lastc=='/' && c=='/') { ignore_to_eol = true; }
@@ -355,7 +726,7 @@ const char* Verilated::catName(const char* n1, const char* n2) {
     // Used by symbol table creation to make module names
     static char* strp = NULL;
     static int   len  = -1;
-    int newlen = strlen(n1)+strlen(n2)+2;    
+    int newlen = strlen(n1)+strlen(n2)+2;
     if (newlen > len) {
 	if (strp) delete [] strp;
 	strp = new char[newlen];

include/verilated.h

@@ -1,15 +1,15 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //*************************************************************************
 ///
 /// \file
@@ -19,7 +19,7 @@
 ///	all C++ files it generates.  It contains standard macros and
 ///	classes required by the Verilated code.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************
 
@@ -29,11 +29,11 @@
 
 #include "verilatedos.h"
 
-#include <assert.h>
+#include <cassert>
-#include <stdarg.h>
+#include <cstdarg>
-#include <stdio.h>
+#include <cstdio>
-#include <stdlib.h>
+#include <cstdlib>
-#include <string.h>
+#include <cstring>
 #include <iostream>
 using namespace std;
 
@@ -129,7 +129,7 @@ struct Verilated {
     // Extern Vars
     // Below two are used as bool, but having as uint32_t avoids conversion time
 private:
-    static int  	s_randReset;		///< Random reset: 0=all 0s, 1=all 1s, 2=random
+    static int		s_randReset;		///< Random reset: 0=all 0s, 1=all 1s, 2=random
     static int		s_debug;		///< See accessors... only when VL_DEBUG set
     static bool		s_calcUnusedSigs;	///< Waves file on, need all signals calculated
     static bool		s_gotFinish;		///< A $finish statement executed
@@ -152,7 +152,7 @@ public:
 #endif
     /// Internal: Create a new module name by concatenating two strings
     static const char* catName(const char* n1, const char* n2); // Returns new'ed data
-    /// Enable calculation of unused signals 
+    /// Enable calculation of unused signals
     static void calcUnusedSigs(bool flag) { s_calcUnusedSigs=flag; }
     static bool calcUnusedSigs() { return s_calcUnusedSigs; }	///< Return calcUnusedSigs value
     /// Did the simulation $finish?
@@ -165,7 +165,7 @@ public:
     /// Enable/disable assertions
     static void assertOn(bool flag) { s_assertOn=flag; }
     static bool assertOn() { return s_assertOn; }
-};    
+};
 
 //=========================================================================
 // Extern functions -- User may override -- See verilated.cpp
@@ -179,21 +179,21 @@ extern void vl_fatal  (const char* filename, int linenum, const char* hier,
 		       const char* msg);
 
 //=========================================================================
-// Extern functions -- Init time only, so slow is fine
+// Extern functions -- Slow path
 
+extern IData  VL_RANDOM_I(int obits);	///< Randomize a signal
+extern QData  VL_RANDOM_Q(int obits);	///< Randomize a signal
+extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp);	///< Randomize a signal
+
+/// Init time only, so slow is fine
 extern IData  VL_RAND_RESET_I(int obits);	///< Random reset a signal
 extern QData  VL_RAND_RESET_Q(int obits);	///< Random reset a signal
 extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp);	///< Random reset a signal
 extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp);	///< Zero reset a signal
 
-/// Return string with formated Verilog value
-extern const char* VL_VALUE_FORMATTED_W(int obits, char fmt, bool drop0, WDataInP lwp);
-extern const char* VL_VALUE_FORMATTED_Q(int obits, char fmt, bool drop0, QData ld);
-inline const char* VL_VALUE_FORMATTED_I(int obits, char fmt, bool drop0, IData ld) {
-    return VL_VALUE_FORMATTED_Q(obits,fmt,drop0,ld);
-}
-
 /// File I/O
+extern IData VL_FGETS_IXQ(int sbits, void* strgp, QData fpq);
+
 extern QData VL_FOPEN_WI(int fnwords, WDataInP ofilename, IData mode);
 extern QData VL_FOPEN_QI(QData ofilename, IData mode);
 inline QData VL_FOPEN_II(IData ofilename, IData mode) { return VL_FOPEN_QI(ofilename,mode); }
@@ -206,16 +206,27 @@ inline void VL_READMEM_I(bool hex, int width, int depth, int array_lsb, int fnwo
 			 IData ofilename,    void* memp, IData start, IData end) {
     VL_READMEM_Q(hex, width,depth,array_lsb,fnwords, ofilename,memp,start,end); }
 
+extern void VL_WRITEF(const char* formatp, ...);
+extern void VL_FWRITEF(QData fpq, const char* formatp, ...);
+
+extern IData VL_FSCANF_IX(QData fpq, const char* formatp, ...);
+extern IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...);
+extern IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...);
+extern IData VL_SSCANF_IWX(int lbits, WDataInP lwp, const char* formatp, ...);
+
 //=========================================================================
 // Base macros
 
 /// Return true if data[bit] set
-#define VL_BITISSET_I(data,bit) (data & (1UL<<VL_BITBIT_I(bit)))
+#define VL_BITISSET_I(data,bit) (data & (VL_UL(1)<<VL_BITBIT_I(bit)))
 #define VL_BITISSET_Q(data,bit) (data & (VL_ULL(1)<<VL_BITBIT_Q(bit)))
-#define VL_BITISSET_W(data,bit) (data[VL_BITWORD_I(bit)] & (1UL<<VL_BITBIT_I(bit)))
+#define VL_BITISSET_W(data,bit) (data[VL_BITWORD_I(bit)] & (VL_UL(1)<<VL_BITBIT_I(bit)))
+#define VL_BITISSETLIMIT_W(data,width,bit) (((bit)<(width)) && data[VL_BITWORD_I(bit)] & (VL_UL(1)<<VL_BITBIT_I(bit)))
 
 /// Create two 32-bit words from quadword
-#define VL_SET_WQ(decl,data)	{ decl[0]=(data); decl[1]=((data)>>VL_WORDSIZE); }
+#define VL_SET_WQ(owp,data)	{ owp[0]=(data); owp[1]=((data)>>VL_WORDSIZE); }
+#define VL_SET_WI(owp,data)	{ owp[0]=(data); owp[1]=0; }
+#define VL_SET_QW(lwp)		( ((QData)(lwp[0])) | ((QData)(lwp[1])<<((QData)(VL_WORDSIZE)) ))
 
 // Use a union to avoid cast-to-different-size warnings
 /// Return FILE* from QData
@@ -225,18 +236,18 @@ static inline QData  VL_CVT_FP_Q(FILE* fp) { union { FILE* fp; QData q; } u; u.q
 
 // Sign extend such that if MSB set, we get ffff_ffff, else 0s
 // (Requires clean input)
-#define VL_SIGN_I(nbits,lhs)      ((lhs) >> VL_BITBIT_I((nbits) - 1UL))
+#define VL_SIGN_I(nbits,lhs)      ((lhs) >> VL_BITBIT_I((nbits) - VL_UL(1)))
 #define VL_SIGN_Q(nbits,lhs)      ((lhs) >> VL_BITBIT_Q((nbits) - VL_ULL(1)))
 #define VL_SIGNONES_I(nbits,lhs)  (-(VL_SIGN_I(nbits,lhs)))
 
 // Sign bit extended up to MSB, doesn't include unsigned portion
 // Optimization bug in GCC 3.3 returns different bitmasks to later states for
-static inline IData  VL_EXTENDSIGN_I(int lbits, IData lhs) { return (-((lhs)&(1UL<<(lbits-1)))); }
+static inline IData  VL_EXTENDSIGN_I(int lbits, IData lhs) { return (-((lhs)&(VL_UL(1)<<(lbits-1)))); }
 static inline QData  VL_EXTENDSIGN_Q(int lbits, QData lhs) { return (-((lhs)&(VL_ULL(1)<<(lbits-1)))); }
 
 // Debugging prints
 static inline void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) {
-    printf("  Data: w%d: ", lbits); 
+    printf("  Data: w%d: ", lbits);
     for (int i=VL_WORDS_I(lbits)-1; i>=0; i--) { printf("%08x ",iwp[i]); }
     printf("\n");
 }
@@ -304,15 +315,15 @@ static inline WDataOutP VL_ASSIGN_W(int obits, WDataOutP owp,WDataInP lwp){
 
 // EMIT_RULE: VL_ASSIGNBIT:  rclean=clean;
 static inline void VL_ASSIGNBIT_II(int, int bit, CData& lhsr, IData rhs) {
-    lhsr = ((lhsr & ~(1UL<<VL_BITBIT_I(bit)))
+    lhsr = ((lhsr & ~(VL_UL(1)<<VL_BITBIT_I(bit)))
 	    | (rhs<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_II(int, int bit, SData& lhsr, IData rhs) {
-    lhsr = ((lhsr & ~(1UL<<VL_BITBIT_I(bit)))
+    lhsr = ((lhsr & ~(VL_UL(1)<<VL_BITBIT_I(bit)))
 	    | (rhs<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_II(int, int bit, IData& lhsr, IData rhs) {
-    lhsr = ((lhsr & ~(1UL<<VL_BITBIT_I(bit)))
+    lhsr = ((lhsr & ~(VL_UL(1)<<VL_BITBIT_I(bit)))
 	    | (rhs<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_QI(int, int bit, QData& lhsr, QData rhs) {
@@ -321,25 +332,25 @@ static inline void VL_ASSIGNBIT_QI(int, int bit, QData& lhsr, QData rhs) {
 }
 static inline void VL_ASSIGNBIT_WI(int, int bit, WDataOutP owp, IData rhs) {
     IData orig = owp[VL_BITWORD_I(bit)];
-    owp[VL_BITWORD_I(bit)] = (orig & ~(1UL<<VL_BITBIT_I(bit))
+    owp[VL_BITWORD_I(bit)] = (orig & ~(VL_UL(1)<<VL_BITBIT_I(bit))
 			    | (rhs<<VL_BITBIT_I(bit)));
 }
 // Alternative form that is an instruction faster when rhs is constant one.
 static inline void VL_ASSIGNBIT_IO(int, int bit, CData& lhsr, IData) {
-    lhsr = (lhsr | (1UL<<VL_BITBIT_I(bit)));
+    lhsr = (lhsr | (VL_UL(1)<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_IO(int, int bit, SData& lhsr, IData) {
-    lhsr = (lhsr | (1UL<<VL_BITBIT_I(bit)));
+    lhsr = (lhsr | (VL_UL(1)<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_IO(int, int bit, IData& lhsr, IData) {
-    lhsr = (lhsr | (1UL<<VL_BITBIT_I(bit)));
+    lhsr = (lhsr | (VL_UL(1)<<VL_BITBIT_I(bit)));
 }
 static inline void VL_ASSIGNBIT_QO(int, int bit, QData& lhsr, IData) {
     lhsr = (lhsr | (VL_ULL(1)<<VL_BITBIT_Q(bit)));
 }
 static inline void VL_ASSIGNBIT_WO(int, int bit, WDataOutP owp, IData) {
     IData orig = owp[VL_BITWORD_I(bit)];
-    owp[VL_BITWORD_I(bit)] = (orig |  (1UL<<VL_BITBIT_I(bit)));
+    owp[VL_BITWORD_I(bit)] = (orig |  (VL_UL(1)<<VL_BITBIT_I(bit)));
 }
 
 //===================================================================
@@ -460,43 +471,92 @@ static inline IData VL_REDOR_W(int words, WDataInP lwp) {
 }
 
 // EMIT_RULE: VL_REDXOR:  oclean=dirty; obits=1;
-static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
-    IData r = lwp[0];
-    for (int i=1; i < words; i++) r ^= lwp[i];
-    r=(r^(r>>1));
-    r=(r^(r>>2));
-    r=(r^(r>>4));
-    r=(r^(r>>8));
-    r=(r^(r>>16));
-    return r;
-}
 static inline IData VL_REDXOR_2(IData r) {
+    // Experiments show VL_REDXOR_2 is faster than __builtin_parityl
     r=(r^(r>>1));
     return r;
 }
 static inline IData VL_REDXOR_4(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_8(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_16(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_32(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_64(QData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityll(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16)); r=(r^(r>>32));
     return r;
+#endif
+}
+static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
+    IData r = lwp[0];
+    for (int i=1; i < words; i++) r ^= lwp[i];
+    return VL_REDXOR_32(r);
+}
+
+static inline IData VL_CLOG2_I(IData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    IData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_UL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_UL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_UL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_UL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_UL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_Q(QData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    QData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_ULL(32); if (chk) { n += 32; lhs = chk; }
+    chk = lhs >> VL_ULL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_ULL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_ULL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_ULL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_ULL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
+    for (int i=words-1; i>=0; i--) {
+	if (lwp[i]) return VL_CLOG2_I(lwp[i])+i*VL_WORDSIZE;
+    }
+    return 0;
 }
 
 // EMIT_RULE: VL_COUNTONES_II:  oclean = false; lhs clean
 static inline IData VL_COUNTONES_I(IData lhs) {
+    // This is faster than __builtin_popcountl
     IData r = lhs - ((lhs >> 1) & 033333333333) - ((lhs >> 2) & 011111111111);
     r = (r + (r>>3)) & 030707070707;
     r = (r + (r>>6));
@@ -829,7 +889,7 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
     return out;
 }
 
-#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) 
+#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
 
 static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
     if (lhs==0) return 0;
@@ -847,23 +907,23 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
 
 // INTERNAL: Stuff LHS bit 0++ into OUTPUT at specified offset
 // ld may be "dirty", output is clean
-static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) {
     QData insmask = (VL_MASK_Q(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) {
     int hoffset = VL_BITBIT_I(hbit);
     int loffset = VL_BITBIT_I(lbit);
     if (hoffset==VL_SIZEBITS_I && loffset==0) {
@@ -888,7 +948,7 @@ static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbi
 
 // INTERNAL: Stuff large LHS bit 0++ into OUTPUT at specified offset
 // lwp may be "dirty"
-static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) { 
+static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) {
     int hoffset = hbit & VL_SIZEBITS_I;
     int loffset = lbit & VL_SIZEBITS_I;
     int lword = VL_BITWORD_I(lbit);
@@ -934,7 +994,7 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
     }
 }
 
-static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) {
     WData lwp[2]; VL_SET_WQ(lwp,ld);
     _VL_INSERT_WW(obits,owp,lwp,hbit,lbit);
 }
@@ -1164,7 +1224,7 @@ static inline IData VL_BITSEL_IWII(int, int lbits, int, int, WDataInP lwp, IData
     int word = VL_BITWORD_I(rd);
     if ((int)rd>lbits) {
 	return ~0; // Spec says you can go outside the range of a array.  Don't coredump if so.
-	// We return all 1's as that's more likely to find bugs (?) then 0's.
+	// We return all 1's as that's more likely to find bugs (?) than 0's.
     } else {
 	return (lwp[word]>>VL_BITBIT_I(rd));
     }
@@ -1214,7 +1274,7 @@ static inline QData VL_SEL_QWII(int, int lbits, int, int, WDataInP lwp, IData ls
 static inline WDataOutP VL_SEL_WWII(int obits,int lbits,int,int,WDataOutP owp,WDataInP lwp, IData lsb, IData width) {
     int msb = lsb+width-1;
     int word_shift = VL_BITWORD_I(lsb);
-    if (msb>lbits) { // Outside bounds, 
+    if (msb>lbits) { // Outside bounds,
 	for (int i=0; i<VL_WORDS_I(obits)-1; i++) owp[i] = ~0;
 	owp[VL_WORDS_I(obits)-1] = VL_MASK_I(obits);
     } else if (VL_BITBIT_I(lsb)==0) {
@@ -1288,123 +1348,60 @@ static inline WDataOutP VL_COND_WIWW(int obits, int, int, int,
 // VL_CONST_W_#X(int obits, WDataOutP owp, IData data0, .... IData data(#-1))
 // Sets wide vector words to specified constant words, zeros upper data.
 
+// If changing the number of functions here, also change EMITCINLINES_NUM_CONSTW
+
 #define I IData
 #define _END(obits,wordsSet) \
     for(int i=(wordsSet);i<VL_WORDS_I(obits);i++) o[i] = (IData)0x0; \
     return o
 
+#define VL_HAVE_CONST_W_1X
 static inline WDataOutP VL_CONST_W_1X(int obits, WDataOutP o,
 				      I d0) {
     o[0]=d0;
     _END(obits,1);  }
+#define VL_HAVE_CONST_W_2X
 static inline WDataOutP VL_CONST_W_2X(int obits, WDataOutP o,
 				      I d1,I d0) {
     o[0]=d0;  o[1]=d1;
     _END(obits,2);  }
+#define VL_HAVE_CONST_W_3X
 static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o,
 				      I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;
     _END(obits,3);  }
-static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_4X
+static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o,
 				      I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;
     _END(obits,4);  }
-static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_5X
+static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o,
 				      I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;
     _END(obits,5);  }
-static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_6X
+static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o,
 				      I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;
     _END(obits,6);  }
-static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_7X
+static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o,
 				      I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;
     _END(obits,7);  }
-static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_8X
+static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o,
 				      I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
     _END(obits,8);  }
-static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o, 
+#define VL_HAVE_CONST_W_9X
+static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o,
 				      I d8,
 				      I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
     o[8]=d8;
     _END(obits,9);  }
-static inline WDataOutP VL_CONST_W_10X(int obits, WDataOutP o, 
-				       I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;
-    _END(obits,10);  }
-static inline WDataOutP VL_CONST_W_11X(int obits, WDataOutP o, 
-				       I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;
-    _END(obits,11);  }
-static inline WDataOutP VL_CONST_W_12X(int obits, WDataOutP o, 
-				       I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10; o[11]=d11;
-    _END(obits,12);  }
-static inline WDataOutP VL_CONST_W_16X(int obits, WDataOutP o, 
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    _END(obits,16);  }
-static inline WDataOutP VL_CONST_W_17X(int obits, WDataOutP o, 
-				       I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;
-    _END(obits,17);  }
-static inline WDataOutP VL_CONST_W_18X(int obits, WDataOutP o, 
-				       I d17,I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;  o[17]=d17;
-    _END(obits,18);  }
-static inline WDataOutP VL_CONST_W_19X(int obits, WDataOutP o, 
-				       I d18,I d17,I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;  o[17]=d17;  o[18]=d18;
-    _END(obits,19);  }
-static inline WDataOutP VL_CONST_W_20X(int obits, WDataOutP o, 
-				       I d19,I d18,I d17,I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;  o[17]=d17;  o[18]=d18;  o[19]=d19;
-    _END(obits,20);  }
-static inline WDataOutP VL_CONST_W_24X(int obits, WDataOutP o, 
-				       I d23,I d22,I d21,I d20,I d19,I d18,I d17,I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;  o[17]=d17;  o[18]=d18;  o[19]=d19;  o[20]=d20;  o[21]=d21;  o[22]=d22;  o[23]=d23;
-    _END(obits,24);  }
-static inline WDataOutP VL_CONST_W_28X(int obits, WDataOutP o, 
-				       I d27,I d26,I d25,I d24,
-				       I d23,I d22,I d21,I d20,I d19,I d18,I d17,I d16,
-				       I d15,I d14,I d13,I d12,I d11,I d10,I d9,I d8,
-				       I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
-    o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
-    o[8]=d8;  o[9]=d9;  o[10]=d10;  o[11]=d11;  o[12]=d12;  o[13]=d13;  o[14]=d14;  o[15]=d15;
-    o[16]=d16;  o[17]=d17;  o[18]=d18;  o[19]=d19;  o[20]=d20;  o[21]=d21;  o[22]=d22;  o[23]=d23;
-    o[24]=d24;  o[25]=d25;  o[26]=d26;  o[27]=d27;
-    _END(obits,28);  }
 
 #undef _END
 #undef I

include/verilated.mk.in

@@ -1,10 +1,10 @@
-# $Id$ -*- Makefile -*-
+# -*- Makefile -*-
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
+# Lesser General Public License or the Perl Artistic License.
 ######################################################################
 
 PERL = @PERL@
@@ -44,7 +44,7 @@ CPPFLAGS += -I. $(VK_CPPFLAGS_ALWAYS) $(VK_CPPFLAGS_WALL)
 VPATH += ..
 VPATH += $(VERILATOR_ROOT)/include
 
-#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE 
+#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE
 #OPT = -ggdb -DPRINTINITSTR
 CPPFLAGS += $(OPT)
 
@@ -59,11 +59,11 @@ LDFLAGS  += $(USER_LDFLAGS)
 # See the benchmarking section of bin/verilator.
 # Support class optimizations.  This includes the tracing and symbol table.
 # SystemC takes minutes to optimize, thus it is off by default.
-#OPT_SLOW = 
+#OPT_SLOW =
 # Fast path optimizations.  Most time is spent in these classes.
 #OPT_FAST = -O2 -fstrict-aliasing
 #OPT_FAST = -O
-#OPT_FAST = 
+#OPT_FAST =
 
 #######################################################################
 ##### Aggregates
@@ -77,7 +77,6 @@ VM_SUPPORT += $(VM_SUPPORT_FAST) $(VM_SUPPORT_SLOW)
 ifeq ($(VM_SP_OR_SC),1)
   CPPFLAGS += $(SYSTEMC_CXX_FLAGS) -I$(SYSTEMC)/include
   LDFLAGS  += $(SYSTEMC_CXX_FLAGS) -L$(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)
-  LIBS     += -lm -lstdc++
   SC_LIBS   = -lsystemc
  ifneq ($(wildcard $(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)/*numeric_bit*),)
   # Systemc 1.2.1beta
@@ -91,6 +90,7 @@ endif
 ifeq ($(VM_SP),1)
   CPPFLAGS += -I$(SYSTEMPERL)/src -DSYSTEMPERL
   VPATH    +=   $(SYSTEMPERL)/src
+  LIBS   += -lm -lstdc++
 
   VK_CLASSES_SP = $(addsuffix .sp, $(VM_CLASSES))
 
@@ -103,6 +103,17 @@ else
   preproc:
 endif
 
+#######################################################################
+##### SystemC w/o SystemPerl builds
+
+ifeq ($(VM_SC),1)
+  LIBS   += -lm -lstdc++
+ ifeq ($(VM_TRACE),1)
+  CPPFLAGS += -I$(SYSTEMPERL)/src
+  VPATH    +=   $(SYSTEMPERL)/src
+ endif
+endif
+
 #######################################################################
 ##### C/H builds
 

include/verilated.v

@@ -1,19 +1,19 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // This is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //=========================================================================
 //
 // DESCRIPTION: Verilator: Include in verilog files to hide verilator defines
@@ -25,7 +25,7 @@
  `ifdef verilator `else
   `define coverage_block_off
  `endif
- 
+
  // Hide file descriptor difference
  `ifdef verilator
   `define verilator_file_descriptor reg [63:0]

include/verilatedos.h

@@ -1,15 +1,15 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //*************************************************************************
 ///
 /// \file
@@ -21,7 +21,7 @@
 ///	config_build.h.in, code needed by Verilated code only goes into
 ///	verilated.h, and code needed by both goes here (verilatedos.h).
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************
 
@@ -46,8 +46,8 @@
 # define VL_ATTR_ALIGNED(alignment)	///< Align structure to specified byte alignment
 # define VL_ATTR_NORETURN		///< Function does not ever return
 # define VL_ATTR_UNUSED			///< Function that may be never used
-# define VL_LIKELY(x)	(!!(x))		///< Boolean expression more often true then false
+# define VL_LIKELY(x)	(!!(x))		///< Boolean expression more often true than false
-# define VL_UNLIKELY(x)	(!!(x))		///< Boolean expression more often false then true
+# define VL_UNLIKELY(x)	(!!(x))		///< Boolean expression more often false than true
 # define VL_PREFETCH_RD(p)		///< Prefetch data with read intent
 # define VL_PREFETCH_RW(p)		///< Prefetch data with read/write intent
 #endif
@@ -68,6 +68,9 @@
 # define VL_ULL(c) (c##ULL)	///< Add appropriate suffix to 64-bit constant
 #endif
 
+// This is not necessarily the same as #UL, depending on what the IData typedef is.
+#define VL_UL(c) ((IData)(c##UL))	///< Add appropriate suffix to 32-bit constant
+
 //=========================================================================
 // Basic integer types
 
@@ -81,7 +84,7 @@ typedef unsigned char           vluint8_t;	///< 8-bit unsigned type
 typedef unsigned short int      vluint16_t;	///< 16-bit unsigned type
 typedef long  			vlsint32_t;	///< 32-bit signed type
 typedef unsigned long           vluint32_t;	///< 32-bit unsigned type
-typedef long long      		vlsint64_t;	///< 64-bit signed type
+typedef long long		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long      vluint64_t;	///< 64-bit unsigned type
 #elif defined(_WIN32) && !defined(__MINGW32__)
 typedef unsigned char           uint8_t;	///< 8-bit unsigned type (backward compatibility)
@@ -89,28 +92,32 @@ typedef unsigned short int      uint16_t;	///< 16-bit unsigned type (backward co
 typedef unsigned long           uint32_t;	///< 32-bit unsigned type (backward compatibility)
 typedef unsigned char           vluint8_t;	///< 8-bit unsigned type
 typedef unsigned short int      vluint16_t;	///< 16-bit unsigned type
-typedef int  			vlsint32_t;	///< 32-bit signed type
+typedef int			vlsint32_t;	///< 32-bit signed type
 typedef unsigned int            vluint32_t;	///< 32-bit unsigned type
-typedef __int64      		vlsint64_t;	///< 64-bit signed type
+typedef __int64			vlsint64_t;	///< 64-bit signed type
 typedef unsigned __int64        vluint64_t;	///< 64-bit unsigned type
 #else // Linux or compliant Unix flavors, -m64
 # include <stdint.h>	// Linux and most flavors
 # include <inttypes.h>	// Solaris
 typedef uint8_t			vluint8_t;	///< 32-bit unsigned type
 typedef uint16_t		vluint16_t;	///< 32-bit unsigned type
-typedef int  			vlsint32_t;	///< 32-bit signed type
+typedef int			vlsint32_t;	///< 32-bit signed type
 typedef uint32_t		vluint32_t;	///< 32-bit signed type
-typedef long long      		vlsint64_t;	///< 64-bit signed type
+typedef long long		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long	vluint64_t;	///< 64-bit unsigned type
 #endif
 
 //=========================================================================
 // Integer size macros
 
+#define VL_BYTESIZE 8			///< Bits in a byte
+#define VL_SHORTSIZE 16			///< Bits in a short
 #define VL_WORDSIZE 32			///< Bits in a word
 #define VL_QUADSIZE 64			///< Bits in a quadword
 #define VL_WORDSIZE_LOG2 5		///< log2(VL_WORDSIZE)
 
+/// Bytes this number of bits needs (1 bit=1 byte)
+#define VL_BYTES_I(nbits) (((nbits)+(VL_BYTESIZE-1))/VL_BYTESIZE)
 /// Words this number of bits needs (1 bit=1 word)
 #define VL_WORDS_I(nbits) (((nbits)+(VL_WORDSIZE-1))/VL_WORDSIZE)
 

install-sh

@@ -115,7 +115,7 @@ fi
 if [ x"$dir_arg" != x ]; then
 	dst=$src
 	src=""
-	
+
 	if [ -d $dst ]; then
 		instcmd=:
 	else

mkinstalldirs

@@ -4,8 +4,6 @@
 # Created: 1993-05-16
 # Public domain
 
-# $Id:$
-
 errstatus=0
 
 for file

nodist/bisonreader

@@ -0,0 +1,66 @@
+#!/usr/bin/perl -w
+######################################################################
+#
+# Copyright 2007-2008 by Wilson Snyder.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of either the GNU General Public License or the
+# Perl Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the Perl Artistic License
+# along with this module; see the file COPYING.  If not, see
+# www.cpan.org
+#
+######################################################################
+
+# DESCRIPTION: Debugging of bison output
+
+use strict;
+
+my $Debug;
+
+my %declared;
+my %used;
+
+my $body = 0;
+my $rule = "";
+my $lineno = 0;
+foreach my $line (<STDIN>) {
+    $lineno++;
+    chomp $line;
+    $line =~ s!//.*$!!g;
+    $line =~ s!\s+! !g;
+    next if $line eq '';
+    if ($line =~ m!^\%\%!) {
+	$body++;
+    } elsif ($body == 1) {
+	$rule .= $line;
+	if ($line =~ m!^\s*;\s*$!) {
+	    #print "Rule: $rule\n";
+	    ($rule =~ /^([a-zA-Z0-9_]+):(.*)$/) or die "%Error: No rule name: $1\n";
+	    my $rulename = $1; my $preaction = $2;
+	    $declared{$rulename} = $lineno;
+	    $preaction =~ s/\{[^\}]*\}/ /g;
+	    #print "RULEN $rulename PA $preaction\n" if $Debug;
+	    $rule = '';
+	    foreach my $ref (split /\s+/, $preaction) {
+		next if $ref !~ /^[a-zA-Z]/;
+		next if $ref eq $rulename;
+		if (!$used{$ref} && $declared{$ref}) {
+		    print "   %Warning: $lineno: $ref used by $rulename after declaration\n";
+		}
+		$used{$ref} = $lineno;
+		print "  ref $ref\n" if $Debug;
+	    }
+	}
+    }
+}
+
+# Local Variables:
+# compile-command: "./bisonreader < verilog.y"
+# End:

nodist/dot_importer

@@ -1,8 +1,7 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
-# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
 # program is free software; you can redistribute it and/or modify it under
 # the terms of either the GNU Lesser General Public License or the Perl
 # Artistic License.
@@ -50,7 +49,6 @@ cwrite ("graph_export.cpp");
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -120,7 +118,7 @@ sub cwrite {
     foreach my $edge (@Edges) {
 	$fh->printf("    new V3GraphEdge(gp, %s, %s, %s, %s);\n",
 		    $edge->{from}, $edge->{to},
-		    $edge->{weight}, $edge->{cutable}?"true":"false");	       
+		    $edge->{weight}, $edge->{cutable}?"true":"false");
     }
     $fh->print("}\n");
 }
@@ -156,7 +154,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License or the Perl Artistic License.
 

nodist/dot_pruner

@@ -1,8 +1,7 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
-# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
 # program is free software; you can redistribute it and/or modify it under
 # the terms of either the GNU Lesser General Public License or the Perl
 # Artistic License.
@@ -55,7 +54,6 @@ dotwrite();
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -175,7 +173,7 @@ __END__
 
 =head1 NAME
 
-dot_pruner - 
+dot_pruner -
 
 =head1 SYNOPSIS
 
@@ -197,7 +195,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License or the Perl Artistic License.
 

nodist/invoke_ncverilog

@@ -1,8 +1,7 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
-# Copyright 2007-2007 by Wilson Snyder <[email protected]>.  This
+# Copyright 2007-2008 by Wilson Snyder <[email protected]>.  This
 # program is free software; you can redistribute it and/or modify it under
 # the terms of either the GNU Lesser General Public License or the Perl
 # Artistic License.
@@ -52,7 +51,7 @@ invoke_ncverilog - Invoke tool under "modules" command
 
 =head1 DISTRIBUTION
 
-Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+Copyright 2007-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License or the Perl Artistic License.
 

nodist/leakchecking.txt

@@ -0,0 +1,4 @@
+export GLIBCPP_FORCE_NEW=1
+compile with -DVL_LEAK_CHECKS
+valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc -f /home/wsnyder/src/verilator/v4/verilator/test_c/../test_v/input.vc top.v --no-skip-identical 2>&1 | tee ~/d/aa
+valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc /home/wsnyder/src/verilator/v4/verilator/test_regress/t/t_case_huge.v --no-skip-identical -I/home/wsnyder/src/verilator/v4/verilator/test_regress/t 2>&1 | tee ~/d/aa

nodist/vtree_importer

@@ -1,8 +1,7 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
-# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
 # program is free software; you can redistribute it and/or modify it under
 # the terms of either the GNU Lesser General Public License or the Perl
 # Artistic License.
@@ -52,7 +51,6 @@ print '(query-replace-regexp "(\\([0-9a-z_]+\\))" "\\1" nil nil nil)',"\n";
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -292,7 +290,7 @@ sub p_var {
     }
     p "\t";
     {
-	local $Avoid_Hex=1; 
+	local $Avoid_Hex=1;
 	t1;
     }
     p "\t";
@@ -322,7 +320,7 @@ __END__
 
 =head1 NAME
 
-vtree_importer - 
+vtree_importer -
 
 =head1 SYNOPSIS
 
@@ -344,7 +342,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License or the Perl Artistic License.
 

readme.texi

@@ -1,6 +1,5 @@
 \input texinfo @c -*-texinfo-*-
 @c %**start of header
-$c $Id$
 @setfilename readme.info
 @settitle Verilator Installation
 @c %**end of header
@@ -15,19 +14,19 @@ $c $Id$
 This is the Verilator Package.
 
 @menu
-* Copyright::                   
+* Copyright::
-* Description::                 
+* Description::
-* Obtaining Distribution::      
+* Obtaining Distribution::
-* Directory Structure::         
+* Directory Structure::
-* Supported Systems::           
+* Supported Systems::
-* Installation::                
+* Installation::
-* Limitations::                 
+* Limitations::
 @end menu
 
 @node Copyright, Description, Top, Top
 @section Copyright
 
-This package is Copyright 2003-2007 by Wilson Snyder @email{wsnyder@@wsnyder.org}.
+This package is Copyright 2003-2008 by Wilson Snyder @email{wsnyder@@wsnyder.org}.
 
 You may distribute under the terms of either the GNU General Public License
 or the Artistic License, as specified in the Perl README file.
@@ -45,7 +44,7 @@ Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
 reads the specified Verilog code, lints it, and optionally adds coverage
 code.  For C++ format, it outputs .cpp and .h files.  For SystemC format,
 it outputs .sp files for the SystemPerl preprocessor available at
-http://veripool.com.
+http://www.veripool.org.
 
 The resulting files are then compiled with C++.  The user writes a little
 C++ wrapper file, which instantiates the top level module.  This is
@@ -56,11 +55,11 @@ The resulting executable will perform the actual simulation.
 @node Obtaining Distribution, Directory Structure, Description, Top
 @section Obtaining Distribution
 
-The latest version is available at 
+The latest version is available at
-@uref{http://veripool.com/verilator.htm}
+@uref{http://www.veripool.org/verilator}
 
 Download the latest package from that site, and decompress.
-@samp{gunzip verilator_version.tar.gz ; tar xvf verilator_version.tar}
+@samp{tar xvzf verilator_version.tgz}
 
 @node Directory Structure, Supported Systems, Obtaining Distribution, Top
 @section Directory Structure
@@ -126,6 +125,12 @@ do a @code{make sc_patch}.
 @item
 Type @samp{./configure} to configure Verilator for your system.
 
+If you are configuring Verilator to be part of a RPM or other
+distribution package system, you may want to use the --enable-defenv
+configure flag.  This will take the current value of VERILATOR_ROOT,
+SYSTEMC, SYSTEMC_ARCH, and SYSTEMPERL and build them as defaults into
+the executable.
+
 @item
 Type @samp{make} to compile Verilator.
 

src/Makefile.in

@@ -1,13 +1,13 @@
-# $Id$ */
+# -*- Makefile -*-
 #*****************************************************************************
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
-# Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 #
@@ -40,12 +40,16 @@ export OBJCACHE_HOSTS := $(shell rschedule --no-allow-reserved --similar hostnam
 endif
 
 ifeq ($(OBJCACHE_HOSTS),)
-export OBJCACHE := 
+export OBJCACHE :=
 else
 export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)")
 export OBJCACHE := @objcache --read --write
 endif
 
+UNDER_GIT = $(wildcard ../.git)
+
+#*********************************************************************
+
 obj_opt:
 	mkdir $@
 obj_dbg:
@@ -71,10 +75,10 @@ dbg: ../verilator_bin_dbg
 
 prefiles::
 
-ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
+ifneq ($(UNDER_GIT),)	# If local git tree... Else don't burden users
 prefiles:: config_rev.h
 # This output goes into srcdir, as we need to distribute it as part of the kit.
-config_rev.h:	config_rev.pl .svn/entries
+config_rev.h:	config_rev.pl ../.git/index
 	$(PERL) config_rev.pl . >$@
 endif
 

src/Makefile_obj.in

@@ -1,13 +1,13 @@
-# $Id$ -*- Makefile -*-
+# -*- Makefile -*-
 #*****************************************************************************
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
-# Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 #
@@ -23,11 +23,28 @@
 srcdir = ..
 incdir = ../../include
 
-PERL = @PERL@
+# Programs
 CC = @CC@
 CXX = @CXX@
 LINK = @CXX@
+LEX = @LEX@
+LFLAGS = -d
+PERL = @PERL@
+YACC = @YACC@
+YFLAGS = -y -d -v
 
+prefix = @prefix@
+
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
+# Directory in which to install package specific files
+# Generally ${prefix}/share/verilator
+pkgdatadir = @pkgdatadir@
+
+# Compile options
+CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
+CPPFLAGSNOWALL += @CPPFLAGS@
 LDFLAGS += @LDFLAGS@
 
 #### End of system configuration section. ####
@@ -48,17 +65,12 @@ COPT = -ggdb -DVL_DEBUG
 endif
 #################
 
-LEX = @LEX@
-LFLAGS = -d
-YACC = @YACC@
-YFLAGS = -y -d -v
-
 #LIBS += -ldl
 #CCMALLOC = /usr/local/lib/ccmalloc-gcc.o -lccmalloc -ldl
 
 LIBS = -lm -lfl
 
-CPPFLAGSNOWALL = -MMD
+CPPFLAGSNOWALL += -MMD
 CPPFLAGSNOWALL += -I. -I$(srcdir) -I$(incdir)
 CPPFLAGSNOWALL += -DYYDEBUG 	# Required to get nice error messages
 #CPPFLAGSNOWALL += -DVL_LEAK_CHECKS 	# If running valgrind or other hunting tool
@@ -70,6 +82,19 @@ CPPFLAGS += -W -Wall -Wno-unused-parameter -Wno-char-subscripts -Werror
 #CPPFLAGS += -pedantic-errors
 endif
 
+# Allow RPM builds to specify hardcoded data directories
+# To do this:
+ifeq ($(CFG_WITH_DEFENV),yes)
+ CPPFLAGS += -DDEFENV_SYSTEMC=\"$(SYSTEMC)\"
+ CPPFLAGS += -DDEFENV_SYSTEMC_ARCH=\"$(SYSTEMC_ARCH)\"
+ CPPFLAGS += -DDEFENV_SYSTEMPERL=\"$(SYSTEMPERL)\"
+ ifeq ($(VERILATOR_ROOT),)	# Use what we're given, or intuit
+  CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(pkgdatadir)\"
+ else
+  CPPFLAGS += -DDEFENV_VERILATOR_ROOT=\"$(VERILATOR_ROOT)\"
+ endif
+endif
+
 HEADERS = $(wildcard V*.h v*.h)
 
 ASTGEN = $(srcdir)/astgen
@@ -121,6 +146,7 @@ RAW_OBJS = \
 	V3DepthBlock.o \
 	V3Descope.o \
 	V3EmitC.o \
+	V3EmitCInlines.o \
 	V3EmitCSyms.o \
 	V3EmitMk.o \
 	V3EmitV.o \
@@ -220,14 +246,19 @@ V3PreProc.o:	V3PreProc.cpp V3PreLex.yy.cpp
 #### Generated files
 
 # Target rule called before parallel build to make generated files
-serial:: V3Ast__gen_classes.h
+serial:: V3Ast__gen_classes.h y.tab.c
 
 V3Ast__gen_classes.h : $(ASTGEN) V3Ast.h V3AstNodes.h
 	$(PERL) $(ASTGEN) -I$(srcdir)  --classes
 
-y.tab.c y.tab.h:	verilog.y $(HEADERS)
+y.tab.h: y.tab.c
+
+# Have only one output file in this rule to prevent parallel make issues
+y.tab.c: verilog.y $(HEADERS)
 	@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
 	${YACC} ${YFLAGS} $<
+	mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c
+	mv y.tab.h y_pregen.tab.h && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.h > y.tab.h
 
 V3Lexer_pregen.yy.cpp:	verilog.l y.tab.h $(HEADERS)
 	${LEX} ${LFLAGS} -o$@ $<

src/V3Active.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Active's Transformations:
-//		
+//
 // Note this can be called multiple times.
 //   Create a IACTIVE(initial), SACTIVE(combo)
 //	ALWAYS: Remove any-edges from sense list
@@ -33,8 +32,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 #include <algorithm>

src/V3Active.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3ActiveTop.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Active's Transformations:
-//		
+//
 // Note this can be called multiple times.
 //   Across all ACTIVES
 //	SenTrees are now under each ACTIVE statement, we want them global:
@@ -30,8 +29,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <vector>

src/V3ActiveTop.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Assert.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2005-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2005-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 #include <iomanip>
@@ -63,6 +62,9 @@ private:
 	AstNode* timesp = nodep->exprsp(); if (timesp) timesp->unlinkFrBack();
 	timesp = timesp->addNext(new AstTime(nodep->fileline()));
 	nodep->exprsp(timesp);
+	if (!nodep->scopeNamep() && nodep->name().find("%m") != string::npos) {
+	    nodep->scopeNamep(new AstScopeName(nodep->fileline()));
+	}
     }
 
     AstNode* newIfAssertOn(AstNode* nodep) {
@@ -103,7 +105,7 @@ private:
 	sentreep->unlinkFrBack();
 	//
 	AstNode* bodysp = NULL;
-	bool selfDestruct = false;	
+	bool selfDestruct = false;
 	if (AstPslCover* snodep = nodep->castPslCover()) {
 	    if (!v3Global.opt.coverageUser()) {
 		selfDestruct = true;

src/V3Assert.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2005-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2005-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3AssertPre.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2005-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2005-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -24,8 +23,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 #include <iomanip>

src/V3AssertPre.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion pre-expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2005-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2005-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Ast.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,8 +18,8 @@
 //
 //*************************************************************************
 
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <fstream>
 #include <iomanip>
 #include <memory>
@@ -83,6 +82,20 @@ void AstNode::init() {
     m_user5Cnt = 0;
 }
 
+string AstNode::encodeName(const string& namein) {
+    string name2 = namein;
+    string out;
+    for (string::iterator pos = name2.begin(); pos != name2.end(); pos++) {
+	if (pos[0]=='_' && pos[1]=='_') {
+	    out += "__ULUL_";
+	    pos++;
+	} else {
+	    out += pos[0];
+	}
+    }
+    return out;
+}
+
 string AstNode::shortName() const {
     string pretty = name();
     string::size_type pos;
@@ -114,6 +127,9 @@ string AstNode::prettyName(const string& namein) {
     while ((pos=pretty.find("__PVT__")) != string::npos) {
 	pretty.replace(pos, 7, "");
     }
+    while ((pos=pretty.find("__ULUL_")) != string::npos) {
+	pretty.replace(pos, 7, "");
+    }
     return AstNode::dedotName(pretty);
 }
 
@@ -134,6 +150,7 @@ inline void AstNode::debugTreeChange(const char* prefix, int lineno, bool next)
     // Called on all major tree changers.
     // Only for use for those really nasty bugs relating to internals
     // Note this may be null.
+    //if (debug()) cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<": "<<(void*)this<<endl;
     //if (debug()) {
     //	cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<endl;
     //	v3Global.rootp()->dumpTree(cout,"-treeChange: ");
@@ -237,8 +254,8 @@ void AstNode::addNextHere(AstNode* newp) {
 void AstNode::setOp1p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp1p\n");
     UDEBUGONLY(if (m_op1p) this->v3fatalSrc("Adding to non-empty, non-list op1"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1");); 
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1"););
     this->debugTreeChange("-setOp1pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp1pNew: ", __LINE__, true);
     m_op1p = newp;
@@ -250,8 +267,8 @@ void AstNode::setOp1p(AstNode* newp) {
 void AstNode::setOp2p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp2p\n");
     UDEBUGONLY(if (m_op2p) this->v3fatalSrc("Adding to non-empty, non-list op2"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2");); 
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2"););
     this->debugTreeChange("-setOp2pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp2pNew: ", __LINE__, true);
     m_op2p = newp;
@@ -263,8 +280,8 @@ void AstNode::setOp2p(AstNode* newp) {
 void AstNode::setOp3p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp3p\n");
     UDEBUGONLY(if (m_op3p) this->v3fatalSrc("Adding to non-empty, non-list op3"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3");); 
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3"););
     this->debugTreeChange("-setOp3pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp3pNew: ", __LINE__, true);
     m_op3p = newp;
@@ -276,8 +293,8 @@ void AstNode::setOp3p(AstNode* newp) {
 void AstNode::setOp4p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp4p\n");
     UDEBUGONLY(if (m_op4p) this->v3fatalSrc("Adding to non-empty, non-list op4"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4");); 
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4"););
     this->debugTreeChange("-setOp4pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp4pNew: ", __LINE__, true);
     m_op4p = newp;
@@ -458,7 +475,7 @@ void AstNode::relink(AstNRelinker* linkerp) {
     if (linkerp->m_iterpp) {
 	// If we're iterating over a next() link, we need to follow links off the
 	// NEW node.  Thus we pass iteration information via a pointer in the node.
-	// This adds a unfortunate 4 bytes to every AstNode, but is faster then passing
+	// This adds a unfortunate 4 bytes to every AstNode, but is faster than passing
 	// across every function.
 	// If anyone has a cleaner way, I'd be grateful.
 	*(linkerp->m_iterpp) = newp;
@@ -586,11 +603,29 @@ void AstNode::deleteTree() {
     // unlinkFromBack or unlinkFromBackWithNext as appropriate before calling this.
     if (!this) return;
     UASSERT(m_backp==NULL,"Delete called on node with backlink still set\n");
-    this->debugTreeChange("-delete: ", __LINE__, true);
+    this->debugTreeChange("-delTree:  ", __LINE__, true);
     // MUST be depth first!
     deleteTreeIter();
 }
 
+//======================================================================
+// Memory checks
+
+#ifdef VL_LEAK_CHECKS
+void* AstNode::operator new(size_t size) {
+    AstNode* objp = static_cast<AstNode*>(::operator new(size));
+    V3Broken::addNewed(objp);
+    return objp;
+}
+
+void AstNode::operator delete(void* objp, size_t size) {
+    if (!objp) return;
+    AstNode* nodep = static_cast<AstNode*>(objp);
+    V3Broken::deleted(nodep);
+    ::operator delete(objp);
+}
+#endif
+
 //======================================================================
 // Iterators
 
@@ -608,7 +643,7 @@ void AstNode::iterateListBackwards(AstNVisitor& v, AstNUser* vup) {
     while (nodep->m_nextp) nodep=nodep->m_nextp;
     while (nodep) {
 	// Edits not supported: nodep->m_iterpp = &nodep;
-  	nodep->accept(v, vup);
+	nodep->accept(v, vup);
 	if (nodep->backp()->m_nextp == nodep) nodep=nodep->backp();
 	else nodep = NULL;  // else: backp points up the tree.
     }
@@ -629,7 +664,7 @@ void AstNode::iterateAndNext(AstNVisitor& v, AstNUser* vup) {
     for (AstNode* nodep=this; nodep;) {
 	AstNode* niterp = nodep;
 	niterp->m_iterpp = &niterp;
-  	niterp->accept(v, vup);
+	niterp->accept(v, vup);
 	// accept may do a replaceNode and change niterp on us...
 	if (!niterp) return;
 	niterp->m_iterpp = NULL;
@@ -646,7 +681,7 @@ void AstNode::iterateAndNextIgnoreEdit(AstNVisitor& v, AstNUser* vup) {
     if (!this) return;
     for (AstNode* nodep=this; nodep; ) {
 	AstNode* nnextp = nodep->m_nextp;
-  	nodep->accept(v, vup);
+	nodep->accept(v, vup);
 	nodep = nnextp;
     }
 }

src/V3Ast.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -197,7 +197,8 @@ public:
 	TRIWIRE,
 	BLOCKTEMP,
 	MODULETEMP,
-	STMTTEMP
+	STMTTEMP,
+	XTEMP
     };
     enum en m_e;
     inline AstVarType () {};
@@ -209,7 +210,7 @@ public:
 	    "?","GPARAM","LPARAM","GENVAR",
 	    "INTEGER","INPUT","OUTPUT","INOUT",
 	    "SUPPLY0","SUPPLY1","WIRE","IMPLICIT","REG","TRIWIRE",
-	    "BLOCKTEMP","MODULETEMP","STMTTEMP"};
+	    "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"};
 	return names[m_e];};
   };
   inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); }
@@ -250,6 +251,25 @@ public:
 
 //######################################################################
 
+class AstCaseType {
+public:
+    enum en {
+	CASE,
+	CASEX,
+	CASEZ
+    };
+    enum en m_e;
+    inline AstCaseType () {};
+    inline AstCaseType (en _e) : m_e(_e) {};
+    explicit inline AstCaseType (int _e) : m_e(static_cast<en>(_e)) {};
+    operator en () const { return m_e; };
+  };
+  inline bool operator== (AstCaseType lhs, AstCaseType rhs) { return (lhs.m_e == rhs.m_e); }
+  inline bool operator== (AstCaseType lhs, AstCaseType::en rhs) { return (lhs.m_e == rhs); }
+  inline bool operator== (AstCaseType::en lhs, AstCaseType rhs) { return (lhs == rhs.m_e); }
+
+//######################################################################
+
 class AstDisplayType {
 public:
     enum en {
@@ -538,6 +558,10 @@ public:
 
     // CONSTRUCTORS
     virtual ~AstNode();
+#ifdef VL_LEAK_CHECKS
+    static void* operator new(size_t size);
+    static void operator delete(void* obj, size_t size);
+#endif
 
     // CONSTANT ACCESSORS
     static int	instrCountBranch() { return 4; }	///< Instruction cycles to branch
@@ -554,6 +578,7 @@ public:
     string 	shortName() const;	// Name with __PVT__ removed for concatenating scopes
     static string dedotName(const string& namein);	// Name with dots removed
     static string prettyName(const string& namein);	// Name for printing out to the user
+    static string encodeName(const string& namein);	// Encode user name into internal C representation
     string	prettyName() const { return prettyName(name()); }
     FileLine*	fileline() const { return m_fileline; }
     int		width() const { return m_width; }
@@ -646,7 +671,6 @@ public:
     virtual bool same(AstNode* otherp) const { return true; }
     virtual bool maybePointedTo() const { return false; }  // Another AstNode* may have a pointer into this node, other then normal front/back/etc.
     virtual bool broken() const { return false; }
-    virtual bool emitWordForm() { return false; }
 
     // INVOKERS
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) = 0;
@@ -677,7 +701,7 @@ struct AstNodeMath : public AstNode {
     virtual ~AstNodeMath() {}
     // METHODS
     virtual string emitVerilog() = 0;  /// Format string for verilog writing; see V3EmitV
-    virtual string emitOperator() = 0;
+    virtual string emitC() = 0;
     virtual string emitSimpleOperator() { return ""; }
     virtual bool cleanOut() = 0; // True if output has extra upper bits zero
 };
@@ -779,7 +803,7 @@ struct AstNodeCond : public AstNodeTriop {
     AstNode*	expr1p() 	const { return op2p()->castNode(); }	// op2 = If true...
     AstNode*	expr2p() 	const { return op3p()->castNode(); }	// op3 = If false...
     virtual string emitVerilog() { return "%k(%l %k? %r %k: %t)"; }
-    virtual string emitOperator() { return "VL_COND"; }
+    virtual string emitC() { return "VL_COND_%nq%lq%rq%tq(%nw,%lw,%rw,%tw, %P, %li, %ri, %ti)"; }
     virtual bool cleanOut() { return false; } // clean if e1 & e2 clean
     virtual bool cleanLhs() { return true; }
     virtual bool cleanRhs() { return false; } virtual bool cleanThs() { return false; } // Propagates up
@@ -999,12 +1023,12 @@ private:
     AstNodeFTask*	m_taskp;	// [AfterLink] Pointer to task referenced
     string		m_name;		// Name of variable
     string		m_dotted;	// Dotted part of scope to task or ""
-    string		m_inlinedDots;	// Dotted hiearchy flattened out
+    string		m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
 	:AstNode(fl)
 	, m_taskp(NULL) {
-	setOp1p(namep);	addNOp2p(pinsp); 
+	setOp1p(namep);	addNOp2p(pinsp);
     }
     virtual ~AstNodeFTaskRef() {}
     virtual bool broken() const { return m_taskp && !m_taskp->brokeExists(); }

src/V3AstNodes.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <fstream>
 #include <iomanip>
 #include <vector>
@@ -304,6 +303,10 @@ void AstCellInline::dump(ostream& str) {
     this->AstNode::dump(str);
     str<<" -> "<<origModName();
 }
+void AstDisplay::dump(ostream& str) {
+    this->AstNode::dump(str);
+    //str<<" "<<displayType().ascii();
+}
 void AstPin::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modVarp()) { str<<" -> "; modVarp()->dump(str); }

src/V3AstNodes.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -53,7 +53,7 @@ public:
     uint32_t asInt()  const { return num().asInt(); }
     vluint64_t asQuad() const { return num().asQuad(); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() { return true; }
     virtual V3Hash sameHash() const { return V3Hash(num().asHash()); }
     virtual bool same(AstNode* samep) const {
@@ -81,7 +81,7 @@ struct AstRange : public AstNode {
     int	     msbConst()	const { AstConst* constp=msbp()->castConst(); return (constp?constp->asInt():0); }
     int	     lsbConst()	const { AstConst* constp=lsbp()->castConst(); return (constp?constp->asInt():0); }
     int	     elementsConst() const { return msbConst()-lsbConst()+1; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual V3Hash sameHash() const { return V3Hash(); }
     virtual bool same(AstNode* samep) const { return true; }
 };
@@ -100,7 +100,7 @@ struct AstArraySel : public AstNodeSel {
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) {
 	V3ERROR_NA; /* How can from be a const? */ }
     virtual string emitVerilog() { return "%k(%l%k[%r])"; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { return "%li%k[%ri]"; }
     virtual bool cleanOut() { return true; }
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -133,7 +133,7 @@ struct AstWordSel : public AstNodeSel {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit) { V3ERROR_NA; }
     virtual string emitVerilog() { return "%k(%l[%r])"; } // Not %k, as usually it's a small constant rhsp
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { return "%li[%ri]"; } // Not %k, as usually it's a small constant rhsp
     virtual bool cleanOut() { return true; }
     virtual bool cleanLhs() { return true; } virtual bool cleanRhs() { return true; }
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -206,7 +206,10 @@ struct AstSel : public AstNodeTriop {
     virtual void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit, const V3Number& width) {
 	out.opRange(from, bit.asInt()+width.asInt()-1, bit.asInt()); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() {
+	return this->widthp()->isOne()
+	    ? "VL_BITSEL_%nq%lq%rq%tq(%nw,%lw,%rw,%tw, %P, %li, %ri)"
+	    : "VL_SEL_%nq%lq%rq%tq(%nw,%lw,%rw,%tw, %P, %li, %ri, %ti)"; }
     virtual bool cleanOut() { return false; }
     virtual bool cleanLhs() { return true;} virtual bool cleanRhs() {return true;}
     virtual bool cleanThs() {return true;}
@@ -254,7 +257,7 @@ private:
 	m_sc=false; m_scClocked=false; m_scSensitive=false;
 	m_usedClock=false; m_usedParam=false;
 	m_sigPublic=false; m_sigModPublic=false;
-	m_funcLocal=false; m_funcReturn=false; 
+	m_funcLocal=false; m_funcReturn=false;
 	m_attrClockEn=false; m_attrIsolateAssign=false;
 	m_fileDescr=false; m_isConst=false; m_isStatic=false;
 	m_trace=false;
@@ -332,9 +335,10 @@ public:
     bool	isSignal() const  { return (varType()==AstVarType::WIRE || varType()==AstVarType::IMPLICIT
 					    || varType()==AstVarType::REG || varType()==AstVarType::INTEGER); }
     bool	isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP
-					 || varType()==AstVarType::STMTTEMP); }
+					 || varType()==AstVarType::STMTTEMP || varType()==AstVarType::XTEMP); }
     bool	isStatementTemp() const { return (varType()==AstVarType::STMTTEMP); }
     bool	isMovableToBlock() const { return (varType()==AstVarType::BLOCKTEMP || isFuncLocal()); }
+    bool	isPure() const { return (varType()==AstVarType::XTEMP); }
     bool	isParam() const { return (varType()==AstVarType::LPARAM || varType()==AstVarType::GPARAM); }
     bool	isGParam() const { return (varType()==AstVarType::GPARAM); }
     bool	isGenVar() const { return (varType()==AstVarType::GENVAR); }
@@ -421,7 +425,7 @@ struct AstScope : public AstNode {
 private:
     string	m_name;		// Name
     AstScope*	m_aboveScopep;	// Scope above this one in the hierarchy (NULL if top)
-    AstCell*	m_aboveCellp;	// Cell above this in the hiearchy (NULL if top)
+    AstCell*	m_aboveCellp;	// Cell above this in the hierarchy (NULL if top)
     AstModule*	m_modp;		// Module scope corresponds to
 public:
     AstScope(FileLine* fl, AstModule* modp, const string& name,
@@ -531,7 +535,7 @@ public:
 		     && varp()->name()==samep->castVarRef()->varp()->name()); }
     virtual int instrCount() const { return widthInstrs()*(lvalue()?1:instrCountLd()); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() { return true; }
 };
 
@@ -540,7 +544,7 @@ struct AstVarXRef : public AstNodeVarRef {
     // Includes pin on a cell, as part of a ASSIGN statement to connect I/Os until AstScope
 private:
     string	m_dotted;	// Scope name to connected to
-    string	m_inlinedDots;	// Dotted hiearchy flattened out
+    string	m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstVarXRef(FileLine* fl, const string& name, const string& dotted, bool lvalue)
 	:AstNodeVarRef(fl, name, NULL, lvalue)
@@ -554,12 +558,12 @@ public:
     virtual AstNode* clone() { return new AstVarXRef(*this);}
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void dump(ostream& str);
-    string	dotted() const { return m_dotted; }	
+    string	dotted() const { return m_dotted; }
     string	prettyDotted() const { return prettyName(dotted()); }
     string	inlinedDots() const { return m_inlinedDots; }
     void	inlinedDots(const string& flag) { m_inlinedDots = flag; }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() { return true; }
     virtual int instrCount() const { return widthInstrs(); }
     virtual V3Hash sameHash() const { return V3Hash(V3Hash(varp()),V3Hash(dotted())); }
@@ -755,7 +759,7 @@ public:
     AstNode*	stmtsp() 	const { return op1p()->castNode(); }	// op1 = List of statements
     void addStmtp(AstNode* nodep) { addOp1p(nodep); }
 };
-  
+
 struct AstGenerate : public AstNode {
     // A Generate/end block
     // Parents: MODULE
@@ -792,7 +796,7 @@ public:
     virtual V3Hash sameHash() const { return V3Hash(m_expect); }
     virtual bool same(AstNode* samep) const { return expect() == samep->castParseRef()->expect(); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     AstParseRefExp expect() const { return m_expect; }
     // op1 = Components
     AstNode*	lhsp() 		const { return op1p(); }	// op1 = List of statements
@@ -808,7 +812,7 @@ struct AstDot : public AstNode {
     virtual AstNode* clone() { return new AstDot(*this);}
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     AstNode* lhsp() const { return op1p(); }
     AstNode* rhsp() const { return op2p(); }
 };
@@ -1117,7 +1121,7 @@ private:
 public:
     AstCoverDecl(FileLine* fl, int column, const string& type, const string& comment)
 	: AstNodeStmt(fl) {
-	m_text = comment; m_typeText = type; m_column = column; 
+	m_text = comment; m_typeText = type; m_column = column;
     }
     virtual ~AstCoverDecl() {}
     virtual AstType type() const { return AstType::COVERDECL;}
@@ -1191,11 +1195,11 @@ struct AstCase : public AstNodeCase {
     // exprp Children:  MATHs
     // casesp Children: CASEITEMs
 private:
-    bool	m_casex;	// True if casex instead of normal case.
+    AstCaseType	m_casex;		// 0=case, 1=casex, 2=casez
     bool	m_fullPragma;		// Synthesis full_case
     bool	m_parallelPragma;	// Synthesis parallel_case
 public:
-    AstCase(FileLine* fileline, bool casex, AstNode* exprp, AstNode* casesp)
+    AstCase(FileLine* fileline, AstCaseType casex, AstNode* exprp, AstNode* casesp)
 	: AstNodeCase(fileline, exprp, casesp) {
 	m_casex=casex;
 	m_fullPragma=false; m_parallelPragma=false;
@@ -1204,11 +1208,14 @@ public:
     virtual AstType type() const { return AstType::CASE;}
     virtual AstNode* clone() { return new AstCase(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
-    virtual string  verilogKwd() const { return casex()?"casex":"case"; }
+    virtual string  verilogKwd() const { return casez()?"casez":casex()?"casex":"case"; }
-    bool	casex()	const { return m_casex; }
+    virtual bool same(AstNode* samep) const {
+	return m_casex==samep->castCase()->m_casex; }
+    bool	casex()	const { return m_casex==AstCaseType::CASEX; }
+    bool	casez()	const { return m_casex==AstCaseType::CASEZ; }
     bool	fullPragma()	const { return m_fullPragma; }
-    bool	parallelPragma()	const { return m_parallelPragma; }
     void	fullPragma(bool flag)	{ m_fullPragma=flag; }
+    bool	parallelPragma()	const { return m_parallelPragma; }
     void	parallelPragma(bool flag) { m_parallelPragma=flag; }
 };
 
@@ -1254,6 +1261,7 @@ public:
     virtual AstType type() const { return AstType::DISPLAY;}
     virtual AstNode* clone() { return new AstDisplay(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void dump(ostream& str);
     virtual string verilogKwd() const { return (filep() ? (string)"$f"+(string)displayType().ascii()
 						: (string)"$"+(string)displayType().ascii()); }
     virtual bool isGateOptimizable() const { return false; }
@@ -1271,11 +1279,8 @@ public:
     bool	addNewline() const { return displayType().addNewline(); }  // * = Add a newline for $display
     AstNode*	filep() const { return op2p(); }
     void 	filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
-    AstNode*	scopeAttrp() const { return op3p(); }
+    AstScopeName* scopeNamep() const { return op3p()->castScopeName(); }
-    AstText*	scopeTextp() const { return op3p()->castText(); }
+    void 	scopeNamep(AstNode* nodep) { setNOp3p(nodep); }
-    void scopeAttrp(AstNode* nodep) { addOp3p(nodep); }
-    bool	needScopeTracking() { return (displayType().needScopeTracking()
-					      || name().find("%m") != string::npos); }
 };
 
 struct AstFClose : public AstNodeStmt {
@@ -1325,6 +1330,101 @@ struct AstFOpen : public AstNodeStmt {
     AstNode*	modep() const { return op3p(); }
 };
 
+struct AstFFlush : public AstNodeStmt {
+    // Parents: stmtlist
+    // Children: file which must be a varref
+    AstFFlush(FileLine* fileline, AstNode* filep)
+	: AstNodeStmt (fileline) {
+	setNOp2p(filep);
+    }
+    virtual ~AstFFlush() {}
+    virtual AstType type() const { return AstType::FFLUSH;}
+    virtual AstNode* clone() { return new AstFFlush(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual string verilogKwd() const { return "$fflush"; };
+    virtual bool isGateOptimizable() const { return false; }
+    virtual bool isPredictOptimizable() const { return false; }
+    virtual bool isSplittable() const { return false; }
+    virtual bool isOutputter() const { return true; }
+    virtual bool isUnlikely() const { return true; }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstNode*	filep() const { return op2p(); }
+    void filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
+};
+
+struct AstFScanF : public AstNodeMath {
+    // Parents: expr
+    // Children: file which must be a varref
+    // Children: varrefs to load
+private:
+    string	m_text;
+public:
+    AstFScanF(FileLine* fileline, const string& text, AstNode* filep, AstNode* exprsp)
+	: AstNodeMath (fileline), m_text(text) {
+	addNOp1p(exprsp);
+	setNOp2p(filep);
+    }
+    virtual ~AstFScanF() {}
+    virtual AstType type() const { return AstType::FSCANF;}
+    virtual AstNode* clone() { return new AstFScanF(*this); }
+    virtual string name()	const { return m_text; }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual string verilogKwd() const { return "$fscanf"; }
+    virtual string emitVerilog() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
+    virtual bool isGateOptimizable() const { return false; }
+    virtual bool isPredictOptimizable() const { return false; }
+    virtual bool isSplittable() const { return false; }	// SPECIAL: has 'visual' ordering
+    virtual bool isOutputter() const { return true; }	// SPECIAL: makes output
+    virtual bool cleanOut() { return false; }
+    virtual V3Hash sameHash() const { return V3Hash(text()); }
+    virtual bool same(AstNode* samep) const {
+	return text()==samep->castFScanF()->text(); }
+    AstNode*	exprsp()	const { return op1p()->castNode(); }	// op1 = Expressions to output
+    void 	exprsp(AstNode* nodep)	{ addOp1p(nodep); }	// op1 = Expressions to output
+    string 	text()		const { return m_text; }		// * = Text to display
+    void 	text(const string& text) { m_text=text; }
+    AstNode*	filep() const { return op2p(); }
+    void 	filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
+};
+
+struct AstSScanF : public AstNodeMath {
+    // Parents: expr
+    // Children: file which must be a varref
+    // Children: varrefs to load
+private:
+    string	m_text;
+public:
+    AstSScanF(FileLine* fileline, const string& text, AstNode* fromp, AstNode* exprsp)
+	: AstNodeMath (fileline), m_text(text) {
+	addNOp1p(exprsp);
+	setOp2p(fromp);
+    }
+    virtual ~AstSScanF() {}
+    virtual AstType type() const { return AstType::SSCANF;}
+    virtual AstNode* clone() { return new AstSScanF(*this); }
+    virtual string name()	const { return m_text; }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual string verilogKwd() const { return "$sscanf"; }
+    virtual string emitVerilog() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
+    virtual bool isGateOptimizable() const { return false; }
+    virtual bool isPredictOptimizable() const { return false; }
+    virtual bool isSplittable() const { return false; }	// SPECIAL: has 'visual' ordering
+    virtual bool isOutputter() const { return true; }	// SPECIAL: makes output
+    virtual bool cleanOut() { return false; }
+    virtual V3Hash sameHash() const { return V3Hash(text()); }
+    virtual bool same(AstNode* samep) const {
+	return text()==samep->castSScanF()->text(); }
+    AstNode*	exprsp()	const { return op1p()->castNode(); }	// op1 = Expressions to output
+    void	exprsp(AstNode* nodep)	{ addOp1p(nodep); }	// op1 = Expressions to output
+    string 	text()		const { return m_text; }		// * = Text to display
+    void 	text(const string& text) { m_text=text; }
+    AstNode*	fromp() const { return op2p(); }
+    void 	fromp(AstNode* nodep) { setOp2p(nodep); }
+};
+
 struct AstReadMem : public AstNodeStmt {
 private:
     bool	m_isHex;	// readmemh, not readmemb
@@ -1453,9 +1553,8 @@ struct AstChangeXor : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opChangeXor(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l ^ %r)"; }
-    virtual string emitOperator() { return "VL_CHANGEXOR"; }
+    virtual string emitC() { return "VL_CHANGEXOR_%li(%lw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "^"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}  // Lclean && Rclean
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -1726,19 +1825,42 @@ public:
     int		dimension() const { return m_dimension; }
 };
 
+struct AstScopeName : public AstNode {
+    // For display %m
+    // Parents:  DISPLAY
+    // Children: TEXT
+    AstScopeName(FileLine* fl)
+	: AstNode(fl) {}
+    virtual ~AstScopeName() {}
+    virtual AstType type() const { return AstType::SCOPENAME;}
+    virtual AstNode* clone() { return new AstScopeName(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstText*	scopeAttrp() const { return op1p()->castText(); }
+    void 	scopeAttrp(AstNode* nodep) { addOp1p(nodep); }
+};
+
 //======================================================================
 // non-ary ops
 
 struct AstRand : public AstNodeTermop {
     // Return a random number, based upon width()
-    AstRand(FileLine* fl, int wwidth) : AstNodeTermop(fl) {
+private:
-	width(wwidth,wwidth); }
+    bool	m_reset;	// Random reset, versus always random
+public:
+    AstRand(FileLine* fl, int wwidth, bool reset) : AstNodeTermop(fl) {
+	width(wwidth,wwidth); m_reset=reset; }
+    AstRand(FileLine* fl) : AstNodeTermop(fl), m_reset(false) { }
     virtual ~AstRand() {}
     virtual AstType type() const { return AstType::RAND;}
     virtual AstNode* clone() { return new AstRand(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual string emitVerilog() { return "$random"; }
-    virtual string emitOperator() { return "VL_RAND_RESET"; }
+    virtual string emitC() {
+	return (m_reset ?
+		"VL_RAND_RESET_%nq(%nw, %P)"
+		:"VL_RANDOM_%nq(%nw, %P)"); }
     virtual bool cleanOut() { return true; }
     virtual bool isGateOptimizable() const { return false; }
     virtual bool isPredictOptimizable() const { return false; }
@@ -1755,7 +1877,7 @@ struct AstTime : public AstNodeTermop {
     virtual AstNode* clone() { return new AstTime(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual string emitVerilog() { return "$time"; }
-    virtual string emitOperator() { return "VL_TIME"; }
+    virtual string emitC() { return "VL_TIME_%nq()"; }
     virtual bool cleanOut() { return true; }
     virtual bool isGateOptimizable() const { return false; }
     virtual bool isPredictOptimizable() const { return false; }
@@ -1777,7 +1899,7 @@ public:
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual bool cleanOut() { return false; }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     AstNode*	bodysp()	const { return op1p()->castNode(); }	// op1= expressions to print
     virtual bool isSplittable() const { return false; }	// SPECIAL: User may order w/other sigs
     virtual bool isOutputter() const { return true; }
@@ -1801,8 +1923,7 @@ struct AstUnaryMin : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opUnaryMin(lhs); }
     virtual string emitVerilog() { return "%k(- %l)"; }
-    virtual string emitOperator() { return "VL_UNARYMIN"; }
+    virtual string emitC() { return "VL_UNARYMIN_%lq(%lW, %P, %li)"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;}
     virtual bool sizeMattersLhs() {return true;}
 };
@@ -1815,7 +1936,7 @@ struct AstRedAnd : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opRedAnd(lhs); }
     virtual string emitVerilog() { return "%k(& %l)"; }
-    virtual string emitOperator() { return "VL_REDAND"; }
+    virtual string emitC() { return "VL_REDAND_%nq%lq(%nw,%lw, %P, %li)"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
 };
@@ -1828,8 +1949,7 @@ struct AstRedOr : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opRedOr(lhs); }
     virtual string emitVerilog() { return "%k(| %l)"; }
-    virtual string emitOperator() { return "VL_REDOR"; }
+    virtual string emitC() { return "VL_REDOR_%lq(%lW, %P, %li)"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
 };
@@ -1842,8 +1962,7 @@ struct AstRedXor : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opRedXor(lhs); }
     virtual string emitVerilog() { return "%k(^ %l)"; }
-    virtual string emitOperator() { return "VL_REDXOR"; }
+    virtual string emitC() { return "VL_REDXOR_%lq(%lW, %P, %li)"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return (lhsp()->width()!=1 && lhsp()->width()!=2 && lhsp()->width()!=4
 				     && lhsp()->width()!=8 && lhsp()->width()!=16);}
@@ -1860,8 +1979,7 @@ struct AstRedXnor : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opRedXnor(lhs); }
     virtual string emitVerilog() { return "%k(~^ %l)"; }
-    virtual string emitOperator() { v3fatalSrc("REDXNOR should have became REDXOR"); return ""; }
+    virtual string emitC() { v3fatalSrc("REDXNOR should have became REDXOR"); return ""; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
     virtual int instrCount()	const { return 1+V3Number::log2b(width()); }
@@ -1876,7 +1994,7 @@ struct AstLogNot : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opLogNot(lhs); }
     virtual string emitVerilog() { return "%k(! %l)"; }
-    virtual string emitOperator() { return "VL_LOGNOT"; }
+    virtual string emitC() { return "VL_LOGNOT_%nq%lq(%nw,%lw, %P, %li)"; }
     virtual string emitSimpleOperator() { return "!"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
@@ -1890,9 +2008,8 @@ struct AstNot : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opNot(lhs); }
     virtual string emitVerilog() { return "%k(~ %l)"; }
-    virtual string emitOperator() { return "VL_NOT"; }
+    virtual string emitC() { return "VL_NOT_%lq(%lW, %P, %li)"; }
     virtual string emitSimpleOperator() { return "~"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;}
     virtual bool sizeMattersLhs() {return true;}
 };
@@ -1905,7 +2022,7 @@ struct AstExtend : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); }
     virtual string emitVerilog() { return "%l"; }
-    virtual string emitOperator() { return "VL_EXTEND"; }
+    virtual string emitC() { return "VL_EXTEND_%nq%lq(%nw,%lw, %P, %li)"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}  // Because the EXTEND operator self-casts
     virtual int instrCount()	const { return 0; }
@@ -1919,7 +2036,7 @@ struct AstExtendS : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opExtendS(lhs); }
     virtual string emitVerilog() { return "%l"; }
-    virtual string emitOperator() { return "VL_EXTENDS"; }
+    virtual string emitC() { return "VL_EXTENDS_%nq%lq(%nw,%lw, %P, %li)"; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}  // Because the EXTEND operator self-casts
     virtual int instrCount()	const { return 0; }
@@ -1936,7 +2053,7 @@ struct AstSigned : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); out.isSigned(false); }
     virtual string emitVerilog() { return "%k$signed(%l)"; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;}  // Eliminated before matters
     virtual bool sizeMattersLhs() {return true;}  // Eliminated before matters
     virtual int instrCount()	const { return 0; }
@@ -1952,11 +2069,24 @@ struct AstUnsigned : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); out.isSigned(false); }
     virtual string emitVerilog() { return "%k$unsigned(%l)"; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;}  // Eliminated before matters
     virtual bool sizeMattersLhs() {return true;}  // Eliminated before matters
     virtual int instrCount()	const { return 0; }
 };
+struct AstCLog2 : public AstNodeUniop {
+    AstCLog2(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
+    virtual ~AstCLog2() {}
+    virtual AstType type() const { return AstType::CLOG2;}
+    virtual AstNode* clone() { return new AstCLog2(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opCLog2(lhs); }
+    virtual string emitVerilog() { return "%k$clog2(%l)"; }
+    virtual string emitC() { return "VL_CLOG2_%lq(%lW, %P, %li)"; }
+    virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*16; }
+};
 struct AstCountOnes : public AstNodeUniop {
     // Number of bits set in vector
     AstCountOnes(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
@@ -1966,8 +2096,7 @@ struct AstCountOnes : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opCountOnes(lhs); }
     virtual string emitVerilog() { return "%k$countones(%l)"; }
-    virtual bool emitWordForm() { return true; }
+    virtual string emitC() { return "VL_COUNTONES_%lq(%lW, %P, %li)"; }
-    virtual string emitOperator() { return "VL_COUNTONES"; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
     virtual int instrCount()	const { return widthInstrs()*16; }
@@ -1982,7 +2111,7 @@ struct AstIsUnknown : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opIsUnknown(lhs); }
     virtual string emitVerilog() { return "%k$isunknown(%l)"; }
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return false;}
     virtual bool sizeMattersLhs() {return false;}
 };
@@ -1996,8 +2125,7 @@ struct AstOneHot : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opOneHot(lhs); }
     virtual string emitVerilog() { return "%k$onehot(%l)"; }
-    virtual bool emitWordForm() { return true; }
+    virtual string emitC() { return "VL_ONEHOT_%lq(%lW, %P, %li)"; }
-    virtual string emitOperator() { return "VL_ONEHOT"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
     virtual int instrCount()	const { return widthInstrs()*4; }
@@ -2012,8 +2140,7 @@ struct AstOneHot0 : public AstNodeUniop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opOneHot0(lhs); }
     virtual string emitVerilog() { return "%k$onehot0(%l)"; }
-    virtual bool emitWordForm() { return true; }
+    virtual string emitC() { return "VL_ONEHOT0_%lq(%lW, %P, %li)"; }
-    virtual string emitOperator() { return "VL_ONEHOT0"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}
     virtual int instrCount()	const { return widthInstrs()*3; }
@@ -2038,7 +2165,7 @@ public:
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); }
     virtual string emitVerilog() { return "%k$_CAST(%l)"; }
-    virtual string emitOperator() { return "VL_CAST"; }
+    virtual string emitC() { return "VL_CAST_%nq%lq(%nw,%lw, %P, %li)"; }
     virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
     virtual bool sizeMattersLhs() {return false;}  // Special cased in V3Cast
     virtual V3Hash sameHash() const { return V3Hash(size()); }
@@ -2048,6 +2175,37 @@ public:
     int size()	const { return m_size; }
 };
 
+struct AstFEof : public AstNodeUniop {
+    AstFEof(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
+    virtual ~AstFEof() {}
+    virtual AstType type() const { return AstType::FEOF;}
+    virtual AstNode* clone() { return new AstFEof(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs) { V3ERROR_NA; }
+    virtual string emitVerilog() { return "%k$feof(%l)"; }
+    virtual string emitC() { return "(%li ? feof(VL_CVT_Q_FP(%li)) : true)"; }
+    virtual bool cleanOut() {return true;} virtual bool cleanLhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*16; }
+    AstNode*	filep() const { return lhsp(); }
+};
+
+struct AstFGetC : public AstNodeUniop {
+    AstFGetC(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
+    virtual ~AstFGetC() {}
+    virtual AstType type() const { return AstType::FEOF;}
+    virtual AstNode* clone() { return new AstFGetC(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs) { V3ERROR_NA; }
+    virtual string emitVerilog() { return "%k$fgetc(%l)"; }
+    // Non-existant filehandle returns EOF
+    virtual string emitC() { return "(%li ? fgetc(VL_CVT_Q_FP(%li)) : -1)"; }
+    virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*64; }
+    AstNode*	filep() const { return lhsp(); }
+};
+
 //======================================================================
 // Binary ops
 
@@ -2060,7 +2218,7 @@ struct AstLogOr : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLogOr(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k|| %r)"; }
-    virtual string emitOperator() { return "VL_LOGOR"; }
+    virtual string emitC() { return "VL_LOGOR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "||"; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2076,7 +2234,7 @@ struct AstLogAnd : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLogAnd(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k&& %r)"; }
-    virtual string emitOperator() { return "VL_LOGAND"; }
+    virtual string emitC() { return "VL_LOGAND_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "&&"; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2092,7 +2250,7 @@ struct AstLogIf : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { V3ERROR_NA; }
     virtual string emitVerilog() { return "%k(%l %k-> %r)"; }
-    virtual string emitOperator() { return "VL_LOGIF"; }
+    virtual string emitC() { return "VL_LOGIF_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "->"; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2108,7 +2266,7 @@ struct AstLogIff : public AstNodeBiCom {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { V3ERROR_NA; }
     virtual string emitVerilog() { return "%k(%l %k<-> %r)"; }
-    virtual string emitOperator() { return "VL_LOGIFF"; }
+    virtual string emitC() { return "VL_LOGIFF_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "<->"; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2124,9 +2282,8 @@ struct AstOr : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opOr(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k| %r)"; }
-    virtual string emitOperator() { return "VL_OR"; }
+    virtual string emitC() { return "VL_OR_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "|"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {V3ERROR_NA; return false;}  // Lclean && Rclean
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2140,9 +2297,8 @@ struct AstAnd : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opAnd(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k& %r)"; }
-    virtual string emitOperator() { return "VL_AND"; }
+    virtual string emitC() { return "VL_AND_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "&"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {V3ERROR_NA; return false;}  // Lclean || Rclean
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2156,9 +2312,8 @@ struct AstXor : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opXor(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k^ %r)"; }
-    virtual string emitOperator() { return "VL_XOR"; }
+    virtual string emitC() { return "VL_XOR_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "^"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}  // Lclean && Rclean
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2172,9 +2327,8 @@ struct AstXnor : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opXnor(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k^ ~ %r)"; }
-    virtual string emitOperator() { return "VL_XNOR"; }
+    virtual string emitC() { return "VL_XNOR_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "^ ~"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2188,9 +2342,8 @@ struct AstEq : public AstNodeBiCom {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opEq(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k== %r)"; }
-    virtual string emitOperator() { return "VL_EQ"; }
+    virtual string emitC() { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "=="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2204,9 +2357,8 @@ struct AstNeq : public AstNodeBiCom {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opNeq(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k!= %r)"; }
-    virtual string emitOperator() { return "VL_NEQ"; }
+    virtual string emitC() { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "!="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2220,9 +2372,8 @@ struct AstLt : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLt(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k< %r)"; }
-    virtual string emitOperator() { return "VL_LT"; }
+    virtual string emitC() { return "VL_LT_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "<"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2236,9 +2387,8 @@ struct AstLtS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLtS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k< %r)"; }
-    virtual string emitOperator() { return "VL_LTS"; }
+    virtual string emitC() { return "VL_LTS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2253,9 +2403,8 @@ struct AstGt : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opGt(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k> %r)"; }
-    virtual string emitOperator() { return "VL_GT"; }
+    virtual string emitC() { return "VL_GT_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ">"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2269,9 +2418,8 @@ struct AstGtS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opGtS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k> %r)"; }
-    virtual string emitOperator() { return "VL_GTS"; }
+    virtual string emitC() { return "VL_GTS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2286,9 +2434,8 @@ struct AstGte : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opGte(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k>= %r)"; }
-    virtual string emitOperator() { return "VL_GTE"; }
+    virtual string emitC() { return "VL_GTE_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ">="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2302,9 +2449,8 @@ struct AstGteS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opGteS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k>= %r)"; }
-    virtual string emitOperator() { return "VL_GTES"; }
+    virtual string emitC() { return "VL_GTES_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2319,9 +2465,8 @@ struct AstLte : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLte(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k<= %r)"; }
-    virtual string emitOperator() { return "VL_LTE"; }
+    virtual string emitC() { return "VL_LTE_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "<="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2335,9 +2480,8 @@ struct AstLteS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opLteS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k<= %r)"; }
-    virtual string emitOperator() { return "VL_LTES"; }
+    virtual string emitC() { return "VL_LTES_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2354,7 +2498,7 @@ struct AstShiftL : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opShiftL(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k<< %r)"; }
-    virtual string emitOperator() { return "VL_SHIFTL"; }
+    virtual string emitC() { return "VL_SHIFTL_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "<<"; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return true;}
@@ -2371,7 +2515,7 @@ struct AstShiftR : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opShiftR(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k>> %r)"; }
-    virtual string emitOperator() { return "VL_SHIFTR"; }
+    virtual string emitC() { return "VL_SHIFTR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ">>"; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2388,7 +2532,7 @@ struct AstShiftRS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opShiftRS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k>>> %r)"; }
-    virtual string emitOperator() { return "VL_SHIFTRS"; }
+    virtual string emitC() { return "VL_SHIFTRS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
@@ -2404,9 +2548,8 @@ struct AstAdd : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opAdd(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k+ %r)"; }
-    virtual string emitOperator() { return "VL_ADD"; }
+    virtual string emitC() { return "VL_ADD_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "+"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2420,9 +2563,8 @@ struct AstSub : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opSub(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k- %r)"; }
-    virtual string emitOperator() { return "VL_SUB"; }
+    virtual string emitC() { return "VL_SUB_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "-"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return false;} virtual bool cleanRhs() {return false;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2436,9 +2578,8 @@ struct AstMul : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opMul(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k* %r)"; }
-    virtual string emitOperator() { return "VL_MUL"; }
+    virtual string emitC() { return "VL_MUL_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "*"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2453,9 +2594,8 @@ struct AstMulS : public AstNodeBiComAsv {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opMulS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k* %r)"; }
-    virtual string emitOperator() { return "VL_MULS"; }
+    virtual string emitC() { return "VL_MULS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return ""; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2471,8 +2611,7 @@ struct AstDiv : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opDiv(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k/ %r)"; }
-    virtual string emitOperator() { return "VL_DIV"; }
+    virtual string emitC() { return "VL_DIV_%lq(%lW, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2487,8 +2626,7 @@ struct AstDivS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opDivS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k/ %r)"; }
-    virtual string emitOperator() { return "VL_DIVS"; }
+    virtual string emitC() { return "VL_DIVS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2504,8 +2642,7 @@ struct AstModDiv : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opModDiv(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k%% %r)"; }
-    virtual string emitOperator() { return "VL_MODDIV"; }
+    virtual string emitC() { return "VL_MODDIV_%lq(%lW, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2520,8 +2657,7 @@ struct AstModDivS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opModDivS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k%% %r)"; }
-    virtual string emitOperator() { return "VL_MODDIVS"; }
+    virtual string emitC() { return "VL_MODDIVS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return true;}
@@ -2537,8 +2673,7 @@ struct AstPow : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPow(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k** %r)"; }
-    virtual string emitOperator() { return "VL_POW"; }
+    virtual string emitC() { return "VL_POW_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
@@ -2553,8 +2688,7 @@ struct AstPowS : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opPowS(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k** %r)"; }
-    virtual string emitOperator() { return "VL_POWS"; }
+    virtual string emitC() { return "VL_POWS_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
-    virtual bool emitWordForm() { return false; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return true;} virtual bool sizeMattersRhs() {return false;}
@@ -2570,9 +2704,8 @@ struct AstEqCase : public AstNodeBiCom {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opCaseEq(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k=== %r)"; }
-    virtual string emitOperator() { return "VL_EQ"; }	// Until have 4 state anyways
+    virtual string emitC() { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "=="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2586,9 +2719,39 @@ struct AstNeqCase : public AstNodeBiCom {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opCaseNeq(lhs,rhs); }
     virtual string emitVerilog() { return "%k(%l %k!== %r)"; }
-    virtual string emitOperator() { return "VL_NEQ"; }	// Until have 4 state anyways
+    virtual string emitC() { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; }
+    virtual string emitSimpleOperator() { return "!="; }
+    virtual bool cleanOut() {return true;}
+    virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
+};
+struct AstEqWild : public AstNodeBiop {
+    // Note wildcard operator rhs differs from lhs
+    AstEqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+	width(1,1); }
+    virtual ~AstEqWild() {}
+    virtual AstType type() const { return AstType::EQWILD;}
+    virtual AstNode* clone() { return new AstEqWild(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opWildEq(lhs,rhs); }
+    virtual string emitVerilog() { return "%k(%l %k==? %r)"; }
+    virtual string emitC() { return "VL_EQ_%lq(%lW, %P, %li, %ri)"; }
+    virtual string emitSimpleOperator() { return "=="; }
+    virtual bool cleanOut() {return true;}
+    virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
+};
+struct AstNeqWild : public AstNodeBiop {
+    AstNeqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
+	width(1,1); }
+    virtual ~AstNeqWild() {}
+    virtual AstType type() const { return AstType::NEQWILD;}
+    virtual AstNode* clone() { return new AstNeqWild(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opWildNeq(lhs,rhs); }
+    virtual string emitVerilog() { return "%k(%l %k!=? %r)"; }
+    virtual string emitC() { return "VL_NEQ_%lq(%lW, %P, %li, %ri)"; }
     virtual string emitSimpleOperator() { return "!="; }
-    virtual bool emitWordForm() { return true; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2604,7 +2767,7 @@ struct AstConcat : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual string emitVerilog() { return "%k{%l, %k%r}"; }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opConcat(lhs,rhs); }
-    virtual string emitOperator() { return "VL_CONCAT"; }
+    virtual string emitC() { return "VL_CONCAT_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual bool cleanOut() {return true;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
@@ -2620,12 +2783,28 @@ struct AstReplicate : public AstNodeBiop {
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opRepl(lhs,rhs); }
     virtual string emitVerilog() { return "%k{%l{%k%r}}"; }
-    virtual string emitOperator() { return "VL_REPLICATE"; }
+    virtual string emitC() { return "VL_REPLICATE_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; }
     virtual bool cleanOut() {return false;}
     virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
     virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
     virtual int instrCount()	const { return widthInstrs()*2; }
 };
+struct AstFGetS : public AstNodeBiop {
+    AstFGetS(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {}
+    virtual ~AstFGetS() {}
+    virtual AstType type() const { return AstType::FEOF;}
+    virtual AstNode* clone() { return new AstFGetS(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { V3ERROR_NA; }
+    virtual string emitVerilog() { return "%k$fgets(%l,%r)"; }
+    virtual string emitC() { return "VL_FGETS_%nqX%rq(%lw, %P, &(%li), %ri)"; }
+    virtual bool cleanOut() {return false;}
+    virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*64; }
+    AstNode*	strgp() const { return lhsp(); }
+    AstNode*	filep() const { return rhsp(); }
+};
 
 //======================================================================
 // SysVerilog assertions
@@ -3094,7 +3273,7 @@ struct AstCMath : public AstNodeMath {
     virtual bool isPredictOptimizable() const { return false; }
     virtual bool cleanOut() { return true; }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
-    virtual string emitOperator() { V3ERROR_NA; return ""; }
+    virtual string emitC() { V3ERROR_NA; return ""; }
     virtual V3Hash sameHash() const { return V3Hash(); }
     virtual bool same(AstNode* samep) const { return true; }
 };

src/V3Begin.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Begin's Transformations:
-//		
+//
 // Each module:
 //	Look for BEGINs
 //	    BEGIN(VAR...) -> VAR ... {renamed}
@@ -29,9 +28,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
+#include <cstring>
 #include <algorithm>
 #include <vector>
 
@@ -131,10 +131,10 @@ private:
 	nodep->replaceWith(newp);
 	nodep->deleteTree(); nodep=NULL;
     }
-    virtual void visit(AstDisplay* nodep, AstNUser*) {
+    virtual void visit(AstScopeName* nodep, AstNUser*) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
 	// Similar code in V3Inline
-	if (m_beginScope != "" && nodep->needScopeTracking()) {
+	if (m_beginScope != "") {
 	    // To keep correct visual order, must add before other Text's
 	    AstNode* afterp = nodep->scopeAttrp();
 	    if (afterp) afterp->unlinkFrBackWithNext();

src/V3Begin.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Branch.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,14 +20,14 @@
 // BRANCH TRANSFORMATIONS:
 //	At each IF/(IF else).
 //	   Count underneath $display/$stop statements.
-//	   If more on if then else, this branch is unlikely, or vice-versa.
+//	   If more on if than else, this branch is unlikely, or vice-versa.
 //
 //*************************************************************************
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 

src/V3Branch.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Broken.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Broken's Transformations:
-//		
+//
 // Entire netlist
 //	Mark all nodes
 //	Check all links point to marked nodes
@@ -28,11 +27,11 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
-#include <set>
+#include <map>
 
 #include "V3Global.h"
 #include "V3Broken.h"
@@ -45,19 +44,100 @@ class BrokenTable : public AstNVisitor {
 private:
     // MEMBERS
     //   For each node, we keep if it exists or not.
-    typedef set<const AstNode*> NodeSet;
+    typedef map<const AstNode*,int> NodeMap;
-    static NodeSet s_nodes;	// Set of all nodes that exist
+    static NodeMap s_nodes;	// Set of all nodes that exist
+    // BITMASK
+    static const int FLAG_ALLOCATED	= 0x01;		// new() and not delete()ed
+    static const int FLAG_IN_TREE	= 0x02;		// Is in netlist tree
+    static const int FLAG_LINKABLE	= 0x04;		// Is in netlist tree, can be linked to
+    static const int FLAG_LEAKED	= 0x08;		// Known to have been leaked
 public:
     // METHODS
-    static void add(const AstNode* nodep) {
+    static void deleted(const AstNode* nodep) {
-	s_nodes.insert(nodep);
+	// Called by operator delete on any node - only if VL_LEAK_CHECKS
+	if (debug()) cout<<"-nodeDel:  "<<(void*)(nodep)<<endl;
+	NodeMap::iterator iter = s_nodes.find(nodep);
+	if (iter==s_nodes.end() || !(iter->second & FLAG_ALLOCATED)) {
+	    ((AstNode*)(nodep))->v3fatalSrc("Deleting AstNode object that was never tracked or already deleted\n");
+	}
+	if (iter!=s_nodes.end()) s_nodes.erase(iter);
     }
-    static bool exists(const AstNode* nodep) {
+    static void addNewed(const AstNode* nodep) {
-	NodeSet::iterator iter = s_nodes.find(nodep);
+	// Called by operator new on any node - only if VL_LEAK_CHECKS
-	return (iter != s_nodes.end());
+	if (debug()) cout<<"-nodeNew:  "<<(void*)(nodep)<<endl;
+	NodeMap::iterator iter = s_nodes.find(nodep);
+	if (iter!=s_nodes.end() || (iter->second & FLAG_ALLOCATED)) {
+	    ((AstNode*)(nodep))->v3fatalSrc("Newing AstNode object that is already allocated\n");
+	}
+	if (iter == s_nodes.end()) {
+	    s_nodes.insert(make_pair(nodep,FLAG_ALLOCATED));
+	}
     }
-    static void clear() {
+    static void addInTree(AstNode* nodep, bool linkable) {
+#ifndef VL_LEAK_CHECKS
+	if (!linkable) return;  // save some time, else the map will get huge!
+#endif
+	NodeMap::iterator iter = s_nodes.find(nodep);
+	if (iter == s_nodes.end()) {
+#ifdef VL_LEAK_CHECKS
+	    nodep->v3fatalSrc("AstNode is in tree, but not allocated\n");
+#endif
+	} else {
+	    if (!(iter->second & FLAG_ALLOCATED)) {
+#ifdef VL_LEAK_CHECKS
+		nodep->v3fatalSrc("AstNode is in tree, but not allocated\n");
+#endif
+	    }
+	    if (iter->second & FLAG_IN_TREE) {
+		nodep->v3fatalSrc("AstNode is already in tree at another location\n");
+	    }
+	}
+	int or_flags = FLAG_IN_TREE | (linkable?FLAG_LINKABLE:0);
+	if (iter == s_nodes.end()) {
+	    s_nodes.insert(make_pair(nodep,or_flags));
+	} else {
+	    iter->second |= or_flags;
+	}
+    }
+    static bool okIfLinkedTo(const AstNode* nodep) {
+	// Someone has a pointer to this node.  Is it kosher?
+	NodeMap::iterator iter = s_nodes.find(nodep);
+	if (iter == s_nodes.end()) return false;
+#ifdef VL_LEAK_CHECKS
+	if (!(iter->second & FLAG_ALLOCATED)) return false;
+#endif
+	if (!(iter->second & FLAG_IN_TREE)) return false;
+	if (!(iter->second & FLAG_LINKABLE)) return false;
+	return true;
+    }
+    static void prepForTree() {
+#ifndef VL_LEAK_CHECKS
 	s_nodes.clear();
+#endif
+	for (NodeMap::iterator it = s_nodes.begin(); it != s_nodes.end(); ++it) {
+	    it->second &= ~FLAG_IN_TREE;
+	    it->second &= ~FLAG_LINKABLE;
+	}
+    }
+    static void doneWithTree() {
+	for (int backs=0; backs<2; backs++) {  // Those with backp() are probably under one leaking without
+	    for (NodeMap::iterator it = s_nodes.begin(); it != s_nodes.end(); ++it) {
+		if ((it->second & FLAG_ALLOCATED)
+		    && !(it->second & FLAG_IN_TREE)
+		    && !(it->second & FLAG_LEAKED)
+		    && (it->first->backp() ? backs==1 : backs==0)) {
+		    // Use only AstNode::dump instead of the virtual one, as there
+		    // may be varp() and other cross links that are bad.
+		    if (debug()) {
+			cout<<"%Error: LeakedNode"<<(it->first->backp()?"Back: ":": ");
+			((AstNode*)(it->first))->AstNode::dump(cout);
+			cout<<endl;
+			V3Error::incErrors();
+		    }
+		    it->second |= FLAG_LEAKED;
+		}
+	    }
+	}
     }
 public:
     // CONSTUCTORS
@@ -65,11 +145,11 @@ public:
     virtual ~BrokenTable() {}
 };
 
-BrokenTable::NodeSet BrokenTable::s_nodes;
+BrokenTable::NodeMap BrokenTable::s_nodes;
 
 bool AstNode::brokeExists() const {
     // Called by node->broken() routines to do table lookup
-    return BrokenTable::exists(this);
+    return BrokenTable::okIfLinkedTo(this);
 }
 
 //######################################################################
@@ -82,9 +162,7 @@ private:
     //			// so userp and friends may not be used
     // VISITORS
     virtual void visit(AstNode* nodep, AstNUser*) {
-	if (nodep->maybePointedTo()) {
+	BrokenTable::addInTree(nodep, nodep->maybePointedTo());
-	    BrokenTable::add(nodep);
-	}
 	nodep->iterateChildren(*this);
     }
 public:
@@ -127,8 +205,15 @@ public:
 
 void V3Broken::brokenAll(AstNetlist* nodep) {
     //UINFO(9,__FUNCTION__<<": "<<endl);
-    BrokenTable::clear();
+    BrokenTable::prepForTree();
     BrokenMarkVisitor mvisitor (nodep);
     BrokenCheckVisitor cvisitor (nodep);
-    BrokenTable::clear();
+    BrokenTable::doneWithTree();
+}
+
+void V3Broken::addNewed(AstNode* nodep) {
+    BrokenTable::addNewed(nodep);
+}
+void V3Broken::deleted(AstNode* nodep) {
+    BrokenTable::deleted(nodep);
 }

src/V3Broken.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -31,6 +31,8 @@
 class V3Broken {
 public:
     static void brokenAll(AstNetlist* nodep);
+    static void addNewed(AstNode* nodep);
+    static void deleted(AstNode* nodep);
 };
 
 #endif // Guard

src/V3Case.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Case's Transformations:
-//		
+//
 // Each module:
 //	TBD: Eliminate tristates by adding __in, __inen, __en wires in parallel
 //	    Need __en in changed list if a signal is on the LHS of a assign
@@ -40,8 +39,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -62,9 +61,6 @@ private:
     //int debug() { return 9; }
 
     virtual void visit(AstNodeCase* nodep, AstNUser*) {
-	// We report a syntax error on empty "case (x) endcase" blocks, so never no items at all
-	if (!nodep->itemsp()) nodep->v3fatalSrc("No items (not even default) under case statement?\n");
-
 	// Detect multiple defaults
 	bool hitDefault = false;
 	for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
@@ -77,7 +73,7 @@ private:
 	}
 
 	// Check for X/Z in non-casex statements
-	if (!nodep->castCase() || !nodep->castCase()->casex()) {
+	{
 	    m_caseExprp = nodep;
 	    nodep->exprp()->accept(*this);
 	    for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
@@ -87,11 +83,18 @@ private:
 	}
     }
     virtual void visit(AstConst* nodep, AstNUser*) {
+	// See also neverItem
 	if (m_caseExprp && nodep->num().isFourState()) {
 	    if (m_caseExprp->castGenCase()) {
 		nodep->v3error("Use of x/? constant in generate case statement, (no such thing as 'generate casez')");
+	    } else if (m_caseExprp->castCase() && m_caseExprp->castCase()->casex()) {
+		// Don't sweat it, we already complained about casex in general
+	    } else if (m_caseExprp->castCase() && m_caseExprp->castCase()->casez()) {
+		if (nodep->num().isUnknown()) {
+		    nodep->v3warn(CASEWITHX, "Use of x constant in casez statement, (perhaps intended ?/z in constant)");
+		}
 	    } else {
-		nodep->v3error("Use of x/? constant in case statement, (perhaps intended casex/casez)");
+		nodep->v3warn(CASEWITHX, "Use of x/? constant in case statement, (perhaps intended casex/casez)");
 	    }
 	}
     }
@@ -156,20 +159,24 @@ private:
 		//if (debug()>=9) icondp->dumpTree(cout," caseitem: ");
 		AstConst* iconstp = icondp->castConst();
 		if (!iconstp) nodep->v3fatalSrc("above 'can't parse' should have caught this\n");
-		V3Number nummask (itemp->fileline(), iconstp->width());
+		if (neverItem(nodep, iconstp)) {
-		nummask.opBitsNonX(iconstp->num());
+		    // X in casez can't ever be executed
-		uint32_t mask = nummask.asInt();
+		} else {
-		V3Number numval  (itemp->fileline(), iconstp->width());
+		    V3Number nummask (itemp->fileline(), iconstp->width());
-		numval.opBitsOne(iconstp->num());
+		    nummask.opBitsNonX(iconstp->num());
-		uint32_t val  = numval.asInt();
+		    uint32_t mask = nummask.asInt();
-		for (uint32_t i=0; i<(1UL<<m_caseWidth); i++) {
+		    V3Number numval  (itemp->fileline(), iconstp->width());
-		    if ((i & mask) == val) {
+		    numval.opBitsOne(iconstp->num());
-			if (!m_valueItem[i]) {
+		    uint32_t val  = numval.asInt();
-			    m_valueItem[i] = itemp;
+		    for (uint32_t i=0; i<(1UL<<m_caseWidth); i++) {
-			} else if (!itemp->ignoreOverlap() && !bitched) {
+			if ((i & mask) == val) {
-			    itemp->v3warn(CASEOVERLAP,"Case values overlap (example pattern 0x"<<hex<<i<<")");
+			    if (!m_valueItem[i]) {
-			    bitched = true;
+				m_valueItem[i] = itemp;
-			    m_caseNoOverlapsAllCovered = false;
+			    } else if (!itemp->ignoreOverlap() && !bitched) {
+				itemp->v3warn(CASEOVERLAP,"Case values overlap (example pattern 0x"<<hex<<i<<")");
+				bitched = true;
+				m_caseNoOverlapsAllCovered = false;
+			    }
 			}
 		    }
 		}
@@ -221,7 +228,10 @@ private:
 		 a++, b++) {
 		if (m_valueItem[a] != m_valueItem[b]) { same=false; break; }
 	    }
-	    if (same) return tree0p;
+	    if (same) {
+		tree1p->deleteTree(); tree1p=NULL;
+		return tree0p;
+	    }
 
 	    // Must have differing logic, so make a selection
 
@@ -235,7 +245,7 @@ private:
 	    //                            new AstConst(cexprp->fileline(), nummask));
 	    AstNode* and1p = new AstSel(cexprp->fileline(), cexprp->cloneTree(false),
 					msb, 1);
-	    AstNode* eqp = new AstNeq(cexprp->fileline(), 
+	    AstNode* eqp = new AstNeq(cexprp->fileline(),
 				      new AstConst(cexprp->fileline(), 0),
 				      and1p);
 	    AstIf* ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p);
@@ -248,8 +258,7 @@ private:
 	// CASEx(cexpr,....
 	// ->  tree of IF(msb,  IF(msb-1, 11, 10)
 	//                      IF(msb-1, 01, 00))
-	AstNode* cexprp = nodep->exprp();
+	AstNode* cexprp = nodep->exprp()->unlinkFrBack();
-	cexprp->unlinkFrBack();
 
 	if (debug()>=9) {
 	    for (uint32_t i=0; i<(1UL<<m_caseWidth); i++) {
@@ -267,6 +276,8 @@ private:
 
 	if (ifrootp) nodep->replaceWith(ifrootp);
 	else nodep->unlinkFrBack();
+	nodep->deleteTree(); nodep=NULL;
+	cexprp->deleteTree(); cexprp=NULL;
 	if (debug()>=9) ifrootp->dumpTree(cout,"    _simp: ");
     }
 
@@ -292,21 +303,29 @@ private:
 		for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondNextp) {
 		    icondNextp = icondp->nextp();
 		    icondp->unlinkFrBack();
-		    
+
 		    AstNode* and1p;
 		    AstNode* and2p;
 		    AstConst* iconstp = icondp->castConst();
-		    if (iconstp && iconstp->num().isFourState()
+		    if (iconstp && neverItem(nodep, iconstp)) {
-			&& nodep->casex()) {
+			// X in casez can't ever be executed
+			icondp->deleteTree(); icondp=NULL; iconstp=NULL;
+			// For simplicity, make expression that is not equal, and let later
+			// optimizations remove it
+			and1p = new AstConst(itemp->fileline(), V3Number(itemp->fileline(),1,0));
+			and2p = new AstConst(itemp->fileline(), V3Number(itemp->fileline(),1,1));
+		    } else if (iconstp && iconstp->num().isFourState()
+			       && (nodep->casex() || nodep->casez())) {
 			V3Number nummask (itemp->fileline(), iconstp->width());
 			nummask.opBitsNonX(iconstp->num());
 			V3Number numval  (itemp->fileline(), iconstp->width());
 			numval.opBitsOne(iconstp->num());
 			and1p = new AstAnd(itemp->fileline(), cexprp->cloneTree(false),
 					   new AstConst(itemp->fileline(), nummask));
-			and2p = new AstAnd(itemp->fileline(), 
+			and2p = new AstAnd(itemp->fileline(),
 					   new AstConst(itemp->fileline(), numval),
 					   new AstConst(itemp->fileline(), nummask));
+			icondp->deleteTree(); icondp=NULL; iconstp=NULL;
 		    } else {
 			// Not a caseX mask, we can simply build CASEEQ(cexpr icond)
 			and1p = cexprp->cloneTree(false);
@@ -323,6 +342,7 @@ private:
 		itemp->condsp(ifexprp);
 	    }
 	}
+	cexprp->deleteTree(); cexprp=NULL;
 	if (!hadDefault) {
 	    // If there was no default, add a empty one, this greatly simplifies below code
 	    // and constant propagation will just eliminate it for us later.
@@ -392,6 +412,17 @@ private:
 	}
     }
 
+    bool neverItem(AstCase* casep, AstConst* itemp) {
+	// Xs in case or casez are impossible due to two state simulations
+	if (casep->casex()) {
+	} else if (casep->casez()) {
+	    if (itemp->num().isUnknown()) return true;
+	} else {
+	    if (itemp->num().isFourState()) return true;
+	}
+	return false;
+    }
+
     // VISITORS
     virtual void visit(AstCase* nodep, AstNUser*) {
 	V3Case::caseLint(nodep);

src/V3Case.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Cast.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2004-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Cast's Transformations:
-//		
+//
 // Each module:
 //	For each math operator, if above operator requires 32 bits,
 //	and this isn't, cast to 32 bits.
@@ -44,8 +43,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -60,6 +59,7 @@ class CastVisitor : public AstNVisitor {
 private:
     // NODE STATE
     // Entire netlist:
+    //   AstNode::user()		// bool.  Indicates node is of known size
 
     // STATE
     //int debug() { return 9; }
@@ -76,6 +76,7 @@ private:
 	//if (debug()>8) castp->dumpTree(cout,"-castins: ");
 	//
 	insureLower32Cast(castp);
+	nodep->user(1);  // Now must be of known size
     }
     int castSize (AstNode* nodep) {
 	if (nodep->isQuad()) return VL_QUADSIZE;
@@ -84,7 +85,8 @@ private:
 	else return VL_WORDSIZE;
     }
     void insureCast(AstNode* nodep) {
-	if (castSize(nodep->backp()) != castSize(nodep)) {
+	if (castSize(nodep->backp()) != castSize(nodep)
+	    || !nodep->user()) {
 	    insertCast(nodep, castSize(nodep->backp()));
 	}
     }
@@ -102,15 +104,21 @@ private:
     // VISITORS
     virtual void visit(AstNodeUniop* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
+	nodep->user(nodep->lhsp()->user());
 	if (nodep->sizeMattersLhs()) insureCast(nodep->lhsp());
     }
     virtual void visit(AstNodeBiop* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
+	nodep->user(nodep->lhsp()->user()
+		    | nodep->rhsp()->user());
 	if (nodep->sizeMattersLhs()) insureCast(nodep->lhsp());
 	if (nodep->sizeMattersRhs()) insureCast(nodep->rhsp());
     }
     virtual void visit(AstNodeTriop* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
+	nodep->user(nodep->lhsp()->user()
+		    | nodep->rhsp()->user()
+		    | nodep->thsp()->user());
 	if (nodep->sizeMattersLhs()) insureCast(nodep->lhsp());
 	if (nodep->sizeMattersRhs()) insureCast(nodep->rhsp());
 	if (nodep->sizeMattersThs()) insureCast(nodep->thsp());
@@ -118,9 +126,11 @@ private:
     virtual void visit(AstCast* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	insureLower32Cast(nodep);
+	nodep->user(1);
     }
     virtual void visit(AstUnaryMin* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
+	nodep->user(nodep->lhsp()->user());
 	if (nodep->lhsp()->widthMin()==1) {
 	    // We want to avoid a GCC "converting of negative value" warning
 	    // from our expansion of
@@ -137,9 +147,16 @@ private:
 	    && nodep->backp()->width()
 	    && castSize(nodep) != castSize(nodep->varp())) {
 	    // Cast vars to IData first, else below has upper bits wrongly set
-	    //  CData x=3;  out = (QData)(x<<30); 
+	    //  CData x=3;  out = (QData)(x<<30);
 	    insertCast (nodep, castSize(nodep));
 	}
+	nodep->user(1);
+    }
+    virtual void visit(AstConst* nodep, AstNUser*) {
+	// Constants are of unknown size if smaller than 33 bits, becase
+	// we're too lazy to wrap every constant in the universe in
+	// ((IData)#).
+	nodep->user(nodep->isQuad() || nodep->isWide());
     }
 
     // NOPs
@@ -154,6 +171,7 @@ private:
 public:
     // CONSTUCTORS
     CastVisitor(AstNetlist* nodep) {
+	AstNode::userClearTree();
 	nodep->accept(*this);
     }
     virtual ~CastVisitor() {}

src/V3Cast.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2004-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Changed.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for changed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Changed's Transformations:
-//		
+//
 // Each module:
 //	Each combo block
 //	    For each variable that comes from combo block and is generated AFTER a usage
@@ -33,8 +32,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <set>

src/V3Changed.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Clean.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for clean nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Clean's Transformations:
-//		
+//
 // Each module:
 //	For each math operator, if it requires a clean operand,
 //	and the operand is dirty, insert a CLEAN node.
@@ -30,8 +29,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -55,7 +54,7 @@ private:
 
     // ENUMS
     enum CleanState { UNKNOWN, CLEAN, DIRTY };
-    
+
     // METHODS
     // Width resetting
     int  cppWidth(AstNode* nodep) {
@@ -196,6 +195,9 @@ private:
     virtual void visit(AstText* nodep, AstNUser*) {
 	setClean (nodep, true);
     }
+    virtual void visit(AstScopeName* nodep, AstNUser*) {
+	setClean (nodep, true);
+    }
     virtual void visit(AstSel* nodep, AstNUser*) {
 	operandTriop(nodep);
         setClean (nodep, nodep->cleanOut());

src/V3Clean.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Clock.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Clock's Transformations:
-//		
+//
 // Top Scope:
 //   Check created ACTIVEs
 //      Compress adjacent ACTIVEs with same sensitivity list
@@ -34,8 +33,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -245,12 +244,12 @@ private:
 	//UINFO(4," MOD   "<<nodep<<endl);
 	m_modp = nodep;
 	m_stableNum = 0;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
     }
     virtual void visit(AstScope* nodep, AstNUser*) {
 	//UINFO(4," SCOPE   "<<nodep<<endl);
 	m_scopep = nodep;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
 	if (AstNode* movep = nodep->finalClksp()) {
 	    if (!m_topScopep) nodep->v3fatalSrc("Final clocks under non-top scope");
 	    movep->unlinkFrBackWithNext();
@@ -416,7 +415,7 @@ private:
 					 new AstConst(fl, 1)));
         preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, countVarp, true),
 					 new AstConst(fl, 0)));
-	
+
 	// Add stable variables & preinits
 	AstNode* setChglastp = NULL;
 	for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) {

src/V3Clock.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Combine.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Combine's Transformations:
-//		
+//
 //	For every function that we spit out
 //	Examine code to find largest common blocks
 //	    Hash each node depth first
@@ -32,13 +31,13 @@
 //		Make new function
 //		Move common block to function
 //		Replace each common block ref with funccall
-//		
+//
 //*************************************************************************
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <vector>
@@ -392,7 +391,7 @@ private:
 	m_hashed.clear();
 	// Compute hash of all statement trees in the function
 	m_state = STATE_HASH;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
 	m_state = STATE_IDLE;
 	// Walk the hashes removing empty functions
 	if (emptyFunctionDeletion()) {

src/V3Combine.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Const.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Constant folding
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -27,8 +26,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 
@@ -39,18 +38,70 @@
 #include "V3Width.h"
 #include "V3Signed.h"
 
+//######################################################################
+// Utilities
+
+class ConstVarMarkVisitor : public AstNVisitor {
+    // NODE STATE
+    // AstVar::userp		-> bool, Var marked, 0=not set yet
+private:
+    // VISITORS
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (nodep->varp()) nodep->varp()->user(1);
+    }
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // CONSTUCTORS
+    ConstVarMarkVisitor(AstNode* nodep) {
+	AstNode::userClearTree();
+	nodep->iterateAndNext(*this, NULL);
+    }
+    virtual ~ConstVarMarkVisitor() {}
+};
+
+class ConstVarFindVisitor : public AstNVisitor {
+    // NODE STATE
+    // AstVar::userp		-> bool, input from ConstVarMarkVisitor
+    // MEMBERS
+    bool m_found;
+private:
+    // VISITORS
+    virtual void visit(AstVarRef* nodep, AstNUser*) {
+	if (nodep->varp() && nodep->varp()->user()) m_found = true;
+    }
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+public:
+    // CONSTUCTORS
+    ConstVarFindVisitor(AstNode* nodep) {
+	m_found = false;
+	nodep->iterateAndNext(*this, NULL);
+    }
+    virtual ~ConstVarFindVisitor() {}
+    // METHODS
+    bool found() const { return m_found; }
+};
+
 //######################################################################
 // Const state, as a visitor of each AstNode
 
 class ConstVisitor : public AstNVisitor {
 private:
+    // NODE STATE
+    // ** only when m_warn is set.  If state is needed other times,
+    // ** must track down everywhere V3Const is called and make sure no overlaps.
+    // AstVar::userp		-> Used by ConstVarMarkVisitor/ConstVarFindVisitor
+
     // STATE
     bool	m_params;	// If true, propogate parameterized and true numbers only
     bool	m_required;	// If true, must become a constant
     bool	m_wremove;	// Inside scope, no assignw removal
     bool	m_warn;		// Output warnings
     bool	m_cpp;		// C++ conversions only
-    AstModule*	m_modp;		// Current module	
+    AstModule*	m_modp;		// Current module
     AstNode*	m_scopep;	// Current scope
     //int debug() { return 9; }
 
@@ -91,7 +142,7 @@ private:
     }
     bool operandIsTwo(AstNode* nodep) {
 	return (nodep->castConst()
-		&& nodep->width() <= VL_QUADSIZE 
+		&& nodep->width() <= VL_QUADSIZE
 		&& nodep->castConst()->asQuad()==2);
     }
     bool operandIsTwostate(AstNode* nodep) {
@@ -384,6 +435,8 @@ private:
 	    int shift1 = shift1p->castConst()->asInt(); if (lhsp->castShiftR())  shift1=-shift1;
 	    int shift2 = shift2p->castConst()->asInt(); if (nodep->castShiftR()) shift2=-shift2;
 	    int newshift = shift1+shift2;
+	    shift1p->deleteTree(); shift1p=NULL;
+	    shift2p->deleteTree(); shift1p=NULL;
 	    AstNode* newp;
 	    V3Number mask1 (nodep->fileline(), nodep->width());
 	    V3Number ones (nodep->fileline(), nodep->width());
@@ -492,10 +545,26 @@ private:
 	    }
 	}
 	else if (!m_cpp && nodep->lhsp()->castConcat()) {
-	    UINFO(4,"  ASSI "<<nodep<<endl);
+	    bool need_temp = false;
+	    if (m_warn && !nodep->castAssignDly()) {  // Is same var on LHS and RHS?
+		ConstVarMarkVisitor mark(nodep->lhsp());
+		ConstVarFindVisitor find(nodep->rhsp());
+		if (find.found()) need_temp = true;
+	    }
+	    if (need_temp) {
+		// The first time we constify, there may be the same variable on the LHS
+		// and RHS.  In that case, we must use temporaries, or {a,b}={b,a} will break.
+		UINFO(4,"  ASSITEMP "<<nodep<<endl);
+		// ASSIGN(CONCAT(lc1,lc2),rhs) -> ASSIGN(temp1,SEL(rhs,{size})),
+		//				  ASSIGN(temp2,SEL(newrhs,{size}))
+		//                                ASSIGN(lc1,temp1),
+		//				  ASSIGN(lc2,temp2)
+	    } else {
+		UINFO(4,"  ASSI "<<nodep<<endl);
+		// ASSIGN(CONCAT(lc1,lc2),rhs) -> ASSIGN(lc1,SEL(rhs,{size})),
+		//				  ASSIGN(lc2,SEL(newrhs,{size}))
+	    }
 	    if (debug()>=9) nodep->dumpTree(cout,"  Ass_old: ");
-	    // ASSIGN(CONCAT(lc1,lc2),rhs) -> ASSIGN(lc1,SEL(rhs,{size})),
-	    //				      ASSIGN(lc2,SEL(newrhs,{size}))
 	    // Unlink the stuff
 	    AstNode*   lc1p    = nodep->lhsp()->castConcat()->lhsp()->unlinkFrBack();
 	    AstNode*   lc2p    = nodep->lhsp()->castConcat()->rhsp()->unlinkFrBack();
@@ -515,16 +584,53 @@ private:
 	    sel2p->width(msb2-lsb2+1,msb2-lsb2+1);
 	    // Make new assigns of same flavor as old one
 	    //*** Not cloneTree; just one node.
-	    AstNodeAssign* asn1p=nodep->cloneType(lc1p, sel1p)->castNodeAssign();
+	    AstNode* newp = NULL;
-	    AstNodeAssign* asn2p=nodep->cloneType(lc2p, sel2p)->castNodeAssign();
+	    if (!need_temp) {
-	    asn1p->width(msb1-lsb1+1,msb1-lsb1+1);
+		AstNodeAssign* asn1ap=nodep->cloneType(lc1p, sel1p)->castNodeAssign();
-	    asn2p->width(msb2-lsb2+1,msb2-lsb2+1);
+		AstNodeAssign* asn2ap=nodep->cloneType(lc2p, sel2p)->castNodeAssign();
-	    nodep->addNextHere(asn1p);
+		asn1ap->width(msb1-lsb1+1,msb1-lsb1+1);
-	    nodep->addNextHere(asn2p);
+		asn2ap->width(msb2-lsb2+1,msb2-lsb2+1);
-	    if (debug()>=9) asn1p->dumpTree(cout,"     _new: ");
+		newp = newp->addNext(asn1ap);
-	    if (debug()>=9) asn2p->dumpTree(cout,"     _new: ");
+		newp = newp->addNext(asn2ap);
+	    } else {
+		if (!m_modp) nodep->v3fatalSrc("Not under module");
+		// We could create just one temp variable, but we'll get better optimization
+		// if we make one per term.
+		string name1 = ((string)"__Vconcswap__"+cvtToStr(m_modp->varNumGetInc()));
+		string name2 = ((string)"__Vconcswap__"+cvtToStr(m_modp->varNumGetInc()));
+		AstVar* temp1p = new AstVar(sel1p->fileline(), AstVarType::BLOCKTEMP, name1,
+					    new AstRange(sel1p->fileline(), msb1-lsb1, 0));
+		AstVar* temp2p = new AstVar(sel2p->fileline(), AstVarType::BLOCKTEMP, name2,
+					    new AstRange(sel2p->fileline(), msb2-lsb2, 0));
+		m_modp->addStmtp(temp1p);
+		m_modp->addStmtp(temp2p);
+		AstNodeAssign* asn1ap=nodep->cloneType
+		    (new AstVarRef(sel1p->fileline(), temp1p, true),
+		     sel1p)->castNodeAssign();
+		AstNodeAssign* asn2ap=nodep->cloneType
+		    (new AstVarRef(sel2p->fileline(), temp2p, true),
+		     sel2p)->castNodeAssign();
+		AstNodeAssign* asn1bp=nodep->cloneType
+		    (lc1p, new AstVarRef(sel1p->fileline(), temp1p, false))
+		    ->castNodeAssign();
+		AstNodeAssign* asn2bp=nodep->cloneType
+		    (lc2p, new AstVarRef(sel2p->fileline(), temp2p, false))
+		    ->castNodeAssign();
+		asn1ap->width(msb1-lsb1+1,msb1-lsb1+1);
+		asn1bp->width(msb1-lsb1+1,msb1-lsb1+1);
+		asn2ap->width(msb2-lsb2+1,msb2-lsb2+1);
+		asn2bp->width(msb2-lsb2+1,msb2-lsb2+1);
+		// This order matters
+		newp = newp->addNext(asn1ap);
+		newp = newp->addNext(asn2ap);
+		newp = newp->addNext(asn1bp);
+		newp = newp->addNext(asn2bp);
+	    }
+	    if (debug()>=9) newp->dumpTreeAndNext(cout,"     _new: ");
+	    nodep->addNextHere(newp);
 	    // Cleanup
-	    nodep->unlinkFrBack()->deleteTree();
+	    nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
+	    conp->deleteTree(); conp=NULL;
 	    // Further reduce, either node may have more reductions.
 	    return true;
 	}
@@ -637,7 +743,8 @@ private:
 	    // If bp was a concat, then we have this exact same form again!
 	    // Recurse rather then calling node->iterate to prevent 2^n recursion!
 	    if (operandConcatMove(abConcp)) moveConcat(abConcp);
-	} else { 
+	    bcConcp->deleteTree(); bcConcp=NULL;
+	} else {
 	    AstConcat* abConcp = nodep->lhsp()->castConcat(); abConcp->unlinkFrBack();
 	    AstNode* ap = abConcp->lhsp()->unlinkFrBack();
 	    AstNode* bp = abConcp->rhsp()->unlinkFrBack();
@@ -647,6 +754,7 @@ private:
 	    nodep->lhsp(ap);
 	    nodep->rhsp(bcConcp);
 	    if (operandConcatMove(bcConcp)) moveConcat(bcConcp);
+	    abConcp->deleteTree(); abConcp=NULL;
 	}
     }
 
@@ -677,6 +785,8 @@ private:
 	if (lsb1p->castConst() && lsb2p->castConst()) {
 	    newlsbp = new AstConst(lsb1p->fileline(),
 				   lsb1p->castConst()->asInt() + lsb2p->castConst()->asInt());
+	    lsb1p->deleteTree(); lsb1p=NULL;
+	    lsb2p->deleteTree(); lsb2p=NULL;
 	} else {
 	    // Width is important, we need the width of the fromp's
 	    // expression, not the potentially smaller lsb1p's width
@@ -802,7 +912,12 @@ private:
 	if (nodep->sensp()->castConst()
 	    || (nodep->varrefp() && nodep->varrefp()->varp()->isParam())) {
 	    // Constants in sensitivity lists may be removed (we'll simplify later)
-	    AstSenItem* newp = new AstSenItem(nodep->fileline(), AstSenItem::Never());
+	    AstSenItem* newp;
+	    if (nodep->isClocked()) {  // A constant can never get a pos/negexge
+		newp = new AstSenItem(nodep->fileline(), AstSenItem::Never());
+	    } else {  // Otherwise it may compute a result that needs to settle out
+		newp = new AstSenItem(nodep->fileline(), AstSenItem::Combo());
+	    }
 	    nodep->replaceWith(newp);
 	    nodep->deleteTree(); nodep=NULL;
 	} else if (nodep->sensp()->castNot()) {
@@ -855,7 +970,7 @@ private:
 				 new AstAssign(nodep->fileline(),
 					       varrefp, exprp));
 	    m_modp->addStmtp(newinitp);
-	    nodep->unlinkFrBack();  nodep=NULL;
+	    nodep->unlinkFrBack()->deleteTree();  nodep=NULL;
 	    // Set the initial value right in the variable so we can constant propagate
 	    AstNode* initvaluep = exprp->cloneTree(false);
 	    varrefp->varp()->initp(initvaluep);
@@ -901,7 +1016,7 @@ private:
 		 && nodep->ifsp() && nodep->elsesp()) {
 	    UINFO(4,"IF(NOT {x})  => IF(x) swapped if/else"<<nodep<<endl);
 	    AstNode* condp = nodep->condp()->castNot()->lhsp()->unlinkFrBackWithNext();
-	    AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();	
+	    AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
 	    AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
 	    AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);
 	    ifp->branchPred(nodep->branchPred().invert());
@@ -922,7 +1037,7 @@ private:
 	    nodep->deleteTree(); nodep=NULL;
 	}
 	else if (0	// Disabled, as vpm assertions are faster without due to short-circuiting
-		 && operandIfIf(nodep)) {  
+		 && operandIfIf(nodep)) {
 	    UINFO(0,"IF({a}) IF({b}) => IF({a} && {b})"<<endl);
 	    AstNodeIf* lowerIfp = nodep->ifsp()->castNodeIf();
 	    AstNode* condp = nodep->condp()->unlinkFrBack();
@@ -938,6 +1053,63 @@ private:
 	}
     }
 
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	// Substitute constants into displays.  The main point of this is to
+	// simplify assertion methodologies which call functions with display's.
+	// This eliminates a pile of wide temps, and makes the C a whole lot more readable.
+	nodep->iterateChildren(*this);
+	bool anyconst = false;
+	for (AstNode* argp = nodep->exprsp(); argp; argp=argp->nextp()) {
+	    if (argp->castConst()) { anyconst=true; break; }
+	}
+	if (anyconst) {
+	    //UINFO(9,"  Display in  "<<nodep->text()<<endl);
+	    string dispout = "";
+	    string fmt = "";
+	    bool inPct = false;
+	    AstNode* argp = nodep->exprsp();
+	    for (const char* inp = nodep->text().c_str(); *inp; inp++) {
+		char ch = *inp;   // Breaks with iterators...
+		if (!inPct && ch=='%') {
+		    inPct = true;
+		    fmt = ch;
+		} else if (inPct && isdigit(ch)) {
+		    fmt += ch;
+		} else if (inPct) {
+		    inPct = false;
+		    fmt += ch;
+		    switch (tolower(ch)) {
+		    case '%': break;  // %% - just output a %
+		    case 'm': break;  // %m - auto insert "name"
+		    default:  // Most operators, just move to next argument
+			if (argp) {
+			    AstNode* nextp=argp->nextp();
+			    if (argp && argp->castConst()) { // Convert it
+				string out = argp->castConst()->num().displayed(fmt);
+				UINFO(9,"     DispConst: "<<fmt<<" -> "<<out<<"  for "<<argp<<endl);
+				{   // fmt = out w/ replace % with %% as it must be literal.
+				    fmt = "";
+				    for (string::iterator pos = out.begin(); pos != out.end(); pos++) {
+					if (*pos == '%') fmt += '%';
+					fmt += *pos;
+				    }
+				}
+				argp->unlinkFrBack()->deleteTree();
+			    }
+			    argp=nextp;
+			}
+			break;
+		    } // switch
+		    dispout += fmt;
+		} else {
+		    dispout += ch;
+		}
+	    }
+	    nodep->text(dispout);
+	    //UINFO(9,"  Display out "<<nodep->text()<<endl);
+	}
+    }
+
     virtual void visit(AstWhile* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->condp()->isZero()) {
@@ -954,7 +1126,7 @@ private:
     // Below lines are magic expressions processed by astgen
     //  "AstNODETYPE {             # bracket not paren
     //                $accessor_name, ...
-    //                             # ,, gets replaced with a , rather then &&
+    //                             # ,, gets replaced with a , rather than &&
     //	             }" 	   # bracket not paren
     //    ,"function to call"
     // or ,"AstREPLACEMENT_TYPE{ $accessor }"
@@ -1048,6 +1220,10 @@ private:
     TREEOP ("AstLogNot{$lhsp.castEqCase}",		"AstNeqCase{$lhsp->op1p(),$lhsp->op2p()}");
     TREEOPV("AstNot   {$lhsp.castNeqCase, $lhsp.width1}","AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
     TREEOP ("AstLogNot{$lhsp.castNeqCase}",		"AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
+    TREEOPV("AstNot   {$lhsp.castEqWild, $lhsp.width1}","AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
+    TREEOP ("AstLogNot{$lhsp.castEqWild}",		"AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
+    TREEOPV("AstNot   {$lhsp.castNeqWild, $lhsp.width1}","AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
+    TREEOP ("AstLogNot{$lhsp.castNeqWild}",		"AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
     TREEOPV("AstNot   {$lhsp.castEq, $lhsp.width1}",	"AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
     TREEOP ("AstLogNot{$lhsp.castEq}",			"AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
     TREEOPV("AstNot   {$lhsp.castNeq, $lhsp.width1}",	"AstEq  {$lhsp->op1p(),$lhsp->op2p()}");
@@ -1089,6 +1265,7 @@ private:
     TREEOP("AstXor    {operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
     TREEOP("AstEq     {operandsSame($lhsp,,$rhsp)}",	"replaceNum(nodep,1)");  // We let X==X -> 1, although in a true 4-state sim it's X.
     TREEOP("AstEqCase {operandsSame($lhsp,,$rhsp)}",	"replaceNum(nodep,1)");
+    TREEOP("AstEqWild {operandsSame($lhsp,,$rhsp)}",	"replaceNum(nodep,1)");
     TREEOP("AstGt     {operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
     TREEOP("AstGtS    {operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
     TREEOP("AstGte    {operandsSame($lhsp,,$rhsp)}",	"replaceNum(nodep,1)");
@@ -1099,6 +1276,7 @@ private:
     TREEOP("AstLteS   {operandsSame($lhsp,,$rhsp)}",	"replaceNum(nodep,1)");
     TREEOP("AstNeq    {operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
     TREEOP("AstNeqCase{operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
+    TREEOP("AstNeqWild{operandsSame($lhsp,,$rhsp)}",	"replaceZero(nodep)");
     TREEOP("AstLogAnd {operandsSame($lhsp,,$rhsp), $lhsp.width1}",	"replaceWLhs(nodep)");
     TREEOP("AstLogOr  {operandsSame($lhsp,,$rhsp), $lhsp.width1}",	"replaceWLhs(nodep)");
     ///=== Verilog operators
@@ -1129,7 +1307,7 @@ private:
     TREEOPV("AstRedXor{$lhsp->castExtend()}",	"AstRedXor{$lhsp->castExtend()->lhsp()}");
     TREEOPV("AstOneHot{$lhsp.width1}",		"replaceWLhs(nodep)");
     TREEOPV("AstOneHot0{$lhsp.width1}",		"replaceNum(nodep,1)");
-    // Binary AND/OR is faster then logical and/or (usually)
+    // Binary AND/OR is faster than logical and/or (usually)
     TREEOPV("AstLogAnd{$lhsp.width1, $rhsp.width1}", "AstAnd{$lhsp,$rhsp}");
     TREEOPV("AstLogOr {$lhsp.width1, $rhsp.width1}", "AstOr{$lhsp,$rhsp}");
     TREEOPV("AstLogNot{$lhsp.width1}",		    "AstNot{$lhsp}");

src/V3Const.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Propagate constants across AST
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Coverage.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Netlist (top level) functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -31,8 +30,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 
@@ -53,7 +52,7 @@ private:
     bool	m_checkBlock;	// Should this block get covered?
     AstModule*	m_modp;		// Current module to add statement to
     FileMap	m_fileps;	// Column counts for each fileline
-   
+
     //int debug() { return 9; }
 
     // METHODS
@@ -66,7 +65,7 @@ private:
 	    column = (it->second)++;
 	}
 
-	AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment); 
+	AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment);
 	m_modp->addStmtp(declp);
 
 	return new AstCoverInc(fl, declp);

src/V3Coverage.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Coverage modules/signals together
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Dead.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead code elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,13 +20,13 @@
 // DEAD TRANSFORMATIONS:
 //	Remove any unreferenced modules
 //	Remove any unreferenced variables
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <vector>
 #include <map>

src/V3Dead.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead branch elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Delayed.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,9 +18,9 @@
 //
 //*************************************************************************
 // V3Delayed's Transformations:
-//		
+//
 // Each module:
-//	Replace ASSIGNDLY var, exp 
+//	Replace ASSIGNDLY var, exp
 //	    With   ASSIGNDLY newvar, exp
 //	    At top of block:  VAR  newvar
 //	    At bottom of block: ASSIGNW var newvar
@@ -54,8 +53,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <map>
@@ -110,18 +109,6 @@ private:
     }
     AstVarScope* createVarSc(AstVarScope* oldvarscp, string name, int width/*0==fromoldvar*/) {
 	// Because we've already scoped it, we may need to add both the AstVar and the AstVarScope
-	AstRange* rangep = NULL;
-	if (width==0) {
-	    rangep = new AstRange(oldvarscp->fileline(),
-				  oldvarscp->varp()->msb(),
-				  oldvarscp->varp()->lsb());
-	} else if (width==1) {
-	    rangep = NULL;
-	} else {
-	    rangep = new AstRange(oldvarscp->fileline(),
-				  width-1, 0);
-	}
-
 	if (!oldvarscp->scopep()) oldvarscp->v3fatalSrc("Var unscoped");
 	AstVar* varp;
 	AstModule* addmodp = oldvarscp->scopep()->modp();
@@ -131,6 +118,17 @@ private:
 	    // Created module's AstVar earlier under some other scope
 	    varp = iter->second;
 	} else {
+	    AstRange* rangep = NULL;
+	    if (width==0) {
+		rangep = new AstRange(oldvarscp->fileline(),
+				      oldvarscp->varp()->msb(),
+				      oldvarscp->varp()->lsb());
+	    } else if (width==1) {
+		rangep = NULL;
+	    } else {
+		rangep = new AstRange(oldvarscp->fileline(),
+				      width-1, 0);
+	    }
 	    varp = new AstVar (oldvarscp->fileline(), AstVarType::BLOCKTEMP, name, rangep);
 	    if (width==0) varp->widthSignedFrom(oldvarscp);
 	    addmodp->addStmtp(varp);
@@ -226,7 +224,7 @@ private:
 
 	if (nodep->user5p()) {
 	    // Simplistic optimization.  If the previous statement in same scope was also a =>,
-	    // then we told this nodep->user5 we can use its Vdlyvset rather then making a new one.
+	    // then we told this nodep->user5 we can use its Vdlyvset rather than making a new one.
 	    // This is good for code like:
 	    //    for (i=0; i<5; i++)  vector[i] <= something;
 	    sharedVset = true;
@@ -270,7 +268,7 @@ private:
 	AstAlwaysPost* finalp = varrefp->varScopep()->user4p()->castNode()->castAlwaysPost();
 	if (!finalp) {
 	    finalp = new AstAlwaysPost(nodep->fileline(), NULL/*sens*/, NULL/*body*/);
-	    UINFO(9,"     Created "<<finalp<<endl); 
+	    UINFO(9,"     Created "<<finalp<<endl);
 	    m_activep->addStmtsp(finalp);
 	    varrefp->varScopep()->user4p(finalp);
 	}
@@ -285,7 +283,7 @@ private:
 				    new AstVarRef(nodep->fileline(), setvscp, false),
 				    NULL,
 				    NULL);
-	    UINFO(9,"     Created "<<postLogicp<<endl); 
+	    UINFO(9,"     Created "<<postLogicp<<endl);
 	    finalp->addBodysp(postLogicp);
 	    finalp->user5p(setvscp);	// Remember IF's vset variable
 	    finalp->user4p(postLogicp);	// and the associated IF, as we may be able to reuse it
@@ -348,7 +346,7 @@ private:
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	if (!nodep->user2()) {  // Not done yet
 	    nodep->user2(true);
-	    
+
 	    if (m_inDly && nodep->lvalue()) {
 		UINFO(4,"AssignDlyVar: "<<nodep<<endl);
 		markVarUsage(nodep->varp(), VU_DLY);
@@ -402,7 +400,7 @@ private:
 							m_activep->sensesp());
 		    newactp->addStmtsp(prep);	// Add to FRONT of statements
 		    newactp->addStmtsp(postp);
-		    m_activep->addNext(newactp);					
+		    m_activep->addNext(newactp);
 		    dlyvscp->user2p(newactp);
 		}
 		AstVarRef* newrefp = new AstVarRef(nodep->fileline(), dlyvscp, true);

src/V3Delayed.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Depth.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Depth's Transformations:
-//		
+//
 // Each module:
 //	For each wide OP, assign a temporary variable.
 //	For each deep expression, assign expression to temporary.
@@ -30,8 +29,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -111,7 +110,7 @@ private:
 	// We have some operator defines that use 2 parens, so += 2.
 	m_depth += 2;
 	if (m_depth>m_maxdepth) m_maxdepth=m_depth;
-	nodep->iterateChildren(*this); 
+	nodep->iterateChildren(*this);
 	m_depth -= 2;
 
 	if (m_stmtp

src/V3Depth.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3DepthBlock.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3DepthBlock's Transformations:
-//		
+//
 // Each module:
 //	For each deep block, create cfunc including that block.
 //
@@ -27,8 +26,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 

src/V3DepthBlock.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Descope.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -24,13 +23,13 @@
 //		Change varref name() to be relative to current module
 //		Remove varScopep()
 //	    This allows for better V3Combine'ing.
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <map>
 

src/V3Descope.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3EmitC.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,10 +20,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
-#include <math.h>
+#include <cmath>
 #include <map>
 #include <vector>
 #include <algorithm>
@@ -79,10 +78,10 @@ public:
     //int debug() { return 9; }
 
     // METHODS
-    void displayEmit(AstDisplay* nodep);
+    void displayNode(AstNode* nodep, const string& vformat, AstNode* exprsp, bool isScan);
-    string displayFormat(AstNode* widthNode, string in, 
+    void displayEmit(AstNode* nodep, bool isScan);
-			 char fmtLetter, bool padZero, bool reallyString);
+    void displayArg(AstNode* dispp, AstNode** elistp, bool isScan,
-    void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter); 
+		    string vfmt, char fmtLetter);
 
     void emitVarDecl(AstVar* nodep, const string& prefixIfImp);
     typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_STATIC, EVL_ALL} EisWhich;
@@ -92,7 +91,8 @@ public:
     void emitIQW(AstNode* nodep) {
 	puts (nodep->isWide()?"W":(nodep->isQuad()?"Q":"I"));
     }
-    void emitOpName(AstNode* nodep, const string& name);
+    void emitOpName(AstNode* nodep, const string& format,
+		    AstNode* lhsp, AstNode* rhsp, AstNode* thsp);
 
     string cFuncArgs(AstCFunc* nodep) {
 	// Return argument list for given C function
@@ -212,7 +212,7 @@ public:
     }
     virtual void visit(AstCoverDecl* nodep, AstNUser*) {
 	puts("__vlCoverInsert(");	// As Declared in emitCoverageDecl
-	puts("&__Vcoverage["); 	
+	puts("&__Vcoverage[");
 	puts(cvtToStr(m_coverIds.remap(nodep))); puts("]");
 	puts(", \"");	puts(nodep->fileline()->filebasename()); puts("\"");
 	puts(", ");	puts(cvtToStr(nodep->fileline()->lineno()));
@@ -231,7 +231,23 @@ public:
 	nodep->lhsp()->iterateAndNext(*this);
 	puts(");\n");
     }
-    virtual void visit(AstDisplay* nodep, AstNUser*);  // BELOW
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	string text = nodep->text();
+	if (nodep->addNewline()) text += "\\n";
+	displayNode(nodep, text, nodep->exprsp(), false);
+    }
+    virtual void visit(AstFScanF* nodep, AstNUser*) {
+	displayNode(nodep, nodep->text(), nodep->exprsp(), true);
+    }
+    virtual void visit(AstSScanF* nodep, AstNUser*) {
+	displayNode(nodep, nodep->text(), nodep->exprsp(), true);
+    }
+
+    void checkMaxWords(AstNode* nodep) {
+	if (nodep->widthWords() > VL_TO_STRING_MAX_WORDS) {
+	    nodep->v3error("String of "<<nodep->width()<<" bits exceeds hardcoded limit VL_TO_STRING_MAX_WORDS in verilatedos.h\n");
+	}
+    }
     virtual void visit(AstFOpen* nodep, AstNUser*) {
 	nodep->filep()->iterateAndNext(*this);
 	puts(" = VL_FOPEN_");
@@ -243,9 +259,7 @@ public:
 	    puts(cvtToStr(nodep->filenamep()->widthWords()));
 	    putbs(", ");
 	}
-	if (nodep->filenamep()->widthWords() > VL_TO_STRING_MAX_WORDS) {
+	checkMaxWords(nodep->filenamep());
-	    nodep->v3error("String of "<<nodep->filenamep()->width()<<" bits exceeds hardcoded limit VL_TO_STRING_MAX_WORDS in verilatedos.h\n");
-	}
 	nodep->filenamep()->iterateAndNext(*this);
 	putbs(", ");
 	nodep->modep()->iterateAndNext(*this);
@@ -254,7 +268,7 @@ public:
     virtual void visit(AstReadMem* nodep, AstNUser*) {
 	puts("VL_READMEM_");
 	emitIQW(nodep->filenamep());
-	puts(" (");  // We take a void* rather then emitIQW(nodep->memp());
+	puts(" (");  // We take a void* rather than emitIQW(nodep->memp());
 	puts(nodep->isHex()?"true":"false");
 	putbs(",");
 	puts(cvtToStr(nodep->memp()->widthMin()));  // Need real storage width
@@ -272,9 +286,7 @@ public:
 	puts(cvtToStr(array_lsb));
 	putbs(",");
 	puts(cvtToStr(nodep->filenamep()->widthWords()));
-	if (nodep->filenamep()->widthWords() > VL_TO_STRING_MAX_WORDS) {
+	checkMaxWords(nodep->filenamep());
-	    nodep->v3error("String of "<<nodep->filenamep()->width()<<" bits exceeds hardcoded limit VL_TO_STRING_MAX_WORDS in verilatedos.h\n");
-	}
 	putbs(", ");
 	nodep->filenamep()->iterateAndNext(*this);
 	putbs(", ");
@@ -293,6 +305,17 @@ public:
 	nodep->filep()->iterateAndNext(*this);	// For saftey, so user doesn't later WRITE with it.
 	puts("=0; }\n");
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	if (!nodep->filep()) {
+	    puts("fflush (stdout);\n");
+	} else {
+	    puts("if (");
+	    nodep->filep()->iterateAndNext(*this);
+	    puts(") { fflush (VL_CVT_Q_FP(");
+	    nodep->filep()->iterateAndNext(*this);
+	    puts(")); }\n");
+	}
+    }
     virtual void visit(AstWhile* nodep, AstNUser*) {
 	nodep->precondsp()->iterateAndNext(*this);
 	puts("while (");
@@ -354,26 +377,24 @@ public:
 
     // Operators
     virtual void visit(AstNodeTermop* nodep, AstNUser*) {
-	emitOpName(nodep,nodep->emitOperator());
+	emitOpName(nodep, nodep->emitC(), NULL, NULL, NULL);
-	puts(")");
     }
     virtual void visit(AstNodeUniop* nodep, AstNUser*) {
 	if (emitSimpleOk(nodep)) {
 	    putbs("("); puts(nodep->emitSimpleOperator()); puts(" ");
+	    nodep->lhsp()->iterateAndNext(*this); puts(")");
 	} else {
-	    emitOpName(nodep,nodep->emitOperator());
+	    emitOpName(nodep, nodep->emitC(), nodep->lhsp(), NULL, NULL);
 	}
-	nodep->lhsp()->iterateAndNext(*this); puts(")");
     }
     virtual void visit(AstNodeBiop* nodep, AstNUser*) {
 	if (emitSimpleOk(nodep)) {
 	    putbs("("); nodep->lhsp()->iterateAndNext(*this);
 	    puts(" "); putbs(nodep->emitSimpleOperator()); puts(" ");
+	    nodep->rhsp()->iterateAndNext(*this); puts(")");
 	} else {
-	    emitOpName(nodep,nodep->emitOperator());
+	    emitOpName(nodep, nodep->emitC(), nodep->lhsp(), nodep->rhsp(), NULL);
-	    nodep->lhsp()->iterateAndNext(*this); puts(", ");
 	}
-	nodep->rhsp()->iterateAndNext(*this); puts(")");
     }
     virtual void visit(AstRedXor* nodep, AstNUser* vup) {
 	if (nodep->lhsp()->isWide()) {
@@ -388,7 +409,7 @@ public:
     }
     virtual void visit(AstMulS* nodep, AstNUser* vup) {
 	if (nodep->widthWords() > VL_MULS_MAX_WORDS) {
-	    nodep->v3error("Signed multiply of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h\n");
+	    nodep->v3error("Unsupported: Signed multiply of "<<nodep->width()<<" bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h\n");
 	}
 	visit(nodep->castNodeBiop(), vup);
     }
@@ -405,10 +426,7 @@ public:
     virtual void visit(AstNodeCond* nodep, AstNUser*) {
 	// Widths match up already, so we'll just use C++'s operator w/o any temps.
 	if (nodep->expr1p()->isWide()) {
-	    emitOpName(nodep,nodep->emitOperator());
+	    emitOpName(nodep, nodep->emitC(), nodep->condp(), nodep->expr1p(), nodep->expr2p());
-	    nodep->condp()->iterateAndNext(*this); puts(", ");
-	    nodep->expr1p()->iterateAndNext(*this); puts(", ");
-	    nodep->expr2p()->iterateAndNext(*this); puts(")");
 	} else {
 	    putbs("(");
 	    nodep->condp()->iterateAndNext(*this); putbs(" ? ");
@@ -418,16 +436,7 @@ public:
     }
     virtual void visit(AstSel* nodep, AstNUser*) {
 	// Note ASSIGN checks for this on a LHS
-	if (nodep->widthp()->isOne()) {
+	emitOpName(nodep, nodep->emitC(), nodep->fromp(), nodep->lsbp(), nodep->thsp());
-	    emitOpName(nodep,"VL_BITSEL");
-	    nodep->fromp()->iterateAndNext(*this); puts(", ");
-	    nodep->lsbp()->iterateAndNext(*this); puts(")");
-	} else {
-	    emitOpName(nodep,"VL_SEL");
-	    nodep->fromp()->iterateAndNext(*this); puts(", ");
-	    nodep->lsbp()->iterateAndNext(*this); puts(", ");
-	    nodep->widthp()->iterateAndNext(*this); puts(")");
-	}
     }
     virtual void visit(AstReplicate* nodep, AstNUser*) {
 	if (nodep->lhsp()->widthMin() == 1 && !nodep->isWide()) {
@@ -441,24 +450,16 @@ public:
 	    if (nodep->lhsp()) { puts(","+cvtToStr(nodep->lhsp()->widthMin())); }
 	    if (nodep->rhsp()) { puts(","+cvtToStr(nodep->rhsp()->widthMin())); }
 	    puts(",");
+	    nodep->lhsp()->iterateAndNext(*this); puts(", ");
+	    nodep->rhsp()->iterateAndNext(*this); puts(")");
 	} else {
-	    emitOpName(nodep,nodep->emitOperator());
+	    emitOpName(nodep, nodep->emitC(), nodep->lhsp(), nodep->rhsp(), NULL);
 	}
-	nodep->lhsp()->iterateAndNext(*this); puts(", ");
-	nodep->rhsp()->iterateAndNext(*this); puts(")");
-    }
-    virtual void visit(AstArraySel* nodep, AstNUser*) {
-	nodep->fromp()->iterateAndNext(*this); putbs("[");
-	nodep->bitp()->iterateAndNext(*this); puts("]");
-    }
-    virtual void visit(AstWordSel* nodep, AstNUser*) {
-	nodep->fromp()->iterateAndNext(*this); puts("["); // Not putbs, as usually it's a small constant next
-	nodep->bitp()->iterateAndNext(*this); puts("]");
     }
     // Terminals
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	puts(nodep->hiername());
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     void emitConstant(AstConst* nodep, AstVarRef* assigntop, const string& assignString) {
 	// Put out constant set to the specified variable, or given variable in a string
@@ -639,7 +640,7 @@ class EmitCImp : EmitCStmts {
 	puts(modClassName(m_modp)+"::"+nodep->name()
 	     +"("+cFuncArgs(nodep)+") {\n");
 
-	puts("VL_DEBUG_IF(cout<<\"  "); 
+	puts("VL_DEBUG_IF(cout<<\"  ");
 	for (int i=0;i<m_modp->level();i++) { puts("  "); }
 	puts(modClassName(m_modp)+"::"+nodep->name()
 	     +"\"<<endl; );\n");
@@ -853,33 +854,95 @@ bool EmitCStmts::emitSimpleOk(AstNodeMath* nodep) {
     return true;
 }
 
-void EmitCStmts::emitOpName(AstNode* nodep, const string& opname) {
+void EmitCStmts::emitOpName(AstNode* nodep, const string& format,
-    putbs(opname+"_");
+			    AstNode* lhsp, AstNode* rhsp, AstNode* thsp) {
-    if (nodep->emitWordForm()) {
+    // Look at emitOperator() format for term/uni/dual/triops,
-	emitIQW(nodep->op1p());
+    // and write out appropriate text.
-	puts("(");
+    //  %n*	node
-	if (nodep->op1p()->isWide()) {
+    //   %nq	  emitIQW on the [node]
-	    puts(cvtToStr(nodep->op1p()->widthWords()));
+    //   %nw	  width in bits
-	    puts(", ");
+    //   %nW	  width in words
+    //   %ni	  iterate
+    //	%l*	lhsp - if appropriate, then second char as above
+    //	%r*	rhsp - if appropriate, then second char as above
+    //	%t*	thsp - if appropriate, then second char as above
+    //	%k	Potential line break
+    //  %P	Wide temporary name
+    //	,	Commas suppressed if the previous field is suppressed
+    string nextComma;
+    bool needComma = false;
+#define COMMA { if (nextComma!="") { puts(nextComma); nextComma=""; } }
+
+    putbs("");
+    for (string::const_iterator pos = format.begin(); pos != format.end(); ++pos) {
+	if (pos[0]==',') {
+	    // Remember we need to add one, but don't do yet to avoid ",)"
+	    if (needComma) {
+		if (pos[1]==' ') { nextComma=", "; }
+		else nextComma = ",";
+		needComma = false;
+	    }
+	    if (pos[1]==' ') { ++pos; } // Must do even if no nextComma
+	}
+	else if (pos[0]=='%') {
+	    ++pos;
+	    bool detail = false;
+	    AstNode* detailp = NULL;
+	    switch (pos[0]) {
+	    case '%': puts("%");  break;
+	    case 'k': putbs("");  break;
+	    case 'n': detail = true; detailp = nodep; break;
+	    case 'l': detail = true; detailp = lhsp; break;
+	    case 'r': detail = true; detailp = rhsp; break;
+	    case 't': detail = true; detailp = thsp; break;
+	    case 'P':
+		if (nodep->isWide()) {
+		    if (!m_wideTempRefp) nodep->v3fatalSrc("Wide Op w/ no temp, perhaps missing op in V3EmitC?");
+		    COMMA;
+		    puts(m_wideTempRefp->hiername());
+		    puts(m_wideTempRefp->varp()->name());
+		    m_wideTempRefp = NULL;
+		    needComma = true;
+		}
+		break;
+	    default:
+		nodep->v3fatalSrc("Unknown emitOperator format code: %"<<pos[0]);
+		break;
+	    }
+	    if (detail) {
+		// Get next letter of %[nlrt]
+		++pos;
+		switch (pos[0]) {
+		case 'q': emitIQW(detailp); break;
+		case 'w': 
+		    COMMA;
+		    puts(cvtToStr(detailp->widthMin()));
+		    needComma = true;
+		    break;
+		case 'W':
+		    if (lhsp->isWide()) {
+			COMMA;
+			puts(cvtToStr(lhsp->widthWords()));
+			needComma = true;
+		    }
+		    break;
+		case 'i':
+		    COMMA;
+		    if (!detailp) { nodep->v3fatalSrc("emitOperator() references undef node"); }
+		    else detailp->iterateAndNext(*this);
+		    needComma = true;
+		    break;
+		default:
+		    nodep->v3fatalSrc("Unknown emitOperator format code: %[nlrt]"<<pos[0]);
+		    break;
+		}
+	    }
+	} else {
+	    // Normal text
+	    if (pos[0] == ')') nextComma="";
+	    COMMA;
+	    string s; s+=pos[0]; puts(s);
 	}
-    } else {
-	emitIQW(nodep);
-	if (nodep->op1p()) { emitIQW(nodep->op1p()); }
-	if (nodep->op2p()) { emitIQW(nodep->op2p()); }
-	if (nodep->op3p()) { emitIQW(nodep->op3p()); }
-	puts("(");
-	puts(cvtToStr(nodep->widthMin()));
-	if (nodep->op1p()) { puts(","+cvtToStr(nodep->op1p()->widthMin())); }
-	if (nodep->op2p()) { puts(","+cvtToStr(nodep->op2p()->widthMin())); }
-	if (nodep->op3p()) { puts(","+cvtToStr(nodep->op3p()->widthMin())); }
-	if (nodep->op1p() || nodep->isWide()) puts(", ");
-    }
-    if (nodep->isWide()) {
-	if (!m_wideTempRefp) nodep->v3fatalSrc("Wide Op w/ no temp, perhaps missing op in V3EmitC?");
-	puts(m_wideTempRefp->hiername());
-	puts(m_wideTempRefp->varp()->name());
-	m_wideTempRefp = NULL;
-	if (nodep->op1p()) puts(", ");
     }
 }
 
@@ -889,13 +952,11 @@ void EmitCStmts::emitOpName(AstNode* nodep, const string& opname) {
 // We only do one display at once, so can just use static state
 
 struct EmitDispState {
-    bool		m_wide;		// Put out a wide func that needs string buffer
     string		m_format;	// "%s" and text from user
     vector<AstNode*>	m_argsp;	// Each argument to be printed
     vector<string>	m_argsFunc;	// Function before each argument to be printed
     EmitDispState() { clear(); }
     void clear() {
-	m_wide = false;
 	m_format = "";
 	m_argsp.clear();
 	m_argsFunc.clear();
@@ -907,18 +968,40 @@ struct EmitDispState {
     }
 } emitDispState;
 
-void EmitCStmts::displayEmit(AstDisplay* nodep) {
+void EmitCStmts::displayEmit(AstNode* nodep, bool isScan) {
-    if (emitDispState.m_format != "") {
+    if (emitDispState.m_format == ""
+	&& nodep->castDisplay()) { // not fscanf etc, as they need to return value
+	// NOP
+    } else {
 	// Format
-	if (nodep->filep()) {
+	bool isStmt;
-	    puts("if (");
+	if (AstFScanF* dispp = nodep->castFScanF()) {
-	    nodep->filep()->iterate(*this);	// Check if closed, to avoid core dump
+	    isStmt = false;
-	    puts(") fprintf(VL_CVT_Q_FP(");
+	    puts("VL_FSCANF_IX(");
-	    nodep->filep()->iterate(*this);
+	    dispp->filep()->iterate(*this);
-	    puts("),\"");
+	    puts(",");
+	} else if (AstSScanF* dispp = nodep->castSScanF()) {
+	    isStmt = false;
+	    checkMaxWords(dispp->fromp());
+	    puts("VL_SSCANF_I"); emitIQW(dispp->fromp()); puts("X(");
+	    puts(cvtToStr(dispp->fromp()->widthMin()));
+	    puts(",");
+	    dispp->fromp()->iterate(*this);
+	    puts(",");
+	} else if (AstDisplay* dispp = nodep->castDisplay()) {
+	    isStmt = true;
+	    if (dispp->filep()) {
+		puts("VL_FWRITEF(");
+		dispp->filep()->iterate(*this);
+		puts(",");
+	    } else {
+		puts("VL_WRITEF(");
+	    }
 	} else {
-	    puts("VL_PRINTF(\"");
+	    isStmt = true;
+	    nodep->v3fatalSrc("Unknown displayEmit node type");
 	}
+	puts("\"");
 	ofp()->putsNoTracking(emitDispState.m_format);
 	puts("\"");
 	// Arguments
@@ -929,161 +1012,133 @@ void EmitCStmts::displayEmit(AstDisplay* nodep) {
 	    ofp()->indentInc();
 	    ofp()->putbs("");
 	    if (func!="") puts(func);
-	    if (argp) argp->iterate(*this);
+	    if (argp) {
-	    if (func!="") puts(")");
+		if (isScan) puts("&(");
+		argp->iterate(*this);
+		if (isScan) puts(")");
+	    }
 	    ofp()->indentDec();
 	}
         // End
-	puts(");\n");
+	puts(")");
+	if (isStmt) puts(";\n");
+	else puts(" ");
 	// Prep for next
 	emitDispState.clear();
     }
 }
 
-string EmitCStmts::displayFormat(AstNode* widthNodep, string in,
+void EmitCStmts::displayArg(AstNode* dispp, AstNode** elistp, bool isScan,
-				 char fmtLetter, bool padZero, bool reallyString) {
+			    string vfmt, char fmtLetter) {
-    if (fmtLetter=='s') padZero = false;
-    if (widthNodep && widthNodep->isWide()
-	&& (fmtLetter=='d'||fmtLetter=='u')) {
-	widthNodep->v3error("Unsupported: $display of dec format of > 64 bit results (use hex format instead)");
-    }
-    if (widthNodep && widthNodep->widthMin()>8 && fmtLetter=='c') {
-	widthNodep->v3error("$display of char format of > 8 bit result");
-    }
-    string fmt;
-    if (in == "") {
-	// Size naturally
-	if (widthNodep == NULL) fmt="";  // Out of args, will get error
-	if (fmtLetter=='u' || fmtLetter=='d') { // Decimal.  Spec says leading spaces, not zeros
-	    double mantissabits = widthNodep->widthMin() - ((fmtLetter=='d')?1:0);
-	    double maxval = pow(2.0, mantissabits);
-	    double dchars = log10(maxval)+1.0;
-	    if (fmtLetter=='d') dchars++;  // space for sign
-	    int nchars = int(dchars);
-	    fmt=cvtToStr(nchars);
-	} else if (fmtLetter!='s' && fmtLetter!='c') {  // Strings/chars don't get padding
-	    int bitsPerChar = (fmtLetter=='b'?1 : fmtLetter=='o'?3 : 4);
-	    int nchars = (widthNodep->widthMin() + bitsPerChar-1)/bitsPerChar;
-	    if (padZero) fmt=(string)("0")+cvtToStr(nchars);
-	    else fmt=cvtToStr(nchars);
-	}
-    } else if (in == "0") {
-	fmt="";	// No width
-    } else {
-	fmt=in;
-    }
-    return fmt;
-}
-
-void EmitCStmts::displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter) {
     // Print display argument, edits elistp
-    if (!*elistp) {
+    AstNode* argp = *elistp;
-	dispp->v3error("Missing arguments for $display format");
+    if (!argp) {
+	// expectDisplay() checks this first, so internal error if found here
+	dispp->v3error("Internal: Missing arguments for $display format");
 	return;
     }
-    if ((*elistp)->widthMin() > VL_VALUE_STRING_MAX_WIDTH) {
+    if (argp->widthMin() > VL_VALUE_STRING_MAX_WIDTH) {
 	dispp->v3error("Exceeded limit of 1024 bits for any display arguments");
     }
-
+    if (argp && argp->isWide()
-    if ((*elistp)->isWide()	// Have to use our own function for wide,
+	&& (fmtLetter=='d'||fmtLetter=='u')) {
-	|| fmtLetter=='s'	// ... Verilog strings
+	argp->v3error("Unsupported: "<<dispp->verilogKwd()<<" of dec format of > 64 bit results (use hex format instead)");
-	|| fmtLetter=='b'	// ... binary, no printf %b in C
-	|| fmtLetter=='d') {	// ... Signed decimal
-	// We use a single static string, so must only have one call per VL_PRINT
-	if (emitDispState.m_wide) { displayEmit(dispp); }
-	emitDispState.m_wide = true;
-	string nfmt = displayFormat(*elistp, fmt, fmtLetter, false, true);
-	string pfmt = "%"+nfmt+"s";
-	string func = "VL_VALUE_FORMATTED_";
-	func += ((*elistp)->isWide()) ? "W(" : ((*elistp)->isQuad()) ? "Q(" : "I(";
-	func += (cvtToStr((*elistp)->widthMin())
-		 +",'"+fmtLetter+"'"
-		 +","+(fmt=="0"?"true":"false")+",");
-	emitDispState.pushFormat(pfmt);
-	emitDispState.pushArg(*elistp,func);
-    } else {
-	string func;
-	string nfmt = displayFormat(*elistp, fmt, fmtLetter, true, false);
-	// We don't need to check for fmtLetter=='d', as it is above.
-	if ((*elistp)->isQuad() && (fmtLetter=='u'||fmtLetter=='o'||fmtLetter=='x')) {
-	    nfmt+="ll";
-	    func="(unsigned long long)(";  // Must match %ull to avoid warnings
-	}
-	string pfmt = "%"+nfmt+fmtLetter;
-
-	emitDispState.pushFormat(pfmt);
-	emitDispState.pushArg(*elistp,func);
     }
+    if (argp && argp->widthMin()>8 && fmtLetter=='c') {
+	// Technically legal, but surely not what the user intended.
+	argp->v3error(dispp->verilogKwd()<<" of char format of > 8 bit result");
+    }
+
+    //string pfmt = "%"+displayFormat(argp, vfmt, fmtLetter)+fmtLetter;
+    string pfmt;
+    if ((fmtLetter=='u' || fmtLetter=='d')
+	&& !isScan
+	&& vfmt == "") { // Size decimal output.  Spec says leading spaces, not zeros
+	double mantissabits = argp->widthMin() - ((fmtLetter=='d')?1:0);
+	double maxval = pow(2.0, mantissabits);
+	double dchars = log10(maxval)+1.0;
+	if (fmtLetter=='d') dchars++;  // space for sign
+	int nchars = int(dchars);
+	pfmt = string("%") + cvtToStr(nchars) + fmtLetter;
+    } else {
+	pfmt = string("%") + vfmt + fmtLetter;
+    }
+    emitDispState.pushFormat(pfmt);
+    emitDispState.pushArg(NULL,cvtToStr(argp->widthMin()));
+    emitDispState.pushArg(argp,"");
+
     // Next parameter
     *elistp = (*elistp)->nextp();
 }
 
-void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
+void EmitCStmts::displayNode(AstNode* nodep, const string& vformat, AstNode* exprsp,
-    string vformat = nodep->text();
+			     bool isScan) {
-    AstNode* elistp = nodep->exprsp();
+    AstNode* elistp = exprsp;
 
     // Convert Verilog display to C printf formats
     // 		"%0t" becomes "%d"
     emitDispState.clear();
-    string fmt = "";
+    string vfmt = "";
-    string::iterator pos = vformat.begin();
+    string::const_iterator pos = vformat.begin();
-    if (*pos == '"') pos++;
     bool inPct = false;
     for (; pos != vformat.end(); ++pos) {
-	if (pos[0]=='"' && (pos+1)==vformat.end()) break;
+	//UINFO(1,"Parse '"<<*pos<<"'  IP"<<inPct<<" List "<<(void*)(elistp)<<endl);
-	if (inPct && pos[0]=='%') {
+	if (!inPct && pos[0]=='%') {
-	    emitDispState.pushFormat("%%");  // We're printf'ing it, so need to quote the %
-	    inPct = false;
-	} else if (pos[0]=='%') {
 	    inPct = true;
-	    fmt = "";
+	    vfmt = "";
 	} else if (!inPct) {   // Normal text
-	    //char text[2]; text[0]=*pos; text[1]='\0';
 	    emitDispState.pushFormat(*pos);
 	} else { // Format character
-	    if (isdigit(pos[0])) {
+	    inPct = false;
+	    switch (tolower(pos[0])) {
+	    case '0': case '1': case '2': case '3': case '4':
+	    case '5': case '6': case '7': case '8': case '9':
 		// Digits, like %5d, etc.
-		fmt += pos[0];
+		vfmt += pos[0];
-	    } else {
+		inPct = true;  // Get more digits
-		inPct = false;
+		break;
-		switch (tolower(pos[0])) {
+	    case '%':
-		// Special codes
+		emitDispState.pushFormat("%%");  // We're printf'ing it, so need to quote the %
-		case '~': displayArg(nodep,&elistp,fmt,'d'); break;  // Signed decimal
+		break;
-		// Spec: h d o b c l
+	    // Special codes
-		case 'b': displayArg(nodep,&elistp,fmt,'b'); break;
+	    case '~': displayArg(nodep,&elistp,isScan, vfmt,'d'); break;  // Signed decimal
-		case 'c': displayArg(nodep,&elistp,fmt,'c'); break;
+	    // Spec: h d o b c l
-		case 'd': displayArg(nodep,&elistp,fmt,'u'); break;  // Unsigned decimal
+	    case 'b': displayArg(nodep,&elistp,isScan, vfmt,'b'); break;
-		case 'o': displayArg(nodep,&elistp,fmt,'o'); break;
+	    case 'c': displayArg(nodep,&elistp,isScan, vfmt,'c'); break;
-		case 'h':
+	    case 't':
-		case 'x': displayArg(nodep,&elistp,fmt,'x'); break;
+	    case 'd': displayArg(nodep,&elistp,isScan, vfmt,'u'); break;  // Unsigned decimal
-		case 's': displayArg(nodep,&elistp,fmt,'s'); break;
+	    case 'o': displayArg(nodep,&elistp,isScan, vfmt,'o'); break;
-		case 't': displayArg(nodep,&elistp,fmt,'u'); break;
+	    case 'h':
-		case 'm': {
+	    case 'x': displayArg(nodep,&elistp,isScan, vfmt,'x'); break;
-		    emitDispState.pushFormat("%s");
+	    case 's': displayArg(nodep,&elistp,isScan, vfmt,'s'); break;
-		    emitDispState.pushArg(NULL, "vlSymsp->name(");
+	    case 'm': {
-		    for (AstText* textp=nodep->scopeTextp(); textp; textp=textp->nextp()->castText()) {
+		emitDispState.pushFormat("%S");
-			emitDispState.pushFormat(textp->text());
+		emitDispState.pushArg(NULL, "vlSymsp->name()");
-		    }
+		if (!nodep->castDisplay()) nodep->v3fatalSrc("Non-Display with %m");
-		    break;
+		AstScopeName* scopenamep = nodep->castDisplay()->scopeNamep();
-		}
+		if (!scopenamep) nodep->v3fatalSrc("Display with %m but no AstScopeName");
-		case 'u':
+		for (AstText* textp=scopenamep->scopeAttrp(); textp; textp=textp->nextp()->castText()) {
-		case 'z':
+		    emitDispState.pushFormat(textp->text());
-		case 'l':
-		case 'v':
-		    nodep->v3error("Unsupported: $display format code: %"<<pos[0]);
-		    break;
-		default:
-		    nodep->v3error("Unknown $display format code: %"<<pos[0]);
-		    break;
 		}
+		break;
+	    }
+	    case 'u':
+	    case 'z':
+	    case 'l':
+	    case 'v':
+		nodep->v3error("Unsupported: $display format code: %"<<pos[0]);
+		break;
+	    default:
+		nodep->v3error("Unknown $display format code: %"<<pos[0]);
+		break;
 	    }
 	}
     }
     if (elistp != NULL) {
-	nodep->v3error("Extra arguments for $display format\n");
+	// expectFormat also checks this, and should have found it first, so internal
+	elistp->v3error("Internal: Extra arguments for $display format\n");
     }
-    if (nodep->addNewline()) emitDispState.pushFormat("\\n");
+    displayEmit(nodep, isScan);
-    displayEmit(nodep);
 }
 
 //######################################################################
@@ -1213,7 +1268,7 @@ void EmitCImp::emitConfigureImp(AstModule* modp) {
 void EmitCImp::emitCoverageImp(AstModule* modp) {
     if (m_coverIds.size()) {
 	puts("\n// Coverage\n");
-	// Rather then putting out SP_COVER_INSERT calls directly, we do it via this function
+	// Rather than putting out SP_COVER_INSERT calls directly, we do it via this function
 	// This gets around gcc slowness constructing all of the template arguments
 	puts("void "+modClassName(m_modp)+"::__vlCoverInsert(SpZeroed<uint32_t>* countp, const char* filename, int lineno, int column,\n");
 	puts(  	"const char* hier, const char* type, const char* comment) {\n");
@@ -1427,6 +1482,9 @@ void EmitCImp::emitInt(AstModule* modp) {
     if (v3Global.opt.coverage()) {
 	puts("#include \"SpCoverage.h\"\n");
     }
+    if (v3Global.needHInlines()) {   // Set by V3EmitCInlines; should have been called before us
+	puts("#include \""+topClassName()+"__Inlines.h\"\n");
+    }
 
     // Declare foreign instances up front to make C++ happy
     puts("class "+symClassName()+";\n");
@@ -1435,6 +1493,13 @@ void EmitCImp::emitInt(AstModule* modp) {
 	    puts("class "+modClassName(cellp->modp())+";\n");
 	}
     }
+    if (v3Global.opt.trace()) {
+	if (optSystemPerl()) {
+	    puts("class SpTraceVcd;\n");
+	} else {
+	    puts("class SpTraceVcdCFile;\n");
+	}
+    }
 
     puts("\n//----------\n\n");
     emitTextSection(AstType::SCHDR);
@@ -1525,9 +1590,9 @@ void EmitCImp::emitInt(AstModule* modp) {
     } else {
 	puts(modClassName(modp)+"(const char* name=\"TOP\");\n");
 	puts("~"+modClassName(modp)+"();\n");
-	if (v3Global.opt.trace()) {
+    }
-	    puts("void\ttrace (SpTraceVcdCFile* tfp, int levels, int options=0);\n");
+    if (v3Global.opt.trace() && !optSystemPerl()) {
-	}
+	puts("void\ttrace (SpTraceVcdCFile* tfp, int levels, int options=0);\n");
     }
     puts("void\t__Vconfigure("+symClassName()+"* symsp);\n");
     if (optSystemPerl()) puts("/*AUTOMETHODS*/\n");
@@ -1613,7 +1678,7 @@ void EmitCImp::emitImp(AstModule* modp) {
     }
 
     if (m_fast && m_splitFilenum==0) {
-	if (v3Global.opt.trace() && optSystemC() && m_modp->isTop()) {
+	if (v3Global.opt.trace() && optSystemPerl() && m_modp->isTop()) {
 	    puts("\n");
 	    puts("\n/*AUTOTRACE(__MODULE__,recurse,activity,exists)*/\n\n");
 	}
@@ -1669,7 +1734,7 @@ void EmitCImp::main(AstModule* modp, bool slow, bool fast) {
     }
 
     emitImp (modp);
-	 
+
     for (AstNode* nodep=modp->stmtsp(); nodep; nodep = nodep->nextp()) {
 	if (AstCFunc* funcp = nodep->castCFunc()) {
 	    if (v3Global.opt.outputSplit() > 1 && splitSize()
@@ -1700,7 +1765,7 @@ class EmitCTrace : EmitCStmts {
     // METHODS
     void emitTraceHeader() {
 	// Includes
-	if (optSystemC()) {
+	if (optSystemPerl()) {
 	    puts("#include \"SpTraceVcd.h\"\n");
 	}
 	puts("#include \"SpTraceVcdC.h\"\n");
@@ -1712,7 +1777,7 @@ class EmitCTrace : EmitCStmts {
 	puts("\n//======================\n\n");
 
 	puts("void "+topClassName()+"::trace (");
-	if (optSystemC()) {
+	if (optSystemPerl()) {
 	    puts("SpTraceFile* tfp, int, int) {\n");
 	} else {
 	    puts("SpTraceVcdCFile* tfp, int, int) {\n");
@@ -1730,7 +1795,7 @@ class EmitCTrace : EmitCStmts {
 	puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
 	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
 	puts("}\n");
-    
+
 	puts("void "+topClassName()+"::traceFull(SpTraceVcd* vcdp, void* userthis, uint32_t code) {\n");
 	puts("// Callback from vcd->dump()\n");
 	puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
@@ -1900,7 +1965,7 @@ class EmitCTrace : EmitCStmts {
     }
     virtual void visit(AstCoverInc* nodep, AstNUser*) {
     }
-    
+
 public:
     EmitCTrace(bool slow) {
 	m_funcp = NULL;

src/V3EmitC.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -31,6 +31,7 @@
 class V3EmitC {
 public:
     static void emitc();
+    static void emitcInlines();
     static void emitcSyms();
     static void emitcTrace();
 };

src/V3EmitCBase.h

@@ -1,14 +1,14 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -24,10 +24,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
-#include <math.h>
+#include <cmath>
 
 #include "V3Global.h"
 #include "V3File.h"

src/V3EmitCInlines.cpp

@@ -0,0 +1,125 @@
+//*************************************************************************
+// DESCRIPTION: Verilator: Emit C++ for tree
+//
+// Code available from: http://www.veripool.org/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+
+#include "config_build.h"
+#include "verilatedos.h"
+#include <cstdio>
+#include <cstdarg>
+#include <unistd.h>
+#include <cmath>
+#include <map>
+#include <vector>
+
+#include "V3Global.h"
+#include "V3EmitC.h"
+#include "V3EmitCBase.h"
+#include "V3Stats.h"
+
+#define EMITCINLINES_NUM_CONSTW	10	// Number of VL_CONST_W_*X's in verilated.h (IE VL_CONST_W_9X is last)
+
+//######################################################################
+
+class EmitCInlines : EmitCBaseVisitor {
+    // STATE
+    vector<V3Double0>	m_wordWidths;	// What sizes are used?
+
+    // METHODS
+    void emitInt();
+
+    // VISITORS
+    virtual void visit(AstVar* nodep, AstNUser*) {
+	// All wide constants load into variables, so we can just hunt for them
+	if (nodep->widthWords() >= EMITCINLINES_NUM_CONSTW ) {
+	    if (int(m_wordWidths.size()) <= nodep->widthWords()) {
+		m_wordWidths.resize(nodep->widthWords()+5);
+	    }
+	    ++ m_wordWidths.at(nodep->widthWords());
+	    v3Global.needHInlines(true);
+	}
+    }
+
+    // NOPs
+    virtual void visit(AstNodeStmt*, AstNUser*) {}
+    // Default
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+    //---------------------------------------
+    // ACCESSORS
+public:
+    EmitCInlines(AstNetlist* nodep) {
+	nodep->accept(*this);
+	if (v3Global.needHInlines()) {
+	    emitInt();
+	}
+    }
+};
+
+void EmitCInlines::emitInt() {
+    string filename = v3Global.opt.makeDir()+"/"+topClassName()+"__Inlines.h";
+    newCFile(filename, false/*slow*/, false/*source*/);
+    V3OutCFile hf (filename);
+    m_ofp = &hf;
+
+    ofp()->putsHeader();
+    puts("#ifndef _"+topClassName()+"__Inlines_H_\n");
+    puts("#define _"+topClassName()+"__Inlines_H_\n");
+    puts("\n");
+
+    puts("#include \"verilated.h\"\n");
+
+    puts("\n//======================\n\n");
+
+    for (unsigned words=0; words<m_wordWidths.size(); words++) {
+	if (m_wordWidths.at(words)) {
+	    puts("#ifndef VL_HAVE_CONST_W_"+cvtToStr(words)+"X\n");
+	    puts("# define VL_HAVE_CONST_W_"+cvtToStr(words)+"X\n");
+	    puts("static inline WDataOutP VL_CONST_W_"+cvtToStr(words)+"X(int obits, WDataOutP o\n");
+	    puts("\t");
+	    for (int i=words-1; i>=0; --i) {
+		puts(",IData d"+cvtToStr(i));
+		if (i && (i % 8 == 0)) puts("\n\t");
+	    }
+	    puts(") {\n");
+	    puts("   ");
+	    for (int i=words-1; i>=0; --i) {
+		puts(" o["+cvtToStr(i)+"]=d"+cvtToStr(i)+";");
+		if (i && (i % 8 == 0)) puts("\n   ");
+	    }
+	    puts("\n");
+	    puts("    for(int i="+cvtToStr(words)+";i<VL_WORDS_I(obits);i++) o[i] = (IData)0x0;\n");
+	    puts("    return o;\n");
+	    puts("}\n");
+	    puts("#endif\n");
+	    puts("\n");
+	}
+    }
+
+    puts("//======================\n\n");
+    puts("#endif  /*guard*/\n");
+}
+
+//######################################################################
+// EmitC class functions
+
+void V3EmitC::emitcInlines() {
+    UINFO(2,__FUNCTION__<<": "<<endl);
+    EmitCInlines syms (v3Global.rootp());
+}

src/V3EmitCSyms.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,10 +20,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
-#include <math.h>
+#include <cmath>
 #include <map>
 #include <set>
 #include <vector>
@@ -68,7 +67,7 @@ class EmitCSyms : EmitCBaseVisitor {
     virtual void visit(AstNetlist* nodep, AstNUser*) {
 	// Collect list of scopes
 	nodep->iterateChildren(*this);
-	
+
 	// Sort m_scopes by scope name
 	sort(m_scopes.begin(), m_scopes.end(), CmpName());
 	// Output

src/V3EmitMk.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2004-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,10 +20,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
-#include <math.h>
+#include <cmath>
 #include <map>
 #include <vector>
 #include <algorithm>
@@ -79,16 +78,16 @@ public:
 	    of.puts("default: "+v3Global.opt.prefix()+"__ALL.a\n");
 	}
 	of.puts("\n# Constants...\n");
-	of.puts("PERL = "+V3Options::getenvStr("PERL","perl")+"\n");
+	of.puts("PERL = "+V3Options::getenvPERL()+"\n");
-	of.puts("VERILATOR_ROOT = "+V3Options::getenvStr("VERILATOR_ROOT","")+"\n");
+	of.puts("VERILATOR_ROOT = "+V3Options::getenvVERILATOR_ROOT()+"\n");
-	of.puts("SYSTEMPERL = "+V3Options::getenvStr("SYSTEMPERL","")+"\n");
+	of.puts("SYSTEMPERL = "+V3Options::getenvSYSTEMPERL()+"\n");
 
 	of.puts("\n# Switches...\n");
 	of.puts(string("VM_SP = ")+(v3Global.opt.systemPerl()?"1":"0")+"\n");
 	of.puts(string("VM_SC = ")+((v3Global.opt.systemC()&&!v3Global.opt.systemPerl())?"1":"0")+"\n");
 	of.puts(string("VM_SP_OR_SC = ")+(v3Global.opt.systemC()?"1":"0")+"\n");
 	of.puts(string("VM_PCLI = ")+(v3Global.opt.systemC()?"0":"1")+"\n");
-	of.puts(string("VM_SC_TARGET_ARCH = ")+V3Options::getenvStr("SYSTEMC_ARCH","")+"\n");
+	of.puts(string("VM_SC_TARGET_ARCH = ")+V3Options::getenvSYSTEMC_ARCH()+"\n");
 
 	of.puts("\n# Vars...\n");
 	of.puts(string("VM_PREFIX = ")+v3Global.opt.prefix()+"\n");
@@ -138,7 +137,7 @@ public:
 
 	    of.puts("\n# Link rules...\n");
 	    of.puts(v3Global.opt.prefix()+": $(VK_USER_OBJS) $(SP_SRCS) $(VM_PREFIX)__ALL.a\n");
-	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
+	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt\n");
 	    of.puts("\n");
 	}
 

src/V3EmitMk.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3EmitV.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog from tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2004-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,10 +20,10 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
-#include <math.h>
+#include <cmath>
 #include <map>
 #include <vector>
 #include <algorithm>
@@ -164,19 +163,30 @@ public:
     virtual void visit(AstCoverInc*, AstNUser*) {
 	// N/A
     }
-    virtual void visit(AstDisplay* nodep, AstNUser*) {
+
+    void visitNodeDisplay(AstNode* nodep, AstNode* filep, const string& text, AstNode* exprsp) {
 	putbs(nodep->verilogKwd());
 	putbs(" (");
-	if (nodep->filep()) { nodep->filep()->iterateAndNext(*this); putbs(","); }
+	if (filep) { filep->iterateAndNext(*this); putbs(","); }
 	puts("\"");
-	ofp()->putsNoTracking(nodep->text());
+	ofp()->putsNoTracking(text);
 	puts("\"");
-	for (AstNode* expp=nodep->exprsp(); expp; expp = expp->nextp()) {
+	for (AstNode* expp=exprsp; expp; expp = expp->nextp()) {
 	    puts(",");
 	    expp->iterateAndNext(*this);
 	}
 	puts(");\n");
     }
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	visitNodeDisplay(nodep, nodep->filep(), nodep->text(), nodep->exprsp());
+    }
+    virtual void visit(AstFScanF* nodep, AstNUser*) {
+	visitNodeDisplay(nodep, nodep->filep(), nodep->text(), nodep->exprsp());
+    }
+    virtual void visit(AstSScanF* nodep, AstNUser*) {
+	visitNodeDisplay(nodep, nodep->fromp(), nodep->text(), nodep->exprsp());
+    }
+
     virtual void visit(AstFOpen* nodep, AstNUser*) {
 	putbs(nodep->verilogKwd());
 	putbs(" (");
@@ -193,6 +203,12 @@ public:
 	if (nodep->filep()) nodep->filep()->iterateChildren(*this);
 	puts(");\n");
     }
+    virtual void visit(AstFFlush* nodep, AstNUser*) {
+	putbs(nodep->verilogKwd());
+	putbs(" (");
+	if (nodep->filep()) nodep->filep()->iterateChildren(*this);
+	puts(");\n");
+    }
     virtual void visit(AstReadMem* nodep, AstNUser*) {
 	putbs(nodep->verilogKwd());
 	putbs(" (");
@@ -246,6 +262,8 @@ public:
     virtual void visit(AstText* nodep, AstNUser*) {
 	ofp()->putsNoTracking(nodep->text());
     }
+    virtual void visit(AstScopeName* nodep, AstNUser*) {
+    }
     virtual void visit(AstCStmt* nodep, AstNUser*) {
 	putbs("$_CSTMT(");
 	nodep->bodysp()->iterateAndNext(*this);
@@ -366,12 +384,12 @@ public:
     // Terminals
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	puts(nodep->hiername());
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     virtual void visit(AstVarXRef* nodep, AstNUser*) {
 	puts(nodep->dotted());
 	puts(".");
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     virtual void visit(AstConst* nodep, AstNUser*) {
 	puts(nodep->num().ascii(true,true));

src/V3EmitV.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Error.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,9 +18,10 @@
 //
 //*************************************************************************
 
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
-#include <string.h>
+#include <cstring>
+#include <set>
 #include "V3Error.h"
 #ifndef _V3ERROR_NO_GLOBAL_
 # include "V3Ast.h"
@@ -34,7 +34,8 @@
 
 FileLine FileLine::s_defaultFileLine = FileLine(EmptySecret());
 
-int V3Error::s_errcnt = 0;
+int V3Error::s_errCount = 0;
+int V3Error::s_warnCount = 0;
 int V3Error::s_debugDefault = 0;
 ostringstream V3Error::s_errorStr;		// Error string being formed
 V3ErrorCode V3Error::s_errorCode = V3ErrorCode::FATAL;
@@ -45,7 +46,7 @@ bool V3Error::s_pretendError[V3ErrorCode::MAX];
 struct v3errorIniter {
     v3errorIniter() {  V3Error::init(); };
 };
-v3errorIniter v3errorInit; 
+v3errorIniter v3errorInit;
 
 //######################################################################
 // ErrorCode class functions
@@ -100,9 +101,16 @@ bool FileLine::warnOff(const string& msg, bool flag) {
     }
 }
 
+void FileLine::warnLintOff(bool flag) {
+    for (int codei=V3ErrorCode::FIRST_WARN; codei<V3ErrorCode::MAX; codei++) {
+	V3ErrorCode code = (V3ErrorCode)codei;
+	if (code.lintError()) warnOff(code, flag);
+    }
+}
+
 FileLine* FileLine::copyOrSameFileLine() {
     // Return this, or a copy of this
-    // There are often more then one token per line, thus we use the
+    // There are often more than one token per line, thus we use the
     // same pointer as long as we're on the same line.
     static FileLine* lastNewp = NULL;
     if (lastNewp && *lastNewp == *this) {
@@ -162,6 +170,46 @@ void FileLine::v3errorEnd(ostringstream& str) {
 	V3Error::v3errorEnd(str);
     }
 }
+
+#ifdef VL_LEAK_CHECKS
+typedef set<FileLine*> FileLineCheckSet;
+FileLineCheckSet fileLineLeakChecks;
+
+void* FileLine::operator new(size_t size) {
+    FileLine* objp = static_cast<FileLine*>(::operator new(size));
+    fileLineLeakChecks.insert(objp);
+    return objp;
+}
+
+void FileLine::operator delete(void* objp, size_t size) {
+    if (!objp) return;
+    FileLine* flp = static_cast<FileLine*>(objp);
+    FileLineCheckSet::iterator it = fileLineLeakChecks.find(flp);
+    if (it != fileLineLeakChecks.end()) {
+	fileLineLeakChecks.erase(it);
+    } else {
+	flp->v3fatalSrc("Deleting FileLine object that was never tracked\n");
+    }
+    ::operator delete(objp);
+}
+#endif
+
+void FileLine::deleteAllRemaining() {
+#ifdef VL_LEAK_CHECKS
+    // FileLines are allocated, but never nicely freed, as it's much faster
+    // that way.  Unfortunately this makes our leak checking a big mess, so
+    // only when leak checking we'll track them all and cleanup.
+    while (1) {
+	FileLineCheckSet::iterator it=fileLineLeakChecks.begin();
+	if (it==fileLineLeakChecks.end()) break;
+	delete *it;
+	// Operator delete will remove the iterated object from the list.
+	// Eventually the list will be empty and terminate the loop.
+    }
+    fileLineLeakChecks.clear();
+#endif
+}
+
 //######################################################################
 // V3Error class functions
 
@@ -187,25 +235,46 @@ string V3Error::lineStr (const char* filename, int lineno) {
     return out.str();
 }
 
+void V3Error::incWarnings() {
+    s_warnCount++;
+    // We don't exit on a lot of warnings.
+}
+
 void V3Error::incErrors() {
-    s_errcnt++;
+    s_errCount++;
-    if (errorCount() == MAX_ERRORS) {  // Not >= as would otherwise recurse
+    if (errorCount() == v3Global.opt.errorLimit()) {  // Not >= as would otherwise recurse
-	v3fatal ("Exiting due to too many errors encountered\n");
+	v3fatal ("Exiting due to too many errors encountered; --error-limit="<<errorCount()<<endl);
     }
 }
 
 void V3Error::abortIfErrors() {
     if (errorCount()) {
-	v3fatal ("Exiting due to "<<dec<<errorCount()<<" warning(s)\n");
+	v3fatal ("Exiting due to "<<dec<<errorOrWarnCount()<<" warning(s)\n");
     }
 }
 
+void V3Error::abortIfWarnings() {
+    if (errorOrWarnCount()) {
+	v3fatal ("Exiting due to "<<dec<<errorOrWarnCount()<<" warning(s)\n");
+    }
+}
+
+bool V3Error::isError(V3ErrorCode code) {
+    if (code==V3ErrorCode::SUPPRESS) return false;
+    else if (code==V3ErrorCode::INFO) return false;
+    else if (code==V3ErrorCode::FATAL) return true;
+    else if (code==V3ErrorCode::ERROR) return true;
+    else if (code<V3ErrorCode::FIRST_WARN
+	     || s_pretendError[code]) return true;
+    else return false;
+}
+
 string V3Error::msgPrefix(V3ErrorCode code) {
     if (code==V3ErrorCode::SUPPRESS) return "-arning-suppressed: ";
+    else if (code==V3ErrorCode::INFO) return "-Info: ";
     else if (code==V3ErrorCode::FATAL) return "%Error: ";
     else if (code==V3ErrorCode::ERROR) return "%Error: ";
-    else if (code<V3ErrorCode::FIRST_WARN
+    else if (isError(code)) return "%Error-"+(string)code.ascii()+": ";
-	     || s_pretendError[code]) return "%Error-"+(string)code.ascii()+": ";
     else return "%Warning-"+(string)code.ascii()+": ";
 }
 
@@ -244,7 +313,8 @@ void V3Error::v3errorEnd (ostringstream& sstr) {
 	if (sstr.str()[sstr.str().length()-1] != '\n') {
 	    cerr<<endl;
 	}
-	if (s_errorCode!=V3ErrorCode::SUPPRESS) {
+	if (s_errorCode!=V3ErrorCode::SUPPRESS
+	    && s_errorCode!=V3ErrorCode::INFO) {
 	    if (!s_describedEachWarn[s_errorCode]
 		&& !s_pretendError[s_errorCode]) {
 		s_describedEachWarn[s_errorCode] = true;
@@ -258,7 +328,8 @@ void V3Error::v3errorEnd (ostringstream& sstr) {
 		    cerr<<msgPrefix()<<"else you may end up with different sim results."<<endl;
 		}
 	    }
-	    incErrors();
+	    if (isError(s_errorCode)) incErrors();
+	    else incWarnings();
 	    if (s_errorCode==V3ErrorCode::FATAL) {
 		static bool inFatal = false;
 		if (!inFatal) {

src/V3Error.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -34,6 +34,7 @@ class V3ErrorCode {
 public:
     enum en {
 	SUPPRESS,	// Warning suppressed by user
+	INFO,		// General information out
 	FATAL,		// Kill the program
 	ERROR,		// General error out, can't suppress
 	// Error codes:
@@ -45,13 +46,16 @@ public:
 	BLKANDNBLK,	// Blocked and non-blocking assignments to same variable
 	CASEINCOMPLETE,	// Case statement has missing values
 	CASEOVERLAP,	// Case statements overlap
+	CASEWITHX,	// Case with X values
 	CASEX,		// Casex
 	CMPCONST,	// Comparison is constant due to limited range
 	COMBDLY,	// Combinatorial delayed assignment
+	STMTDLY,	// Delayed statement
 	GENCLK,		// Generated Clock
 	IMPLICIT,	// Implicit wire
 	IMPURE,		// Impure function not being inlined
 	MULTIDRIVEN,	// Driven from multiple blocks
+	REDEFMACRO,	// Redefining existing define macro
 	UNDRIVEN,	// No drivers
 	UNOPT,		// Unoptimizable block
 	UNOPTFLAT,	// Unoptimizable block after flattening
@@ -59,6 +63,7 @@ public:
 	UNUSED,		// No receivers
 	VARHIDDEN,	// Hiding variable
 	WIDTH,		// Width mismatch
+	WIDTHCONCAT,	// Unsized numbers/parameters in concatenations
 	MAX
 	// ***Add new elements below also***
     };
@@ -71,15 +76,15 @@ public:
     const char* ascii() const {
 	const char* names[] = {
 	    // Leading spaces indicate it can't be disabled.
-	    " SUPPRESS", " FATAL", " ERROR",
+	    " SUPPRESS", " INFO", " FATAL", " ERROR",
 	     "MULTITOP", "TASKNSVAR",
 	    " FIRST_WARN",
 	    "BLKANDNBLK",
-	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",
+	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CMPCONST",
-	    "COMBDLY", "GENCLK", "IMPLICIT", "IMPURE",
+	    "COMBDLY", "STMTDLY", "GENCLK", "IMPLICIT", "IMPURE",
-	    "MULTIDRIVEN",
+	    "MULTIDRIVEN", "REDEFMACRO",
 	    "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
-	    "VARHIDDEN", "WIDTH",
+	    "VARHIDDEN", "WIDTH", "WIDTHCONCAT",
 	    " MAX"
 	};
 	return names[m_e];
@@ -89,6 +94,14 @@ public:
     // Warnings we'll present to the user as errors
     // Later -Werror- options may make more of these.
     bool pretendError() const { return ( m_e==BLKANDNBLK || m_e==IMPURE); };
+    // Warnings that are lint only
+    bool lintError() const { return ( m_e==CASEINCOMPLETE || m_e==CASEOVERLAP
+				      || m_e==CASEWITHX || m_e==CASEX
+				      || m_e==CMPCONST
+				      || m_e==IMPLICIT
+				      || m_e==UNDRIVEN || m_e==UNSIGNED
+				      || m_e==UNUSED || m_e==VARHIDDEN
+				      || m_e==WIDTH); };
   };
   inline bool operator== (V3ErrorCode lhs, V3ErrorCode rhs) { return (lhs.m_e == rhs.m_e); }
   inline bool operator== (V3ErrorCode lhs, V3ErrorCode::en rhs) { return (lhs.m_e == rhs); }
@@ -104,11 +117,11 @@ class V3Error {
     static bool 	s_describedEachWarn[V3ErrorCode::MAX]; // Told user specifics about this warning
     static bool 	s_pretendError[V3ErrorCode::MAX]; // Pretend this warning is an error
     static int		s_debugDefault;		// Default debugging level
-    static int		s_errcnt;		// Error count
+    static int		s_errCount;		// Error count
+    static int		s_warnCount;		// Error count
     static ostringstream s_errorStr;		// Error string being formed
     static V3ErrorCode	s_errorCode;		// Error string being formed will abort
     enum MaxErrors { 	MAX_ERRORS = 50 };	// Fatal after this may errors
-    static void	incErrors();
 
     V3Error() { cerr<<("Static class"); abort(); }
 
@@ -118,12 +131,18 @@ class V3Error {
     static void		debugDefault(int level) { s_debugDefault = level; }
     static int		debugDefault() { return s_debugDefault; }
     static string	msgPrefix(V3ErrorCode code=s_errorCode);	// returns %Error/%Warn
-    static int		errorCount() { return s_errcnt; }
+    static int		errorCount() { return s_errCount; }
+    static int		warnCount() { return s_warnCount; }
+    static int		errorOrWarnCount() { return errorCount()+warnCount(); }
     // METHODS
+    static void		incErrors();
+    static void		incWarnings();
     static void		init();
     static void		abortIfErrors();
+    static void		abortIfWarnings();
     static void		suppressThisWarning();	// Suppress next %Warn if user has it off
     static void		pretendError(V3ErrorCode code, bool flag) { s_pretendError[code]=flag; }
+    static bool		isError(V3ErrorCode code);
     static string 	v3sform (const char* format, ...);
     static string	lineStr (const char* filename, int lineno);
     static V3ErrorCode	errorCode() { return s_errorCode; }
@@ -143,6 +162,7 @@ inline void v3errorEnd(ostringstream& sstr) { V3Error::v3errorEnd(sstr); }
 
 // These allow errors using << operators: v3error("foo"<<"bar");
 // Careful, you can't put () around msg, as you would in most macro definitions
+#define v3info(msg)  v3errorEnd(((V3Error::v3errorPrep(V3ErrorCode::INFO)<<msg),V3Error::v3errorStr()));
 #define v3fatal(msg) v3errorEnd(((V3Error::v3errorPrep(V3ErrorCode::FATAL)<<msg),V3Error::v3errorStr()));
 #define v3error(msg) v3errorEnd(((V3Error::v3errorPrep(V3ErrorCode::ERROR)<<msg),V3Error::v3errorStr()));
 #define v3warn(code,msg) v3errorEnd(((V3Error::v3errorPrep(V3ErrorCode::code)<<msg),V3Error::v3errorStr()));
@@ -185,9 +205,14 @@ protected:
     void incLineno() { m_lineno++; }
     FileLine* copyOrSameFileLine();
 public:
-    FileLine (const string& filename, int lineno) { m_lineno=lineno; m_filename = filename; m_warnOff=s_defaultFileLine.m_warnOff;}
+    FileLine (const string& filename, int lineno) { m_lineno=lineno; m_filename = filename; m_warnOff=s_defaultFileLine.m_warnOff; }
-    FileLine (FileLine* fromp) { m_lineno=fromp->lineno(); m_filename = fromp->filename(); m_warnOff=fromp->m_warnOff;};
+    FileLine (FileLine* fromp) { m_lineno=fromp->lineno(); m_filename = fromp->filename(); m_warnOff=fromp->m_warnOff; }
-    FileLine (EmptySecret) { m_lineno=0; m_filename="COMMAND_LINE"; m_warnOff=0; } // Only for static constructor
+    FileLine (EmptySecret) { m_lineno=0; m_filename="COMMAND_LINE"; m_warnOff=0; }
+    ~FileLine() { }
+#ifdef VL_LEAK_CHECKS
+    static void* operator new(size_t size);
+    static void operator delete(void* obj, size_t size);
+#endif
     static FileLine& defaultFileLine() { return s_defaultFileLine; }
     int lineno () const { return m_lineno; }
     string ascii() const;
@@ -198,11 +223,14 @@ public:
     void warnOff(V3ErrorCode code, bool flag) { m_warnOff.set(code,flag); }	// Turn on/off warning messages on this line.
     bool warnOff(const string& code, bool flag);  // Returns 1 if ok
     bool warnIsOff(V3ErrorCode code);
+    void warnLintOff(bool flag);
     void warnStateFrom(const FileLine& from) { m_warnOff=from.m_warnOff; }
     void warnResetDefault() { warnStateFrom(s_defaultFileLine); }
 
     void	v3errorEnd(ostringstream& str);
     inline bool operator==(FileLine rhs) { return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename); }
+
+    static void deleteAllRemaining();
 };
 ostream& operator<<(ostream& os, FileLine* fileline);
 

src/V3Expand.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for expand nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2004-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2004-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Expand's Transformations:
-//		
+//
 // Each module:
 //	Expand verilated.h macros into internal micro optimizations (RTL)
 //	this will enable later optimizations.
@@ -32,8 +31,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 
@@ -168,7 +167,7 @@ private:
 	}
 	return newp;
     }
-	
+
     AstNode* newSelBitWord(AstNode* lsbp, int wordAdder) {
 	// Return equation to get the VL_BITWORD of a constant or non-constant
 	if (lsbp->castConst()) {
@@ -355,7 +354,7 @@ private:
 	    AstNode* lowwordp = new AstWordSel (nodep->fromp()->fileline(),
 						nodep->fromp()->cloneTree(true),
 						newSelBitWord(nodep->lsbp(), 0));
-	    if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep); 
+	    if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep);
 	    AstNode* lowp = new AstShiftR (nodep->fileline(),
 					   lowwordp,
 					   newSelBitBit(nodep->lsbp()),
@@ -368,7 +367,7 @@ private:
 		    new AstWordSel (nodep->fromp()->fileline(),
 				    nodep->fromp()->cloneTree(true),
 				    newSelBitWord(nodep->lsbp(), 1));
-		if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep); 
+		if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep);
 		// If we're selecting bit zero, then all 32 bits in word 1 get shifted << by 32 bits
 		// else we need to form the lower word, so we << by 31 or less
 		// nbitsfromlow <= (lsb==0) ? 64-bitbit(lsb) : 32-bitbit(lsb)
@@ -406,7 +405,7 @@ private:
 		    new AstWordSel (nodep->fromp()->fileline(),
 				    nodep->fromp()->cloneTree(true),
 				    newSelBitWord(nodep->lsbp(), 2));
-		if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep); 
+		if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep);
 		AstNode* himayp =
 		    new AstShiftL (nodep->fileline(),
 				   hiwordp,
@@ -434,7 +433,7 @@ private:
 	    UINFO(8,"    SEL->SHIFT "<<nodep<<endl);
 	    AstNode* fromp = nodep->fromp()->unlinkFrBack();
 	    AstNode* lsbp = nodep->lsbp()->unlinkFrBack();
-	    if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep); 
+	    if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep);
 	    AstNode* newp = new AstShiftR (nodep->fileline(),
 					   fromp,
 					   dropCondBound(lsbp),
@@ -504,7 +503,7 @@ private:
 	bool destwide = lhsp->fromp()->isWide();
 	bool ones = nodep->rhsp()->isAllOnesV();
 	if (lhsp->lsbp()->castConst()) {
-	    // The code should work without this constant test, but it won't 
+	    // The code should work without this constant test, but it won't
 	    // constify as nicely as we'd like.
 	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
 	    AstNode* destp = lhsp->fromp()->unlinkFrBack();
@@ -531,6 +530,8 @@ private:
 								  rhsp, lsb)));
 		    }
 		}
+		rhsp->deleteTree(); rhsp=NULL;
+		destp->deleteTree(); destp=NULL;
 	    } else {
 		UINFO(8,"    ASSIGNSEL(const,narrow) "<<nodep<<endl);
 		if (destp->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep);
@@ -590,7 +591,7 @@ private:
 		//   For wide destp, we can either form a equation for every destination word,
 		// with the appropriate long equation of if it's being written or not.
 		//   Or, we can use a LHS variable arraysel with non-constant index to set the vector.
-		// Doing the variable arraysel is better for globals and large arrays, 
+		// Doing the variable arraysel is better for globals and large arrays,
 		// doing every word is better for temporaries and if we're setting most words
 		// since it may result in better substitution optimizations later.
 		//   This results in so much code, we're better off leaving a function call.
@@ -628,7 +629,7 @@ private:
 		//newp->dumpTree(cout,"-  new: ");
 		insertBefore(nodep,newp);
 		return true;
-	    }		
+	    }
 	}
     }
 
@@ -639,10 +640,10 @@ private:
 	} else {
 	    UINFO(8,"    CONCAT "<<nodep<<endl);
 	    AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
-	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();	
+	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
 	    int rhsshift = rhsp->widthMin();
-	    if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); 
+	    if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
-	    if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep); 
+	    if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep);
 	    AstNode* newp = new AstOr (nodep->fileline(),
 				       new AstShiftL (nodep->fileline(),
 						      lhsp,
@@ -655,7 +656,7 @@ private:
     }
     bool expandWide (AstNodeAssign* nodep, AstConcat* rhsp) {
 	UINFO(8,"    Wordize ASSIGN(CONCAT) "<<nodep<<endl);
-	// Lhs or Rhs may be word, long, or quad. 
+	// Lhs or Rhs may be word, long, or quad.
 	// newAstWordSelClone nicely abstracts the difference.
 	int rhsshift = rhsp->rhsp()->widthMin();
 	// Sometimes doing the words backwards is preferrable.
@@ -668,7 +669,7 @@ private:
 						      rhsp->lhsp(), rhsshift),
 				     newAstWordSelClone (rhsp->rhsp(), w)));
 	}
- 	return true;
+	return true;
     }
 
     virtual void visit(AstReplicate* nodep, AstNUser*) {
@@ -688,7 +689,7 @@ private:
 		AstConst* constp = nodep->rhsp()->castConst();
 		if (!constp) nodep->v3fatalSrc("Replication value isn't a constant.  Checked earlier!");
 		uint32_t times = constp->asInt();
-		if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); 
+		if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
 		newp = lhsp->cloneTree(true);
 		for (unsigned repnum=1; repnum<times; repnum++) {
 		    int rhsshift = repnum*lhswidth;
@@ -729,7 +730,7 @@ private:
 	    }
 	    addWordAssign(nodep, w, newp);
 	}
- 	return true;
+	return true;
     }
 
     virtual void visit(AstChangeXor* nodep, AstNUser*) {
@@ -803,7 +804,7 @@ private:
 	    for (int w=0; w<nodep->lhsp()->widthWords(); w++) {
 		AstNode* eqp = newAstWordSelClone (nodep->lhsp(), w);
 		if (w==nodep->lhsp()->widthWords()-1) {
-		    // Rather then doing a (slowish) ==##, we OR in the bits that aren't part of the mask
+		    // Rather than doing a (slowish) ==##, we OR in the bits that aren't part of the mask
 		    eqp = new AstOr (nodep->fileline(),
 				     new AstConst (nodep->fileline(), notWideMask(nodep->lhsp())),
 				     eqp);

src/V3Expand.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Expansion of wide operator macros to C operators
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3File.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,9 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdarg.h>
+#include <cstdarg>
 #include <sys/stat.h>
+#include <sys/types.h>
 #include <unistd.h>
 #include <iomanip>
 #include <memory>
@@ -232,12 +232,21 @@ bool V3File::checkTimes(const string& filename, const string& cmdline) {
     return dependImp.checkTimes(filename, cmdline);
 }
 
+void V3File::createMakeDir() {
+    static bool created = false;
+    if (!created) {
+	created = true;
+	mkdir(v3Global.opt.makeDir().c_str(), 0777);
+    }
+}
+
 //######################################################################
 // V3OutFile: A class for printing to a file, with automatic indentation of C++ code.
 
 V3OutFile::V3OutFile(const string& filename)
-    : m_lineno(1), m_column(0), m_nobreak(false), m_prependIndent(true), m_indentLevel(0)
+    : m_filename(filename), m_lineno(1), m_column(0)
-      , m_declSAlign(0), m_declNSAlign(0), m_declPadNum(0) {
+    , m_nobreak(false), m_prependIndent(true), m_indentLevel(0)
+    , m_declSAlign(0), m_declNSAlign(0), m_declPadNum(0) {
     if ((m_fp = V3File::new_fopen_w(filename.c_str())) == NULL) {
 	v3fatal("Cannot write "<<filename);
     }

src/V3File.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -24,7 +24,7 @@
 #include "config_build.h"
 #include "verilatedos.h"
 #include "V3Error.h"
-#include <stdio.h>
+#include <cstdio>
 #include <stack>
 #include <set>
 #include <fstream>
@@ -46,6 +46,7 @@ public:
 	return new_ofstream_nodepend (filename, append);
     }
     static ofstream* new_ofstream_nodepend(const string& filename, bool append=false) {
+	if (filename != "/dev/null") createMakeDir();
 	if (append) {
 	    return new ofstream(filename.c_str(), ios::app);
 	} else {
@@ -53,15 +54,20 @@ public:
 	}
     }
     static FILE* new_fopen_w(const string& filename) {
+	if (filename != "/dev/null") createMakeDir();
 	addTgtDepend(filename);
 	return fopen(filename.c_str(),"w");
     }
+
     // Dependencies
     static void addSrcDepend(const string& filename);
     static void addTgtDepend(const string& filename);
     static void writeDepend(const string& filename);
     static void writeTimes(const string& filename, const string& cmdline);
     static bool checkTimes(const string& filename, const string& cmdline);
+
+    // Directory utilities
+    static void createMakeDir();
 };
 
 //============================================================================
@@ -81,6 +87,7 @@ public:
 private:
     // MEMBERS
     FILE*	m_fp;
+    string	m_filename;
     int		m_lineno;
     int		m_column;
     int		m_nobreak;	// Basic operator or begin paren, don't break next
@@ -114,8 +121,9 @@ public:
     bool tokenStart(const char* cp, const char* cmp);
     bool tokenEnd(const char* cp);
     void indentInc() { m_indentLevel += INDBLK; };
-    void indentDec() { m_indentLevel -= INDBLK;
+    void indentDec() {
-       UASSERT(m_indentLevel>=0,"Underflow of indentation\n");
+	m_indentLevel -= INDBLK;
+	UASSERT(m_indentLevel>=0, ": "<<m_filename<<": Underflow of indentation\n");
     }
     void blockInc() { m_parenVec.push(m_indentLevel + INDBLK); }
     void blockDec() { if (!m_parenVec.empty()) m_parenVec.pop(); }

src/V3Gate.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Gate optimizations, such as wire elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Gate's Transformations:
-//		
+//
 // Extract a graph of the *entire* netlist with cells expanded
 // Perform constant optimization across the graph
 // Create VARSCOPEs for any variables we can rip out
@@ -28,8 +27,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <iomanip>
@@ -170,7 +169,7 @@ private:
 	// V3Const cleans up any NOTs by flipping the edges for us
 	if (m_buffersOnly
 	    && !(nodep->rhsp()->castVarRef()
-		 // Until NEW_ORDERING, avoid making non-clocked logic into clocked, 
+		 // Until NEW_ORDERING, avoid making non-clocked logic into clocked,
 		 // as it slows down the verilator_sim_benchmark
 		 || (nodep->rhsp()->castNot()
 		     && nodep->rhsp()->castNot()->lhsp()->castVarRef()
@@ -341,9 +340,9 @@ private:
 	    if (!varscp) nodep->v3fatalSrc("Var didn't get varscoped in V3Scope.cpp\n");
 	    GateVarVertex* varvertexp = makeVarVertex(varscp);
 	    UINFO(5," VARREF to "<<varscp<<endl);
-	    // We use weight of one; if we ref the var more then once, when we simplify,
+	    // We use weight of one; if we ref the var more than once, when we simplify,
 	    // the weight will increase
-	    if (nodep->lvalue()) {	
+	    if (nodep->lvalue()) {
 		new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1);
 	    } else {
 		new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1);
@@ -433,7 +432,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 		}
 	    }
 	    else if (!vvertexp->inSize1()) {
-		vvertexp->clearReducible("size!1");	// Can't deal with more then one src
+		vvertexp->clearReducible("size!1");	// Can't deal with more than one src
 	    }
 	    // Reduce it?
 	    if (!vvertexp->reducible()) {
@@ -490,7 +489,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 			if (debug()>=5) substp->dumpTree(cout,"\t  subst:  ");
 			m_statSigs++;
 			while (V3GraphEdge* edgep = vvertexp->outBeginp()) {
- 			    GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
+			    GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
 			    AstNode* consumerp = consumeVertexp->nodep();
 			    optimizeElimVar(vvertexp->varScp(), substp, consumerp);
 			    // If the new replacement referred to a signal,

src/V3Gate.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3GenClk.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,13 +20,13 @@
 // GENCLK TRANSFORMATIONS:
 //	Follow control-flow graph with assignments and var usages
 //	    ASSIGNDLY to variable later used as clock requires change detect
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 
 #include "V3Global.h"
@@ -93,7 +92,7 @@ private:
     }
     //----
     virtual void visit(AstVarRef* nodep, AstNUser*) {
-	// Consumption/generation of a variable, 
+	// Consumption/generation of a variable,
 	AstVarScope* vscp = nodep->varScopep();
 	if (!vscp) nodep->v3fatalSrc("Scope not assigned");
 	if (m_activep && !nodep->user3()) {
@@ -172,7 +171,7 @@ private:
     //----
 
     virtual void visit(AstVarRef* nodep, AstNUser*) {
-	// Consumption/generation of a variable, 
+	// Consumption/generation of a variable,
 	AstVarScope* vscp = nodep->varScopep();
 	if (!vscp) nodep->v3fatalSrc("Scope not assigned");
 	if (m_activep) {

src/V3GenClk.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock Repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3Global.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Common headers
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -42,8 +42,10 @@ class V3Global {
     AstNetlist*	m_rootp;	// Root of entire netlist
     int		m_debugFileNumber;	// Number to append to debug files created
     bool	m_assertWidthsSame;	// Tree should have width()==widthMin()
-    // Options
+    bool	m_needHInlines;		// Need a __Inlines file
+
 public:
+    // Options
     V3Options	opt;		// All options; let user see them directly
 
   public:
@@ -52,6 +54,7 @@ public:
 	m_rootp = new AstNetlist;
 	m_debugFileNumber = 0;
 	m_assertWidthsSame = false;
+	m_needHInlines = false;
     }
     void clear() {
 	if (m_rootp) m_rootp->deleteTree(); m_rootp=NULL;
@@ -70,6 +73,8 @@ public:
 	char digits[100]; sprintf(digits, "%02d", m_debugFileNumber);
 	return opt.makeDir()+"/"+opt.prefix()+"_"+digits+"_"+nameComment;
     }
+    bool needHInlines() const { return m_needHInlines; }
+    void needHInlines(bool flag) { m_needHInlines=flag; }
 };
 
 extern V3Global v3Global;

src/V3Graph.cpp

@@ -1,14 +1,14 @@
-// $Id$
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +21,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <vector>
@@ -106,7 +106,7 @@ ostream& operator<<(ostream& os, V3GraphVertex* vertexp) {
 //######################################################################
 // Edges
 
-V3GraphEdge::V3GraphEdge(V3Graph* graphp, 
+V3GraphEdge::V3GraphEdge(V3Graph* graphp,
 			 V3GraphVertex* fromp, V3GraphVertex* top, int weight,
 			 bool cutable) {
     UASSERT(fromp, "Null from pointer\n");
@@ -177,10 +177,10 @@ void V3Graph::clear() {
 void V3Graph::userClearVertices() {
     // Clear user() in all of tree
     // We may use the userCnt trick in V3Ast later... For now we don't call this often, and
-    // the extra code on each read of user() would probably slow things down more then help.
+    // the extra code on each read of user() would probably slow things down more than help.
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	vertexp->user(0);
-	vertexp->userp(NULL);	 // Its a union, but might be different size then user()
+	vertexp->userp(NULL);	 // Its a union, but might be different size than user()
     }
 }
 
@@ -189,7 +189,7 @@ void V3Graph::userClearEdges() {
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
 	    edgep->user(0);
-	    edgep->userp(NULL);	 // Its a union, but might be different size then user()
+	    edgep->userp(NULL);	 // Its a union, but might be different size than user()
 	}
     }
 }

src/V3Graph.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -67,7 +67,7 @@ public:
     virtual ~V3Graph();
     static void debug(int level) { s_debug = level; }
     virtual string dotRankDir() { return "TB"; }	// rankdir for dot plotting
-    
+
     // METHODS
     void clear();	// Empty it of all vertices/edges, as if making a new object
 

src/V3GraphAcyc.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph acyclic algorithm
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <vector>
@@ -440,7 +439,7 @@ void GraphAcyc::place() {
     UINFO(4, "    Cutable edges = "<<numEdges<<endl);
 
     vector<V3GraphEdge*>	edges;	// List of all edges to be processed
-    edges.reserve(numEdges+1); // Make the vector properly sized right off the bat -- faster then reallocating
+    edges.reserve(numEdges+1); // Make the vector properly sized right off the bat -- faster than reallocating
     for (V3GraphVertex* vertexp = m_breakGraph.verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	vertexp->user(0);	// Clear in prep of next step
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {

src/V3GraphAlg.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <algorithm>
 #include <vector>
@@ -58,7 +57,7 @@ void V3Graph::deleteCutableOnlyEdges() {
     }
 
     // Pass 2, delete those marked
-    // Rather then doing a delete() we set the weight to 0 which disconnects the edge.
+    // Rather than doing a delete() we set the weight to 0 which disconnects the edge.
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	if (vertexp->user()) {
 	    //UINFO(7,"Disconnect "<<vertexp->name()<<endl);
@@ -99,9 +98,9 @@ private:
 		} else { // Duplicate
 		    bool saveOld = true;
 		    if (prevEdgep->cutable() && !edgep->cutable()) {
-			saveOld = false;  // new !cutable more important then old
+			saveOld = false;  // new !cutable more important than old
 		    } else if (!prevEdgep->cutable() && edgep->cutable()) {
-			saveOld = true;  // old !cutable more important then new
+			saveOld = true;  // old !cutable more important than new
 		    } else {
 			saveOld = true;
 			if (!m_sumWeights && (prevEdgep->weight() < edgep->weight())) {  // Keep max weight
@@ -345,7 +344,7 @@ private:
 	if (m_done) return;
 
 	m_callTrace.reserve(currentRank+10);   // Leave slop for speed
-	m_callTrace[currentRank++] = vertexp; 
+	m_callTrace[currentRank++] = vertexp;
 
 	if (vertexp->user() == 1) {
 	    for (unsigned i=0; i<currentRank; i++) {

src/V3GraphAlg.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph algorithm base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //

src/V3GraphDfa.cpp

@@ -1,14 +1,13 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2005-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2005-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -21,8 +20,8 @@
 
 #include "config_build.h"
 #include "verilatedos.h"
-#include <stdio.h>
+#include <cstdio>
-#include <stdarg.h>
+#include <cstdarg>
 #include <unistd.h>
 #include <stack>
 #include <map>
@@ -224,7 +223,7 @@ private:
 	    }
 	}
     }
-	
+
     void main() {
 	UINFO(5,"Dfa to Nfa conversion...\n");
 	// Vertex::color() begin: 1 indicates vertex on DFA graph, 0=NFA graph
@@ -236,7 +235,7 @@ private:
 
 	// Find NFA start
 	DfaVertex* nfaStartp = graphp()->findStart();
-	    
+
 	// Create new DFA State (start state) from the NFA states
 	DfaVertex* dfaStartp = newDfaVertex(nfaStartp);
 
@@ -267,7 +266,7 @@ private:
 	    }
 	}
 	if (debug()>=6) m_graphp->dumpDotFilePrefixed("dfa_start");
-	insertDfaOrigins(dfaStartp); 
+	insertDfaOrigins(dfaStartp);
 
 	int i=0;
 	UINFO(5,"Main state conversion...\n");
@@ -293,7 +292,7 @@ private:
 		    }
 		}
 	    }
-	    
+
 	    // Foreach input state (NFA inputs of this DFA state)
 	    for (set<DfaInput>::const_iterator inIt=inputs.begin(); inIt!=inputs.end(); ++inIt) {
 		DfaInput input = *inIt;
@@ -303,7 +302,7 @@ private:
 		// Find all states reachable for given input
 		DfaStates nfasWithInput;
 		findNfasWithInput(dfaStatep, input, nfasWithInput/*ref*/);
-		
+
 		// nfasWithInput now maps to the DFA we want a transition to.
 		// Does a DFA already exist with this, and only this subset of NFA's?
 		DfaVertex* toDfaStatep = findDfaOrigins(nfasWithInput);
@@ -317,7 +316,7 @@ private:
 			new DfaEdge (graphp(), toDfaStatep, *nfaIt, DfaEdge::NA());
 			if ((*nfaIt)->accepting()) toDfaStatep->accepting(true);
 		    }
-		    insertDfaOrigins(toDfaStatep); 
+		    insertDfaOrigins(toDfaStatep);
 		}
 		// Add input transition
 		new DfaEdge (graphp(), dfaStatep, toDfaStatep, input);
@@ -375,7 +374,7 @@ private:
     }
 
     void optimize_accepting_out() {
-	// Delete outbound edges from accepting states 
+	// Delete outbound edges from accepting states
 	// (As once we've accepted, we no longer care about anything else.)
 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
@@ -480,3 +479,97 @@ public:
 void DfaGraph::dfaReduce() {
     DfaGraphReduce (this, &V3GraphEdge::followAlwaysTrue);
 }
+
+//######################################################################
+//######################################################################
+// Algorithms - complement a DFA
+//
+// The traditional algorithm is to make a rejecting state, add edges to
+// reject from all missing values, then swap accept and reject.  Rather
+// than swap at the end, it's faster if we swap up front, then do the edge
+// changes.
+//
+// 1. Since we didn't log rejecting states, make a temp state (this will be
+// the old accept, and new reject).
+//
+// 2. All vertexes except start/accept get edges to NEW accept for any
+// non-existing case.  Weedely we don't have a nice way of representing
+// this so we just create a edge for each case and mark it "complemented."
+//
+// 3. Delete temp vertex (old accept/new reject) and related edges.
+// The user's old accept is now the new accept.  This is imporant as
+// we want the virtual type of it to be intact.
+
+class DfaGraphComplement : GraphAlg {
+private:
+    // MEMBERS
+    DfaVertex* m_tempNewerReject;
+
+    // METHODS
+    int debug() { return 9; }
+    DfaGraph* graphp() { return static_cast<DfaGraph*>(m_graphp); }
+
+    void add_complement_edges() {
+	// Find accepting vertex
+	DfaVertex* acceptp = NULL;
+	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
+	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
+		if (vvertexp->accepting()) {
+		    acceptp = vvertexp;
+		    break;
+		}
+	    }
+	}
+	if (!acceptp) v3fatalSrc("No accepting vertex in DFA\n");
+
+	// Remap edges
+	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
+	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
+		//UINFO(9, "   on vertex "<<vvertexp->name()<<endl);
+		if (!vvertexp->accepting() && vvertexp != m_tempNewerReject) {
+		    for (V3GraphEdge* nextp, *edgep = vertexp->outBeginp(); edgep; edgep=nextp) {
+			nextp = edgep->outNextp();
+			if (!edgep->user()) { // Not processed
+			    // Old edges to accept now go to new reject
+			    DfaEdge* vedgep = static_cast<DfaEdge*>(edgep);
+			    DfaVertex* tovertexp = static_cast<DfaVertex*>(edgep->top());
+			    if (tovertexp->accepting()) {
+				new DfaEdge(graphp(), vvertexp, m_tempNewerReject, vedgep);
+				edgep->unlinkDelete(); edgep=NULL;
+			    }
+
+			    // NOT of all values goes to accept
+			    // We make a edge for each value to OR, IE
+			    // edge(complemented,a) edge(complemented,b) means !(a | b)
+			    if (!tovertexp->accepting()) {  // Note we must include edges moved above to reject
+				DfaEdge* newp = new DfaEdge (graphp(), vvertexp, acceptp, vedgep);
+				newp->complement(!newp->complement());
+				newp->user(1);
+			    }
+			}
+		    }
+		}
+	    }
+	}
+    }
+public:
+    DfaGraphComplement(V3Graph* dfagraphp, V3EdgeFuncP edgeFuncp)
+	: GraphAlg(dfagraphp, edgeFuncp) {
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_in");
+
+	// Vertex::m_user begin: 1 indicates new edge, no more processing
+	m_graphp->userClearEdges();
+
+	m_tempNewerReject = new DfaVertex(graphp());
+	add_complement_edges();
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_preswap");
+
+	m_tempNewerReject->unlinkDelete(graphp()); m_tempNewerReject=NULL;
+	if (debug()>=6) m_graphp->dumpDotFilePrefixed("comp_out");
+    }
+    ~DfaGraphComplement() {}
+};
+
+void DfaGraph::dfaComplement() {
+    DfaGraphComplement (this, &V3GraphEdge::followAlwaysTrue);
+}

src/V3GraphDfa.h

@@ -1,14 +1,14 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph automata base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
 //*************************************************************************
 //
-// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// Copyright 2003-2008 by Wilson Snyder.  This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // General Public License or the Perl Artistic License.
 //
@@ -43,16 +43,18 @@ class DfaEdge;
 /// or epsilon, represented as a empty list of inputs.
 ///
 /// We're only looking for matches, so the only accepting states are
-/// at the end of the transformations.
+/// at the end of the transformations.  (If we want the complement, we
-///	
+/// call complement and the algorithm makes a REJECT state, then flips
+/// accept and reject for you.)
+///
 /// Common transforms:
 ///
 ///	"*":	DfaVertex(START) --> [epsilon] -->DfaVertex(ACCEPT)
 ///
 ///	"L":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
 ///
-///	"LR":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx()
+///	"LR":	...->[ON_L]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
-///		   ->[ON_R]-->DfaVtx-->[epsilon]-->DfaVtx(ACCEPT)
+///		   ->[ON_R]-->DfaVtx-->[epsilon]-/
 ///
 ///	"L|R":	...->DfaVtx-->[epsilon]-->DfaVtx-->[ON_L]-->DfaVtx()->[epsilon]-->DfaVtx(ACCEPT)
 ///			   \->[epsilon]-->DfaVtx-->[ON_R]-->DfaVtx()->[epsilon]-/
@@ -76,14 +78,17 @@ public:
 
     /// Simplify a DFA automata
     void dfaReduce();
+
+    /// Complement result (must already be dfa)
+    void dfaComplement();
 };
 
 //=============================================================================
 // Vertex
 
 class DfaVertex : public V3GraphVertex {
-    // Each DFA state is captured in this vertex.  
+    // Each DFA state is captured in this vertex.
-    // Start and accepting are members, rather then the more intuitive
+    // Start and accepting are members, rather than the more intuitive
     // subclasses, as subclassing them would make it harder to inherit from here.
     bool	m_start;	// Start state
     bool	m_accepting;	// Accepting state?
@@ -93,7 +98,7 @@ public:
 	: V3GraphVertex(graphp)
 	, m_start(start), m_accepting(accepting) {}
     virtual DfaVertex* clone(DfaGraph* graphp) {
-    	return new DfaVertex(graphp, start(), accepting()); }
+	return new DfaVertex(graphp, start(), accepting()); }
     virtual ~DfaVertex() {}
     // ACCESSORS
     virtual string dotShape() const { return (accepting()?"doublecircle":""); }
@@ -113,20 +118,33 @@ typedef AstNUser* DfaInput;
 
 class DfaEdge : public V3GraphEdge {
     DfaInput	m_input;
+    bool	m_complement;	// Invert value when doing compare
 public:
     static DfaInput EPSILON() { return NULL; }
     static DfaInput NA() { return AstNUser::fromInt(1); }	// as in not-applicable
     // CONSTRUCTORS
     DfaEdge(DfaGraph* graphp, DfaVertex* fromp, DfaVertex* top, DfaInput input)
 	: V3GraphEdge(graphp, fromp, top, 1)
-	, m_input(input) {}
+	, m_input(input), m_complement(false) {}
+    DfaEdge(DfaGraph* graphp, DfaVertex* fromp, DfaVertex* top, const DfaEdge* copyfrom)
+	: V3GraphEdge(graphp, fromp, top, copyfrom->weight())
+	, m_input(copyfrom->input()), m_complement(copyfrom->complement()) {}
     virtual ~DfaEdge() {}
     // METHODS
-    virtual string dotColor() const { return na()?"yellow":epsilon()?"green":"black"; }
+    virtual string dotColor() const {
-    virtual string dotLabel() const { return na()?"":epsilon()?"e":cvtToStr((void*)(input())); }
+	return (na() ? "yellow"
+		: epsilon() ? "green"
+		: "black"); }
+    virtual string dotLabel() const {
+	return (na() ? ""
+		: epsilon() ? "e"
+		: complement() ? ("not "+cvtToStr((void*)(input())))
+		: cvtToStr((void*)(input()))); }
     virtual string dotStyle() const { return (na()||cutable())?"dashed":""; }
     bool epsilon() const { return input()==EPSILON(); }
     bool na() const { return input()==NA(); }
+    bool complement() const { return m_complement; }
+    void complement(bool value) { m_complement=value; }
     DfaInput	input() const { return m_input; }
 };