Fix tracing missing changes on undriven public wires.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** "Make install" now installs verilator_includer and verilator_profcfunc.
 
+**** Fix tracing missing changes on undriven public wires. [Rodney Sinclair]
+
 **** Fix syntax error when "`include `defname" is ifdefed.  [John Dickol]
 
 **** Fix error when macro call has commas in concatenate. [John Dickol]

src/V3Trace.cpp

@@ -554,7 +554,7 @@ private:
 	} else if (nodep->funcType() == AstCFuncType::TRACE_CHANGE) {
 	    m_chgFuncp = nodep;
 	}
-	V3GraphVertex* funcVtxp = new TraceCFuncVertex(&m_graph, nodep);
+	V3GraphVertex* funcVtxp = getCFuncVertexp(nodep);
 	if (!m_finding) {  // If public, we need a unique activity code to allow for sets directly in this func
 	    if (nodep->funcPublic() || nodep->name() == "_eval") {
 		// Need a non-null place to remember to later add a statement; make one
@@ -591,7 +591,8 @@ private:
 	    }
 	    V3GraphVertex* traceVtxp = m_tracep->userp()->castGraphVertex();
 	    new V3GraphEdge(&m_graph, varVtxp, traceVtxp, 1);
-	    if (nodep->varp()->isPrimaryIn()) {   // Always need to trace primary inputs
+	    if (nodep->varp()->isPrimaryIn()   // Always need to trace primary inputs
+		|| nodep->varp()->isSigPublic()) {  // Or ones user can change
 		new V3GraphEdge(&m_graph, m_alwaysVtxp, traceVtxp, 1);
 	    }
 	}

test_regress/driver.pl

@@ -246,6 +246,13 @@ sub error {
     $self->{errors} ||= $msg;
 }
 
+sub skip {
+    my $self = shift;
+    my $msg = join('',@_);
+    warn "%Warning: Skip: $self->{mode}/$self->{name}: ".$msg."\n";
+    $self->{errors} ||= "Skip: ".$msg;
+}
+
 sub read {
     my $self = shift;
     # Read the control file
@@ -747,6 +754,23 @@ sub files_identical {
     return 1;
 }
 
+sub vcd_identical {
+    my $self = (ref $_[0]? shift : $Last_Self);
+    my $fn1 = shift;
+    my $fn2 = shift;
+    if (!-r $fn1) { $self->error("File does not exist $fn1\n"); return 0; }
+    if (!-r $fn2) { $self->error("File does not exist $fn2\n"); return 0; }
+    my $out = `vcddiff --help`;
+    if ($out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; }
+    $out = `vcddiff "$fn1" "$fn2"`;
+    if ($out ne '') {
+	print $out;
+	$self->error("VCD miscompare $fn1 $fn2\n");
+	return 0;
+    }
+    return 1;
+}
+
 sub file_grep_not {
     my $self = (ref $_[0]? shift : $Last_Self);
     my $filename = shift;

test_regress/t/t_trace_public.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (
+    input  wire CLK,
+    output reg  RESET
+	  );
+
+   glbl glbl;
+
+   initial RESET = 1'b1;
+   always @ (posedge CLK)
+     RESET <= glbl.GSR;
+
+endmodule
+
+module glbl();
+`ifdef PUB_FUNC
+   wire GSR;
+   task setGSR;
+      /* verilator public */
+      input value;
+      GSR = value;
+   endtask
+`else
+   wire GSR /*verilator public*/;
+`endif
+endmodule

test_regress/t/t_trace_public_func.cpp

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+#include <verilated.h>
+#include <SpTraceVcdC.h>
+
+#include "Vt_trace_public_func.h"
+#include "Vt_trace_public_func_t.h"
+#include "Vt_trace_public_func_glbl.h"
+
+unsigned long long main_time = 0;
+double sc_time_stamp() {
+    return (double)main_time;
+}
+
+const unsigned long long dt_2 = 3;
+
+int main(int argc, char **argv, char **env) {
+    Vt_trace_public_func *top = new Vt_trace_public_func();
+
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+
+    SpTraceVcdCFile* tfp = new SpTraceVcdCFile;
+    top->trace(tfp,99);
+    tfp->open("obj_dir/t_trace_public_func_simx.vcd");
+
+    while (main_time <= 20) {
+	top->CLK   = (main_time/dt_2)%2;
+	top->eval();
+
+	top->v->glbl->setGSR(main_time < 7);
+
+	tfp->dump((unsigned int)(main_time));
+	++main_time;
+    }
+    tfp->close();
+    top->final();
+    printf ("*-* All Finished *-*\n");
+    return 0;
+}

test_regress/t/t_trace_public_func.out

@@ -0,0 +1,53 @@
+$version Generated by SpTraceVcd $end
+$date Wed Jun 11 19:43:32 2008
+ $end
+$timescale 1ns $end
+
+ $scope module TOP $end
+  $var wire  1 $ CLK $end
+  $var wire  1 % RESET $end
+  $scope module v $end
+   $var wire  1 $ CLK $end
+   $var wire  1 # RESET $end
+   $scope module glbl $end
+    $var wire  1 & GSR $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+0$
+1%
+1&
+#1
+#2
+#3
+1$
+#4
+#5
+#6
+0$
+#7
+0&
+#8
+#9
+0#
+1$
+0%
+#10
+#11
+#12
+0$
+#13
+#14
+#15
+1$
+#16
+#17
+#18
+0$
+#19
+#20

test_regress/t/t_trace_public_func.pl

@@ -0,0 +1,28 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_public.v");
+
+if ($Last_Self->{v3}) {
+    compile (
+	     make_top_shell => 0,
+	     make_main => 0,
+	     v_flags2 => ["-DPUB_FUNC --trace --exe t/$Last_Self->{name}.cpp"],
+	     );
+
+    execute (
+	     check_finished=>1,
+	     );
+
+    ok(vcd_identical ("obj_dir/$Last_Self->{name}_simx.vcd",
+		      "t/$Last_Self->{name}.out"));
+}
+else {
+    ok(1);
+}
+1;

test_regress/t/t_trace_public_sig.cpp

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+#include <verilated.h>
+#include <SpTraceVcdC.h>
+
+#include "Vt_trace_public_sig.h"
+#include "Vt_trace_public_sig_t.h"
+#include "Vt_trace_public_sig_glbl.h"
+
+unsigned long long main_time = 0;
+double sc_time_stamp() {
+    return (double)main_time;
+}
+
+const unsigned long long dt_2 = 3;
+
+int main(int argc, char **argv, char **env) {
+    Vt_trace_public_sig *top = new Vt_trace_public_sig();
+
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+
+    SpTraceVcdCFile* tfp = new SpTraceVcdCFile;
+    top->trace(tfp,99);
+    tfp->open("obj_dir/t_trace_public_sig_simx.vcd");
+
+    while (main_time <= 20) {
+	top->CLK   = (main_time/dt_2)%2;
+	top->eval();
+
+	top->v->glbl->GSR = (main_time < 7);
+
+	tfp->dump((unsigned int)(main_time));
+	++main_time;
+    }
+    tfp->close();
+    top->final();
+    printf ("*-* All Finished *-*\n");
+    return 0;
+}

test_regress/t/t_trace_public_sig.out

@@ -0,0 +1,53 @@
+$version Generated by SpTraceVcd $end
+$date Wed Jun 11 19:43:32 2008
+ $end
+$timescale 1ns $end
+
+ $scope module TOP $end
+  $var wire  1 $ CLK $end
+  $var wire  1 % RESET $end
+  $scope module v $end
+   $var wire  1 $ CLK $end
+   $var wire  1 # RESET $end
+   $scope module glbl $end
+    $var wire  1 & GSR $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+1#
+0$
+1%
+1&
+#1
+#2
+#3
+1$
+#4
+#5
+#6
+0$
+#7
+0&
+#8
+#9
+0#
+1$
+0%
+#10
+#11
+#12
+0$
+#13
+#14
+#15
+1$
+#16
+#17
+#18
+0$
+#19
+#20

test_regress/t/t_trace_public_sig.pl

@@ -0,0 +1,28 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_public.v");
+
+if ($Last_Self->{v3}) {
+    compile (
+	     make_top_shell => 0,
+	     make_main => 0,
+	     v_flags2 => ["--trace --exe t/$Last_Self->{name}.cpp"],
+	     );
+
+    execute (
+	     check_finished=>1,
+	     );
+
+    ok(vcd_identical ("obj_dir/$Last_Self->{name}_simx.vcd",
+		      "t/$Last_Self->{name}.out"));
+}
+else {
+    ok(1);
+}
+1;