Fixed tracing of SystemC w/o SystemPerl

git-svn-id: file://localhost/svn/verilator/trunk/verilator@975 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -8,6 +8,8 @@ indicates the contributor was also the author of the fix; Thanks!
 **** Wide VL_CONST_W_#X functions are now made automatically. [Bernard Deadman]
      In such cases, a new {prefix}__Inlines.h file will be built and included.
 
+**** Fixed tracing of SystemC w/o SystemPerl. [Bernard Deadman]
+
 * Verilator 3.655 11/27/2007
 
 ***  Support "#delay <statement>;" with associated STMTDLY warning.

bin/verilator

@@ -538,9 +538,12 @@ Creates a dump file with statistics on the design in {prefix}__stats.txt.
 
 =item --trace
 
-Adds waveform tracing code to the model.  Having tracing compiled in may
-result in some small performance losses, even when waveforms are not turned
-on during model execution.
+Adds waveform tracing code to the model, this will create additional
+{prefix}__Trace*.cpp files you will need to add to your Makefiles, if
+you're not using the ones generated for you.
+
+Having tracing compiled in may result in some small performance losses,
+even when waveforms are not turned on during model execution.
 
 =item --trace-depth I<levels>
 

include/verilated.mk.in

@@ -77,7 +77,6 @@ VM_SUPPORT += $(VM_SUPPORT_FAST) $(VM_SUPPORT_SLOW)
 ifeq ($(VM_SP_OR_SC),1)
   CPPFLAGS += $(SYSTEMC_CXX_FLAGS) -I$(SYSTEMC)/include
   LDFLAGS  += $(SYSTEMC_CXX_FLAGS) -L$(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)
-  LIBS     += -lm -lstdc++
   SC_LIBS   = -lsystemc
  ifneq ($(wildcard $(SYSTEMC)/lib-$(VM_SC_TARGET_ARCH)/*numeric_bit*),)
   # Systemc 1.2.1beta
@@ -91,6 +90,7 @@ endif
 ifeq ($(VM_SP),1)
   CPPFLAGS += -I$(SYSTEMPERL)/src -DSYSTEMPERL
   VPATH    +=   $(SYSTEMPERL)/src
+  LIBS   += -lm -lstdc++
 
   VK_CLASSES_SP = $(addsuffix .sp, $(VM_CLASSES))
 
@@ -103,6 +103,17 @@ else
   preproc:
 endif
 
+#######################################################################
+##### SystemC w/o SystemPerl builds
+
+ifeq ($(VM_SC),1)
+  LIBS   += -lm -lstdc++
+ ifeq ($(VM_TRACE),1)
+  CPPFLAGS += -I$(SYSTEMPERL)/src
+  VPATH    +=   $(SYSTEMPERL)/src
+ endif
+endif
+
 #######################################################################
 ##### C/H builds
 

src/V3EmitC.cpp

@@ -1529,9 +1529,9 @@ void EmitCImp::emitInt(AstModule* modp) {
     } else {
 	puts(modClassName(modp)+"(const char* name=\"TOP\");\n");
 	puts("~"+modClassName(modp)+"();\n");
-	if (v3Global.opt.trace()) {
-	    puts("void\ttrace (SpTraceVcdCFile* tfp, int levels, int options=0);\n");
-	}
+    }
+    if (v3Global.opt.trace() && !optSystemPerl()) {
+	puts("void\ttrace (SpTraceVcdCFile* tfp, int levels, int options=0);\n");
     }
     puts("void\t__Vconfigure("+symClassName()+"* symsp);\n");
     if (optSystemPerl()) puts("/*AUTOMETHODS*/\n");
@@ -1617,7 +1617,7 @@ void EmitCImp::emitImp(AstModule* modp) {
     }
 
     if (m_fast && m_splitFilenum==0) {
-	if (v3Global.opt.trace() && optSystemC() && m_modp->isTop()) {
+	if (v3Global.opt.trace() && optSystemPerl() && m_modp->isTop()) {
 	    puts("\n");
 	    puts("\n/*AUTOTRACE(__MODULE__,recurse,activity,exists)*/\n\n");
 	}
@@ -1704,7 +1704,7 @@ class EmitCTrace : EmitCStmts {
     // METHODS
     void emitTraceHeader() {
 	// Includes
-	if (optSystemC()) {
+	if (optSystemPerl()) {
 	    puts("#include \"SpTraceVcd.h\"\n");
 	}
 	puts("#include \"SpTraceVcdC.h\"\n");
@@ -1716,7 +1716,7 @@ class EmitCTrace : EmitCStmts {
 	puts("\n//======================\n\n");
 
 	puts("void "+topClassName()+"::trace (");
-	if (optSystemC()) {
+	if (optSystemPerl()) {
 	    puts("SpTraceFile* tfp, int, int) {\n");
 	} else {
 	    puts("SpTraceVcdCFile* tfp, int, int) {\n");

src/V3PreLex.l

@@ -76,7 +76,7 @@ psl		[p]sl
 <INITIAL>^{ws}*"`line"{ws}+.*{crnl}	{ V3PreLex::s_currentLexp->lineDirective(yytext);
 					  return(VP_LINE); }
 
-	/* Special directives we recognise */
+	/* Special directives we recognize */
 <INITIAL>"`include"	{ return(VP_INCLUDE); }
 <INITIAL>"`ifdef"	{ return(VP_IFDEF); }
 <INITIAL>"`ifndef"	{ return(VP_IFNDEF); }
@@ -86,7 +86,7 @@ psl		[p]sl
 <INITIAL>"`undef"	{ return(VP_UNDEF); }
 <INITIAL>"`define"	{ return(VP_DEFINE); }
 
-	/* Optional directives we recognise */
+	/* Optional directives we recognize */
 <INITIAL>"`__FILE__"	{ if (!pedantic()) {
 	    		     yytext = (char*)V3PreLex::s_currentLexp->m_curFilelinep->cfilename();
 	    		     yyleng = strlen(yytext); return (VP_TEXT);

src/verilog.l

@@ -344,7 +344,7 @@ escid	\\[^ \t\f\r\n]+
   "coverpoint"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "cross"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "dist"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
-  "endcass"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
+  "endclass"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endclocking"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endgroup"		{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}
   "endinterface"	{yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);}

test_regress/driver.pl

@@ -285,6 +285,7 @@ sub compile {
     return 1 if $self->errors;
     $self->oprint("Compile\n");
 
+    $self->{sc} = 1 if (join(' ',@{$param{v_flags}},@{$param{v_flags2}}) =~ /-sc\b/);
     $self->{sp} = 1 if (join(' ',@{$param{v_flags}},@{$param{v_flags2}}) =~ /-sp\b/);
     $self->{trace} = 1 if (join(' ',@{$param{v_flags}},@{$param{v_flags2}}) =~ /-trace\b/);
     $self->{coverage} = 1 if (join(' ',@{$param{v_flags}},@{$param{v_flags2}}) =~ /-coverage\b/);
@@ -346,7 +347,7 @@ sub compile {
 		      @{$param{v_other_filenames}},
 		      ($param{stdout_filename}?"> ".$param{stdout_filename}:""),
 		      );
-	if ($self->sp && !defined $ENV{SYSTEMC}) {
+	if ($self->sc_or_sp && !defined $ENV{SYSTEMC}) {
 	    $self->error("Test requires SystemC; ignore error since not installed\n");
 	    return 1;
 	}
@@ -429,6 +430,15 @@ sub sp {
     return $self->{sp};
 }
 
+sub sc {
+    my $self = (ref $_[0]? shift : $Last_Self);
+    return $self->{sc};
+}
+
+sub sc_or_sp {
+    return sc($_[0]) || sp($_[0]);
+}
+
 #----------------------------------------------------------------------
 
 sub _run {
@@ -526,19 +536,19 @@ sub _make_main {
     
     print $fh "// Compile in-place for speed\n";
     print $fh "#include \"verilated.cpp\"\n";
-    print $fh "#include \"systemc.h\"\n" if $self->{sc};
+    print $fh "#include \"systemc.h\"\n" if $self->sc;
     print $fh "#include \"systemperl.h\"\n" if $self->sp;
-    print $fh "#include \"SpTraceVcdC.cpp\"\n" if $self->{trace};
-    print $fh "#include \"SpCoverage.cpp\"\n" if $self->{coverage};
+    print $fh "#include \"SpTraceVcdC.cpp\"\n" if $self->{trace} && !$self->sp;
+    print $fh "#include \"Sp.cpp\"\n"  if $self->sp;
 
     print $fh "$VM_PREFIX * topp;\n";
-    if (!$self->sp) {
+    if (!$self->sc_or_sp) {
 	print $fh "unsigned int main_time = false;\n";
 	print $fh "double sc_time_stamp () {\n";
 	print $fh "    return main_time;\n";
 	print $fh "}\n";
     }
-    if ($self->sp) {
+    if ($self->sc_or_sp) {
 	print $fh "extern int sc_main(int argc, char **argv);\n";
 	print $fh "int sc_main(int argc, char **argv) {\n";
 	print $fh "    sc_signal<bool> fastclk;\n" if $self->{inputs}{fastclk};
@@ -556,17 +566,25 @@ sub _make_main {
 	print $fh "    SP_PIN(topp,fastclk,fastclk);\n" if $self->{inputs}{fastclk};
 	print $fh "    SP_PIN(topp,clk,clk);\n" if $self->{inputs}{clk};
 	$set = "";
+    } elsif ($self->sc) {
+	print $fh "    topp->fastclk(fastclk);\n" if $self->{inputs}{fastclk};
+	print $fh "    topp->clk(clk);\n" if $self->{inputs}{clk};
+	$set = "";
     } else {
 	print $fh "    topp->eval();\n";
 	$set = "topp->";
     }
 
-    my $traceit = ($self->{trace} && !$self->{sp} && !$self->{sc});
-    if ($traceit) {
+    my $ctraceit = ($self->{trace} && !$self->{sp});
+    if ($self->{trace}) {
 	$fh->print("\n");
 	$fh->print("#if VM_TRACE\n");
 	$fh->print("    Verilated::traceEverOn(true);\n");
-	$fh->print("    SpTraceVcdCFile* tfp = new SpTraceVcdCFile;\n");
+	if ($self->{sp}) {
+	    $fh->print("    SpTraceFile* tfp = new SpTraceFile;\n");
+	} else {
+	    $fh->print("    SpTraceVcdCFile* tfp = new SpTraceVcdCFile;\n");
+	}
 	$fh->print("    topp->trace (tfp, 99);\n");
 	$fh->print("    tfp->open (\"obj_dir/".$self->{name}."_simx.vcd\");\n");
 	$fh->print("#endif\n");
@@ -585,12 +603,12 @@ sub _make_main {
 	    print $fh "	${set}clk=!${set}clk;\n";
 	    $action = 1;
 	}
-	if ($self->sp) {
+	if ($self->sc_or_sp) {
 	    print $fh "	sc_start(1);\n";
 	} else {
 	    print $fh "	main_time+=1;\n";
 	    print $fh "	${set}eval();\n" if $action;
-	    if ($traceit) {
+	    if ($ctraceit) {
 		$fh->print("#if VM_TRACE\n");
 		$fh->print("	tfp->dump (main_time);\n");
 		$fh->print("#endif //VM_TRACE\n");
@@ -604,7 +622,7 @@ sub _make_main {
     print $fh "    topp->final();\n";
     print $fh "    SpCoverage::write(\"",$self->{coverage_filename},"\");\n" if $self->{coverage};
 
-    if ($traceit) {
+    if ($self->{trace}) {
 	$fh->print("#if VM_TRACE\n");
 	$fh->print("	tfp->close();\n");
 	$fh->print("#endif //VM_TRACE\n");

test_regress/t/t_trace_ena_cc.pl

@@ -7,6 +7,8 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 
+top_filename("t/t_trace_ena.v");
+
 compile (
 	 v_flags2 => [$Last_Self->{v3}?'-trace':''],
 	 );
@@ -16,9 +18,9 @@ execute (
 	 );
 
 if ($Last_Self->{v3}) {
-    file_grep     ("obj_dir/Vt_trace_ena__Trace__Slow.cpp", qr/c_trace_on\"/x);
-    file_grep_not ("obj_dir/Vt_trace_ena__Trace__Slow.cpp", qr/_trace_off\"/x);
-    file_grep     ("obj_dir/t_trace_ena_simx.vcd", qr/\$enddefinitions/x);
+    file_grep     ("obj_dir/V$Last_Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x);
+    file_grep_not ("obj_dir/V$Last_Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x);
+    file_grep     ("obj_dir/$Last_Self->{name}_simx.vcd", qr/\$enddefinitions/x);
 }
 
 ok(1);

test_regress/t/t_trace_ena_sc.pl

@@ -0,0 +1,26 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_ena.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'-trace -sc':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+if ($Last_Self->{v3}) {
+    # Note more checks in _cc.pl
+    file_grep     ("obj_dir/$Last_Self->{name}_simx.vcd", qr/\$enddefinitions/x);
+}
+
+ok(1);
+1;

test_regress/t/t_trace_ena_sp.pl

@@ -0,0 +1,26 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_ena.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'-trace -sp':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+if ($Last_Self->{v3}) {
+    # Note more checks in _cc.pl
+    file_grep     ("obj_dir/$Last_Self->{name}_simx.vcd", qr/\$enddefinitions/x);
+}
+
+ok(1);
+1;

test_regress/t/t_trace_off_cc.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_ena.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'-notrace':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+if ($Last_Self->{v3}) {
+    !-r "obj_dir/$Last_Self->{name}_simx.vcd" or $Last_Self->error("Tracing should be off\n");
+}
+
+ok(1);
+1;

test_regress/t/t_trace_off_sc.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_ena.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'-notrace -sc':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+if ($Last_Self->{v3}) {
+    !-r "obj_dir/$Last_Self->{name}_simx.vcd" or $Last_Self->error("Tracing should be off\n");
+}
+
+ok(1);
+1;

test_regress/t/t_trace_off_sp.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_trace_ena.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'-notrace -sp':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+if ($Last_Self->{v3}) {
+    !-r "obj_dir/$Last_Self->{name}_simx.vcd" or $Last_Self->error("Tracing should be off\n");
+}
+
+ok(1);
+1;