Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@928 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,20 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.651 5/22/2007
+
+***  Added verilator_profcfunc utility.  [Gene Weber]
+
+***  Treat modules within `celldefine and `endcelldefine as if in library.
+
+***  Support functions which return integers.  [Mark Nodine]
+
+**** Warn if flex is not installed.  [Ralf Karge]
+
+**** Ignore `protect and `endprotect.
+
+**** Allow empty case/endcase blocks.
+
 * Verilator 3.650 4/20/2007
 
 **   Add --compiler msvc option.  This is now required when Verilated code

TODO

@@ -26,11 +26,11 @@ Features:
 		Points should be per-scope like everything else rather then per-module
 		Expression coverage (see notes)
 	More Verilog 2001 Support
-		C-style function and task arguments.  [Wim Michiels]
 		(* *) Attributes  (just ignore -- preprocessor?)
 		Real numbers (NEVER)
 		Recursive functions (NEVER)
 		Verilog configuration files (NEVER)
+	DPI to define C/C++ calls from Verilog
 
 Long-term Features
 	Assertions

bin/verilator

@@ -730,9 +730,9 @@ feedback driven compilation.  With GCC, using -fprofile-arcs, then
 
 You may uncover further tuning possibilities by profiling the Verilog code.
 Use Verilator's --profile-cfuncs, then GCC's -g -pg.  You can then run
-either oprofile or gprof to see where in the C++ code, and by looking at
-the mangled function name where in the Verilog code most of the time is
-being spent.
+either oprofile or gprof to see where in the C++ code the time is spent.
+Run the gprof output through verilator_profcfunc and it will tell you what
+Verilog line numbers on which most of the time is being spent.
 
 When done, please let the author know the results.  I like to keep tabs on
 how Verilator compares, and may be able to suggest additional improvements.
@@ -1434,6 +1434,14 @@ This section describes specific limitations for each language keyword.
 
 =over 4
 
+=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords,
+`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords,
+`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor,
+`systemc_dtor, `systemc_header, `systemc_imp_header,
+`systemc_implementation, `systemc_interface, `timescale, `undef, `verilog
+
+Fully supported.
+
 =item always, always_comb, always_ff, always_latch, and, assign, begin,
 buf, case, casex, casez, default, defparam, do-while, else, end, endcase,
 endfunction, endgenerate, endmodule, endspecify, endtask, final, for,
@@ -1453,8 +1461,9 @@ All specify blocks and timing checks are ignored.
 Verilator does not perform warning checking on uwires, it treats the uwire
 keyword as if it were the normal wire keyword.
 
-=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
-$readmemh, $signed, $stop, $time, $unsigned
+=item $bits, $countones, $error, $fatal, $finish, $info, $isunknown,
+$onehot, $onehot0, $readmemb, $readmemh, $signed, $stop, $time, $unsigned,
+$warning.
 
 Generally supported.
 
@@ -2069,7 +2078,7 @@ Communications, Sun Microsystems, Nauticus Networks, and SiCortex.
 
 The people who have contributed code or other major functionality are Paul
 Wasson, Duane Galbi, and Wilson Snyder.  Major testers include Jeff Dutton,
-Ralf Karge and Wim Michiels.
+Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
 
 Some of the people who have provided ideas and feedback for Verilator
 include Hans Van Antwerpen, Jens Arm, David Black, Gregg Bouchard, Chris
@@ -2096,7 +2105,7 @@ Major concepts by Paul Wasson and Duane Galbi.
 
 =head1 SEE ALSO
 
-L<systemperl>, L<vcoverage>, L<make>
+L<verilator_profcfunc>, L<systemperl>, L<vcoverage>, L<make>
 
 =cut
 

bin/verilator_difftree

@@ -35,12 +35,13 @@ my $Opt_A;
 my $Opt_B;
 autoflush STDOUT 1;
 autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
 if (! GetOptions (
 		  "help"	=> \&usage,
 		  "debug"	=> \&debug,
 		  "<>"		=> \&parameter,
 		  )) {
-    usage();
+    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
 }
 
 defined $Opt_A or die "%Error: No old diff filename\n";

bin/verilator_profcfunc

@@ -0,0 +1,211 @@
+: # -*-Mode: perl;-*- use perl, wherever it is
+eval 'exec perl -wS $0 ${1+"$@"}'
+  if 0;
+# $Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use warnings;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+
+
+#======================================================================
+# main
+
+$Debug = 0;
+my $Opt_File;
+autoflush STDOUT 1;
+autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
+if (! GetOptions (
+		  "help"	=> \&usage,
+		  "debug"	=> \&debug,
+		  "<>"		=> \&parameter,
+		  )) {
+    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
+}
+
+defined $Opt_File or die "%Error: No filename given\n";
+
+profcfunc($Opt_File);
+
+#----------------------------------------------------------------------
+
+sub usage {
+    print '$Id$ ', "\n";
+    pod2usage(-verbose=>2, -exitval => 2);
+    exit (1);
+}
+
+sub debug {
+    $Debug = 1;
+}
+
+sub parameter {
+    my $param = shift;
+    if (!defined $Opt_File) {
+	$Opt_File = $param;
+    } else {	
+	die "%Error: Unknown parameter: $param\n";
+    }
+}
+
+#######################################################################
+
+sub profcfunc {
+    my $filename = shift;
+    # Remove hex numbers before diffing
+    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
+
+    my %funcs;
+
+    while (defined (my $line=$fh->getline())) {
+	if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+.*\s+(\S+)\s*$/) {
+	    my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
+	    $funcs{$func}{pct} += $pct;
+	    $funcs{$func}{sec} += $sec;
+	    $funcs{$func}{calls} += $calls;
+	}
+    }
+    $fh->close;
+
+    # Find modules
+    my %verilated_mods;
+    foreach my $func (keys %funcs) {
+	if ($func =~ /(.*)::_eval\(.*__Syms.*\)$/) {
+	    $verilated_mods{$1} = qr/^$1/;
+	}
+    }
+
+    # Resort by Verilog name
+    my %vfuncs;
+    my %groups;
+    foreach my $func (keys %funcs) {
+	my $vfunc = $func;
+	my $design;
+	foreach my $vde (keys %verilated_mods) {
+	    if ($func =~ /$verilated_mods{$vde}/) {
+		$design=$vde;
+		last;
+	    }
+	}
+	if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__([0-9]+)\(/) {
+	    $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
+	    $groups{"Verilog Blocks under $design"} += $funcs{$func}{pct};
+	} else {
+	    if ($design) {
+		$vfunc = sprintf("VCommon   %s", $func);
+		$groups{"Common code under $design"} += $funcs{$func}{pct};
+	    } else {
+		$vfunc = sprintf("C++       %s", $func);
+		$groups{'C++'} += $funcs{$func}{pct};
+	    }
+	}
+	$vfuncs{$vfunc} = $funcs{$func};
+    }
+
+    print("Overall summary:\n");
+    print("  % time\n");
+    foreach (sort (keys %groups)) {
+	printf("  %6.2f  In all %s\n", $groups{$_}, $_);
+    }
+    print("\n");
+
+
+    print("Verilog code profile:\n");
+    print("   These are split into three categories:\n");
+    print("      C++:     Time in non-Verilated C++ code\n");
+    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
+    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
+    print("\n");
+
+    print("  %   cumulative   self              \n");
+    print(" time   seconds   seconds    calls   type      filename and line number\n");
+
+    my $cume = 0;
+    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
+			    || $a cmp $b}
+		      (keys %vfuncs)) {
+	$cume += $vfuncs{$func}{sec};
+	printf +("%6.2f %9.2f %8.2f %8d   %s\n",
+		 $vfuncs{$func}{pct},
+		 $cume, $vfuncs{$func}{sec},
+		 $vfuncs{$func}{calls},
+		 $func);
+    }
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+verilator_profcfunc - Read gprof report created with --profile-cfuncs
+
+=head1 SYNOPSIS
+
+  verilator --profile-cfuncs ....
+  gcc --ggdb -pg ....
+  {run executable}
+  gprof
+  verilator_profcfuncs gprof.out
+
+=head1 DESCRIPTION
+
+Verilator_profcfunc reads a profile report created by gprof.  The names of
+the functions are then transformed, assuming the user used verilator's
+--profile-cfuncs, and a report printed showing the percentage of time, etc,
+in each Verilog block.
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+The latest version is available from L<http://www.veripool.com/>.
+
+Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+C<verilator>
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
+### End:

configure.ac

@@ -16,8 +16,17 @@ AC_PROG_CC
 AC_PROG_CXX
 AC_PROG_INSTALL
 AC_PATH_PROG(PERL,perl)
-AC_PATH_PROG(YACC,bison)
+if test "x$PERL" = "x" ; then
+   AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
+fi
 AC_PATH_PROG(LEX,flex)
+if test "x$LEX" = "x" ; then
+   AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it])
+fi
+AC_PATH_PROG(YACC,bison)
+if test "x$YACC" = "x" ; then
+   AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it])
+fi
 
 dnl Checks for libraries.
 

nodist/bisonreader

@@ -0,0 +1,67 @@
+#!/usr/bin/perl -w
+#$Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of either the GNU General Public License or the
+# Perl Artistic License.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the Perl Artistic License
+# along with this module; see the file COPYING.  If not, see
+# www.cpan.org
+#                                                                           
+######################################################################
+
+# DESCRIPTION: Debugging of bison output
+
+use strict;
+
+my $Debug;
+
+my %declared;
+my %used;
+
+my $body = 0;
+my $rule = "";
+my $lineno = 0;
+foreach my $line (<STDIN>) {
+    $lineno++;
+    chomp $line;
+    $line =~ s!//.*$!!g;
+    $line =~ s!\s+! !g;
+    next if $line eq '';
+    if ($line =~ m!^\%\%!) {
+	$body++;
+    } elsif ($body == 1) {
+	$rule .= $line;
+	if ($line =~ m!^\s*;\s*$!) {
+	    #print "Rule: $rule\n";
+	    ($rule =~ /^([a-zA-Z0-9_]+):(.*)$/) or die "%Error: No rule name: $1\n";
+	    my $rulename = $1; my $preaction = $2;
+	    $declared{$rulename} = $lineno;
+	    $preaction =~ s/\{[^\}]*\}/ /g;
+	    #print "RULEN $rulename PA $preaction\n" if $Debug;
+	    $rule = '';
+	    foreach my $ref (split /\s+/, $preaction) {
+		next if $ref !~ /^[a-zA-Z]/;
+		next if $ref eq $rulename;
+		if (!$used{$ref} && $declared{$ref}) {
+		    print "   %Warning: $lineno: $ref used by $rulename after declaration\n";
+		}
+		$used{$ref} = $lineno;
+		print "  ref $ref\n" if $Debug;
+	    }
+	}
+    }
+}
+
+# Local Variables:
+# compile-command: "./bisonreader < verilog.y"
+# End:

src/V3Ast.h

@@ -999,7 +999,7 @@ private:
     AstNodeFTask*	m_taskp;	// [AfterLink] Pointer to task referenced
     string		m_name;		// Name of variable
     string		m_dotted;	// Dotted part of scope to task or ""
-    string		m_inlinedDots;	// Dotted hiearchy flattened out
+    string		m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
 	:AstNode(fl)

src/V3AstNodes.h

@@ -421,7 +421,7 @@ struct AstScope : public AstNode {
 private:
     string	m_name;		// Name
     AstScope*	m_aboveScopep;	// Scope above this one in the hierarchy (NULL if top)
-    AstCell*	m_aboveCellp;	// Cell above this in the hiearchy (NULL if top)
+    AstCell*	m_aboveCellp;	// Cell above this in the hierarchy (NULL if top)
     AstModule*	m_modp;		// Module scope corresponds to
 public:
     AstScope(FileLine* fl, AstModule* modp, const string& name,
@@ -540,7 +540,7 @@ struct AstVarXRef : public AstNodeVarRef {
     // Includes pin on a cell, as part of a ASSIGN statement to connect I/Os until AstScope
 private:
     string	m_dotted;	// Scope name to connected to
-    string	m_inlinedDots;	// Dotted hiearchy flattened out
+    string	m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstVarXRef(FileLine* fl, const string& name, const string& dotted, bool lvalue)
 	:AstNodeVarRef(fl, name, NULL, lvalue)

src/V3Case.cpp

@@ -62,9 +62,6 @@ private:
     //int debug() { return 9; }
 
     virtual void visit(AstNodeCase* nodep, AstNUser*) {
-	// We report a syntax error on empty "case (x) endcase" blocks, so never no items at all
-	if (!nodep->itemsp()) nodep->v3fatalSrc("No items (not even default) under case statement?\n");
-
 	// Detect multiple defaults
 	bool hitDefault = false;
 	for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {

src/V3LinkDot.cpp

@@ -21,7 +21,7 @@
 // LinkDot TRANSFORMATIONS:
 //	Top-down traversal
 //	    Cells:
-//		Make graph of cell hiearchy
+//		Make graph of cell hierarchy
 //	    Var/Funcs's:
 //		Collect all names into symtable under appropriate cell
 //	Top-down traversal
@@ -180,7 +180,7 @@ private:
     // TYPES
     typedef std::multimap<string,LinkDotCellVertex*> NameScopeMap;
     // MEMBERS
-    LinkDotGraph	m_graph;		// Graph of hiearchy
+    LinkDotGraph	m_graph;		// Graph of hierarchy
     NameScopeMap	m_nameScopeMap;		// Hash of scope referenced by non-pretty textual name
     bool		m_forPrearray;		// Compress cell__[array] refs
     bool		m_forScopeCreation;	// Remove VarXRefs for V3Scope
@@ -277,7 +277,7 @@ private:
 public:
     LinkDotBaseVertex* findDotted(LinkDotBaseVertex* cellVxp, const string& dotname,
 				  string& baddot, LinkDotBaseVertex*& okVxp) {
-	// Given a dotted hiearchy name, return where in scope it is
+	// Given a dotted hierarchy name, return where in scope it is
 	// Note when dotname=="" we just fall through and return cellVxp
 	UINFO(8,"    dottedFind "<<dotname<<endl);
 	bool firstId = true;
@@ -520,8 +520,8 @@ private:
     virtual void visit(AstScope* nodep, AstNUser*) {
 	UINFO(8,"  SCOPE "<<nodep<<endl);
 	if (!m_statep->forScopeCreation()) v3fatalSrc("Scopes should only exist right after V3Scope");
-	// Using the CELL names, we created all hiearchy.  We now need to match this Scope
-	// up with the hiearchy created by the CELL names.
+	// Using the CELL names, we created all hierarchy.  We now need to match this Scope
+	// up with the hierarchy created by the CELL names.
 	m_cellVxp = m_statep->findScope(nodep);
 	nodep->iterateChildren(*this);
 	m_cellVxp = NULL;
@@ -610,7 +610,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->varp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->varp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;
@@ -657,7 +657,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->taskp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->taskp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;

src/V3PreLex.l

@@ -57,6 +57,9 @@ static void pslMoreNeeded(bool flag) { V3PreLex::s_currentLexp->m_pslMoreNeeded
 %x DEFMODE
 %x ARGMODE
 %x INCMODE
+%x PRTMODE
+
+/* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
 
 ws		[ \t\f\r]
 wsn		[ \t\f]
@@ -64,6 +67,7 @@ crnl		[\r]*[\n]
 quote		[\"]
 backslash	[\\]
 symb		[a-zA-Z_][a-zA-Z0-9_$]*
+drop		[\032]
 psl		[p]sl
 
 	/**************************************************************/
@@ -103,6 +107,13 @@ psl		[p]sl
 			  if (V3PreLex::s_currentLexp->m_parenLevel) appendDefValue(yytext,yyleng);
 			  else return (VP_STRING); }
 
+	/* Protected blocks */
+<INITIAL>"`protected"	{ yy_push_state(PRTMODE); yymore(); }
+<PRTMODE><<EOF>>	{ linenoInc(); yyerror("EOF in `protected"); yyleng=0; yyterminate(); }
+<PRTMODE>{crnl}		{ linenoInc(); yymore(); }
+<PRTMODE>.	 	{ yymore(); }
+<PRTMODE>"`endprotected" { yy_pop_state(); return (VP_TEXT); }
+
 	/* Pass-through include <> filenames */
 <INCMODE><<EOF>>	{ linenoInc(); yyerror("EOF in unterminated include filename"); yyleng=0; yyterminate(); }
 <INCMODE>{crnl}		{ linenoInc(); yyerror("Unterminated include filename"); BEGIN(INITIAL); }
@@ -113,6 +124,7 @@ psl		[p]sl
 	/* Reading definition */
 <DEFMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <DEFMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<DEFMODE>{drop}		{ }
 <DEFMODE><<EOF>>	{ linenoInc(); yyerror("EOF (missing return?) in define value"); yyleng=0; yyterminate(); }
 <DEFMODE>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); }
 <DEFMODE>[\\]{crnl}	{ linenoInc(); appendDefValue("\n",1); } /* Include return so can maintain output line count */
@@ -123,6 +135,7 @@ psl		[p]sl
 	/* Define arguments */
 <ARGMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <ARGMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<ARGMODE>{drop}		{ }
 <ARGMODE><<EOF>>	{ yyerror("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
 <ARGMODE>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <ARGMODE>{quote}	{ yy_push_state(STRMODE); yymore(); }
@@ -179,8 +192,9 @@ psl		[p]sl
 	/* Generics */
 <INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{symb}	{ return (VP_SYMBOL); }
-<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>{wsn}+	{ return (VP_WHITE); }
+<INITIAL,PSLMULM,PSLONEM>{drop}	{ }
+<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>.	{ return (VP_TEXT); }
 %%
 

src/V3PreShell.cpp

@@ -61,12 +61,6 @@ protected:
 	    s_preprocp->define(prefl,"verilator3", "1");
 	    s_preprocp->define(prefl,"systemc_clock", "/*verilator systemc_clock*/");
 	    s_preprocp->define(prefl,"coverage_block_off", "/*verilator coverage_block_off*/");
-	    // Standards - We ignore
-	    s_preprocp->define(prefl,"endcelldefine", "");
-	    s_preprocp->define(prefl,"celldefine", "");
-	    s_preprocp->define(prefl,"resetall", "");
-	    s_preprocp->define(prefl,"portcoerce", "");
-	    s_preprocp->define(prefl,"inline", "");
 	}
     }
 

src/V3Read.h

@@ -38,7 +38,8 @@ class V3Read {
     V3Lexer*	m_lexerp;	// Current FlexLexer
     static V3Read*	s_readp;	// Current THIS, bison() isn't class based
     FileLine*	m_fileline;	// Filename/linenumber currently active
-    bool	m_inLibrary;	// Currently reading a library vs. regular file
+    bool	m_inCellDefine;		// Inside a `celldefine
+    bool	m_inLibrary;		// Currently reading a library vs. regular file
     int		m_inBeginKwd;		// Inside a `begin_keywords
     int		m_lastVerilogState;	// Last LEX state in `begin_keywords
     deque<string*> m_stringps;		// Created strings for later cleanup
@@ -92,6 +93,8 @@ public: // But for internal use only
     static FileLine* fileline() { return s_readp->m_fileline; }
     static AstNetlist* rootp() { return s_readp->m_rootp; }
     static FileLine* copyOrSameFileLine() { return s_readp->fileline()->copyOrSameFileLine(); }
+    static bool inCellDefine() { return s_readp->m_inCellDefine; }
+    static void inCellDefine(bool flag) { s_readp->m_inCellDefine = flag; }
     static bool inLibrary() { return s_readp->m_inLibrary; }
     static void stateExitPsl();	// Parser -> lexer communication
     static void statePushVlg();	// Parser -> lexer communication
@@ -102,6 +105,7 @@ public:
     // CREATORS
     V3Read(AstNetlist* rootp) {
 	m_rootp = rootp; m_lexerp = NULL;
+	m_inCellDefine = false;
 	m_inLibrary = false;
 	m_inBeginKwd = 0;
 	m_lastVerilogState = stateVerilogRecent();

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.650 4/20/2007"
+#define DTVERSION	"Verilator 3.651 4/20/2007"
 
 //**********************************************************************
 //**** Functions

src/flexfix

@@ -19,7 +19,7 @@
 #                                                                           
 ######################################################################
 
-# DESCRIPTION: Edits flex output to get around Redhat 8.0 broken flex.
+# DESCRIPTION: Edits flex output to get around various broken flex issues.
 
 foreach my $line (<STDIN>) {
     # Fix flex 2.5.4 namespace omission
@@ -28,5 +28,9 @@ foreach my $line (<STDIN>) {
     $line =~ s!(\#define\s+yyFlexLexer\s+yyFlexLexer)!//flexfix: $1!g;
     # Fix flex 2.5.1 yytext_ptr undef
     $line =~ s!(\#undef\s+yytext_ptr)!//flexfix: $1!g;
+    # Fix flex 2.5.4 and GCC 4.1.0 warn_unused_result
+    $line =~ s!\(void\) *fwrite\((.*)\)!if (fwrite($1)) {}!g;
+    # Fix flex 2.5.33 and GCC 4.1.2 "warning: comparison between signed and unsigned integer expressions" in YY_INPUT
+    $line =~ s!for \( n = 0; n < max_size && !for ( n = 0; ((size_t)n < (size_t)max_size) && !g;
     print "$line";
 }

src/verilog.l

@@ -104,11 +104,12 @@ void yyerrorf(const char* format, ...) {
 %o 25000
 
 %s V95 V01 V05 S05
-%s PSL STRING
+%s PSL STRING ATTRMODE
 %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
 %s IGNORE
 
 ws	[ \t\f\r]+
+wsnr	[ \t\f]+
 	/* identifier */
 id	[a-zA-Z_][a-zA-Z0-9_$]*
 	/* escaped identifier */
@@ -130,38 +131,39 @@ escid	\\[^ \t\f\r\n]+
   "$fdisplay"		{yylval.fileline = CRELINE(); return yD_FDISPLAY;}
   "$finish"		{yylval.fileline = CRELINE(); return yD_FINISH;}
   "$fopen"		{yylval.fileline = CRELINE(); return yD_FOPEN;}
-  "$fullskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$fullskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$fwrite"		{yylval.fileline = CRELINE(); return yD_FWRITE;}
-  "$hold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$nochange"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$period"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$hold"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$nochange"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$period"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$readmemb"		{yylval.fileline = CRELINE(); return yD_READMEMB;}
   "$readmemh"		{yylval.fileline = CRELINE(); return yD_READMEMH;}
   "$realtime"		{yylval.fileline = CRELINE(); return yD_TIME;}
-  "$recovery"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$recrem"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$removal"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$setup"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$setuphold"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$skew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$recovery"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$recrem"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$removal"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$setup"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$setuphold"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$skew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$stop"		{yylval.fileline = CRELINE(); return yD_STOP;}
   "$time"		{yylval.fileline = CRELINE(); return yD_TIME;}
-  "$timeskew"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
-  "$width"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "$timeskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "$width"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$write"		{yylval.fileline = CRELINE(); return yD_WRITE;}
   /*     Keywords */
   "always"		{yylval.fileline = CRELINE(); return yALWAYS;}
   "and"			{yylval.fileline = CRELINE(); return yAND;}
   "assign"		{yylval.fileline = CRELINE(); return yASSIGN;}
-  "begin"		{yylval.fileline = CRELINE(); return yBBEGIN;}
+  "begin"		{yylval.fileline = CRELINE(); return yBEGIN;}
   "buf"			{yylval.fileline = CRELINE(); return yBUF;}
   "case"		{yylval.fileline = CRELINE(); return yCASE;}
   "casex"		{yylval.fileline = CRELINE(); return yCASEX;}
   "casez"		{yylval.fileline = CRELINE(); return yCASEZ;}
   "default"		{yylval.fileline = CRELINE(); return yDEFAULT;}
   "defparam"		{yylval.fileline = CRELINE(); return yDEFPARAM;}
+  "edge"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "else"		{yylval.fileline = CRELINE(); return yELSE;}
-  "end"			{yylval.fileline = CRELINE(); return yBEND;}
+  "end"			{yylval.fileline = CRELINE(); return yEND;}
   "endcase"		{yylval.fileline = CRELINE(); return yENDCASE;}
   "endfunction"		{yylval.fileline = CRELINE(); return yENDFUNCTION;}
   "endmodule"		{yylval.fileline = CRELINE(); return yENDMODULE;}
@@ -182,12 +184,12 @@ escid	\\[^ \t\f\r\n]+
   "not"			{yylval.fileline = CRELINE(); return yNOT;}
   "or"			{yylval.fileline = CRELINE(); return yOR;}
   "output"		{yylval.fileline = CRELINE(); return yOUTPUT;}
-  "parameter"		{yylval.fileline = CRELINE(); return yPARAM;}
+  "parameter"		{yylval.fileline = CRELINE(); return yPARAMETER;}
   "posedge"		{yylval.fileline = CRELINE(); return yPOSEDGE;}
   "reg"			{yylval.fileline = CRELINE(); return yREG;}
   "scalared"		{yylval.fileline = CRELINE(); return ySCALARED;}
   "specify"		{yylval.fileline = CRELINE(); return ySPECIFY;}
-  "specparam"		{yylval.fileline = CRELINE(); return yTIMINGSPEC;}
+  "specparam"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "supply0"		{yylval.fileline = CRELINE(); return ySUPPLY0;}
   "supply1"		{yylval.fileline = CRELINE(); return ySUPPLY1;}
   "task"		{yylval.fileline = CRELINE(); return yTASK;}
@@ -216,7 +218,6 @@ escid	\\[^ \t\f\r\n]+
   "cmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "deassign"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "disable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
-  "edge"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endprimitive"	{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endtable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "event"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
@@ -273,30 +274,30 @@ escid	\\[^ \t\f\r\n]+
   "$signed"		{yylval.fileline = CRELINE(); return yD_SIGNED;}
   "$unsigned"		{yylval.fileline = CRELINE(); return yD_UNSIGNED;}
   /*     Keywords */
+  "automatic"		{yylval.fileline = CRELINE(); return yAUTOMATIC;}
   "endgenerate"		{yylval.fileline = CRELINE(); return yENDGENERATE;}
   "generate"		{yylval.fileline = CRELINE(); return yGENERATE;}
   "genvar"		{yylval.fileline = CRELINE(); return yGENVAR;}
+  "ifnone"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "localparam"		{yylval.fileline = CRELINE(); return yLOCALPARAM;}
+  "noshowcancelled"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "pulsestyle_ondetect"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "pulsestyle_onevent"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
+  "showcancelled"	{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "signed"		{yylval.fileline = CRELINE(); return ySIGNED;}
+  "unsigned"		{yylval.fileline = CRELINE(); return yUNSIGNED;}
   /*     Special errors */
-  "include"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented; probably you want `include instead: %s",yytext);}
+  "include"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s",yytext);}
   /*     Generic unsupported warnings */
-  "automatic"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "cell"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "config"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "design"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "endconfig"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "ifnone"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "incdir"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "instance"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "liblist"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "library"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "noshowcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "pulsestyle_ondetect"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "pulsestyle_onevent"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "showcancelled"	{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "unsigned"		{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
-  "use"			{yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
+  "cell"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "config"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "design"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "endconfig"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "incdir"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "instance"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "liblist"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "library"		{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
+  "use"			{yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);}
 }
 
   /* Verilog 2005 */
@@ -552,45 +553,45 @@ escid	\\[^ \t\f\r\n]+
 
   /* Verilog 1995 Operators */
 <V95,V01,V05,S05,PSL>{
-  "&&"			{yylval.fileline = CRELINE(); return yANDAND;}
-  "||"			{yylval.fileline = CRELINE(); return yOROR;}
-  "<="			{yylval.fileline = CRELINE(); return yLTE;}
-  ">="			{yylval.fileline = CRELINE(); return yGTE;}
-  "<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
-  ">>"			{yylval.fileline = CRELINE(); return ySRIGHT;}
-  "=="			{yylval.fileline = CRELINE(); return yEQUAL;}
-  "!="			{yylval.fileline = CRELINE(); return yNOTEQUAL;}
-  "==="			{yylval.fileline = CRELINE(); return yCASEEQUAL;}
-  "!=="			{yylval.fileline = CRELINE(); return yCASENOTEQUAL;}
-  "^~"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
-  "~^"			{yylval.fileline = CRELINE(); return yOP_XNOR;}
-  "~&"			{yylval.fileline = CRELINE(); return yOP_NAND;}
-  "~|"			{yylval.fileline = CRELINE(); return yOP_NOR;}
+  "&&"			{yylval.fileline = CRELINE(); return yP_ANDAND;}
+  "||"			{yylval.fileline = CRELINE(); return yP_OROR;}
+  "<="			{yylval.fileline = CRELINE(); return yP_LTE;}
+  ">="			{yylval.fileline = CRELINE(); return yP_GTE;}
+  "<<"			{yylval.fileline = CRELINE(); return yP_SLEFT;}
+  ">>"			{yylval.fileline = CRELINE(); return yP_SRIGHT;}
+  "=="			{yylval.fileline = CRELINE(); return yP_EQUAL;}
+  "!="			{yylval.fileline = CRELINE(); return yP_NOTEQUAL;}
+  "==="			{yylval.fileline = CRELINE(); return yP_CASEEQUAL;}
+  "!=="			{yylval.fileline = CRELINE(); return yP_CASENOTEQUAL;}
+  "^~"			{yylval.fileline = CRELINE(); return yP_XNOR;}
+  "~^"			{yylval.fileline = CRELINE(); return yP_XNOR;}
+  "~&"			{yylval.fileline = CRELINE(); return yP_NAND;}
+  "~|"			{yylval.fileline = CRELINE(); return yP_NOR;}
 }
 
   /* Verilog 2001 Operators */
 <V01,V05,S05,PSL>{
-  "<<<"			{yylval.fileline = CRELINE(); return ySLEFT;}
-  ">>>"			{yylval.fileline = CRELINE(); return ySSRIGHT;}
-  "**"			{yylval.fileline = CRELINE(); return yPOW;}
-  "+:"			{yylval.fileline = CRELINE(); return yPLUSCOLON;}
-  "-:"			{yylval.fileline = CRELINE(); return yMINUSCOLON;}
+  "<<<"			{yylval.fileline = CRELINE(); return yP_SLEFT;}
+  ">>>"			{yylval.fileline = CRELINE(); return yP_SSRIGHT;}
+  "**"			{yylval.fileline = CRELINE(); return yP_POW;}
+  "+:"			{yylval.fileline = CRELINE(); return yP_PLUSCOLON;}
+  "-:"			{yylval.fileline = CRELINE(); return yP_MINUSCOLON;}
 }
 
   /* PSL Operators */
 <PSL>{
   "{"			{yylval.fileline = CRELINE(); return yPSL_BRA;}	// Avoid parser hitting concatenate.
   "}"			{yylval.fileline = CRELINE(); return yPSL_KET;}	// Avoid parser hitting concatenate.
-  "->"			{yylval.fileline = CRELINE(); return yOP_LOGIF;}
+  "->"			{yylval.fileline = CRELINE(); return yP_LOGIF;}
   "<->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools
-  "[*"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR
-  "[*]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_STAR_KET
-  "[+]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_PLUS_KET
-  "[->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT
-  "[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_MINUS_GT_KET
-  "[="			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yBRA_EQ
-  "|->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_MINUS_GT
-  "|=>"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yOR_EQ_GT
+  "[*"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR
+  "[*]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR_KET
+  "[+]"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_PLUS_KET
+  "[->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT
+  "[->]"		{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT_KET
+  "[="			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_EQ
+  "|->"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_MINUS_GT
+  "|=>"			{yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_EQ_GT
 }
 
   /* Identifiers and numbers */
@@ -604,45 +605,42 @@ escid	\\[^ \t\f\r\n]+
 			   } else {
 			       yylval.strp = V3Read::newString(yytext); // Need _ as "6..." isn't legal ID
 			   }
-			   return yID;
+			   return yaID;
 			 }
 
   {id}			{  yylval.strp = V3Read::newString(yytext);
-			   return yID;
+			   return yaID;
 			 }
 
   \"[^\"\\]*\"		{  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
-			   return ySTRING;
+			   return yaSTRING;
 			}
   \" 			{ yy_push_state(STRING); yymore(); }
 
 
   [0-9]*?['']s?[bcodhBCODH][ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
   [0-9]*?['']s?[01xXzZ]	{	/* SystemVerilog */
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
-  [0-9]+[_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
+  [0-9][_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]*	{
 			  yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+                          return yaINTNUM;
 			}
-  [0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
-                          return yINTNUM;
+  [0-9][_0-9]*		{ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
+                          return yaINTNUM;
 			}
-  [-+]?[0-9]+(\.[0-9]+)([eE][-+]?[0-9]+)? {
+  [0-9][_0-9]*(\.[_0-9]+)([eE][-+]?[_0-9]+)? {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
-                          return yFLOATNUM;
+                          return yaFLOATNUM;
 			}
-  [-+]?[0-9]+(\.[0-9]+)?([eE][-+]?[0-9]+) {
+  [0-9][_0-9]*(\.[_0-9]+)?([eE][-+]?[_0-9]+) {
     			  yylval.cdouble = 0;  /* Only for delays, not used yet */
-                          return yFLOATNUM;
+                          return yaFLOATNUM;
 			}
-
-  "`timescale"{ws}+[^\n]*	{}
-  "`line"{ws}+[^\n]*\n		{V3Read::ppline(yytext);}
 }
 
   /************************************************************************/
@@ -653,42 +651,65 @@ escid	\\[^ \t\f\r\n]+
 <STRING>\\.	 	{ yymore(); }
 <STRING>\" 		{ yy_pop_state();
 			  yylval.strp = V3Read::newString(yytext+1,yyleng-2);
-			  return ySTRING; }
+			  return yaSTRING; }
 
   /************************************************************************/
+  /* Attributes */
+<ATTRMODE>\n		{ yymore(); NEXTLINE(); }
+<ATTRMODE>"*)"		{ yy_pop_state(); } 
+<ATTRMODE>. 		{ yymore(); }
+<ATTRMODE><<EOF>>	{ yyerror("EOF in (*");
+			  yyleng = 0; }
+
+  /************************************************************************/
+  /* Attributes */
+<V95,V01,V05,S05>{
+    "(*" 		{ yymore(); yy_push_state(ATTRMODE); }
+}
+
+  /************************************************************************/
+  /* Preprocessor*/
   /* Common for all SYSC header states */
   /* OPTIMIZE: we return one per line, make it one for the entire block */
 <V95,V01,V05,S05,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
-  [ \t]*"`verilog"			{ BEGIN V3Read::lastVerilogState(); }
-  [ \t]*"`psl"				{ if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
-  [ \t]*"`systemc_header"		{ BEGIN SYSCHDR; }
-  [ \t]*"`systemc_ctor"			{ BEGIN SYSCCTOR; }
-  [ \t]*"`systemc_dtor"			{ BEGIN SYSCDTOR; }
-  [ \t]*"`systemc_interface"		{ BEGIN SYSCINT; }
-  [ \t]*"`systemc_implementation"	{ BEGIN SYSCIMP; }
-  [ \t]*"`systemc_imp_header"		{ BEGIN SYSCIMPH; }
+  "`celldefine"				{ V3Read::inCellDefine(true); }
+  "`endcelldefine"			{ V3Read::inCellDefine(false); }
+  "`endprotect"				{ }
+  "`inline"				{ }
+  "`line"{ws}+[^\n]*\n			{ V3Read::ppline(yytext); }
+  "`portcoerce"				{ }
+  "`protect"				{ }
+  "`psl"				{ if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
+  "`resetall"				{ }
+  "`systemc_ctor"			{ BEGIN SYSCCTOR; }
+  "`systemc_dtor"			{ BEGIN SYSCDTOR; }
+  "`systemc_header"			{ BEGIN SYSCHDR; }
+  "`systemc_imp_header"			{ BEGIN SYSCIMPH; }
+  "`systemc_implementation"		{ BEGIN SYSCIMP; }
+  "`systemc_interface"			{ BEGIN SYSCINT; }
+  "`timescale"{ws}+[^\n]*		{}
+  "`verilog"				{ BEGIN V3Read::lastVerilogState(); }
 
-  [ \t]*"`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2001\"		{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\"	{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
-  [ \t]*"`begin_keywords"[ \t]*\"1364-2005\"		{ yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);}
-  [ \t]*"`begin_keywords"[ \t]*\"1800-2005\"		{ yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);}
-  [ \t]*"`end_keywords"					{ yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
-
-  "`line"[ \t][^\n]*\n			{V3Read::ppline(yytext);}
+  "`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2001\"		{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2001-noconfig\"	{ yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1364-2005\"		{ yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);}
+  "`begin_keywords"[ \t]*\"1800-2005\"		{ yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);}
+  "`end_keywords"					{ yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
 }
 
-<SYSCHDR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCHDR;}
-<SYSCINT>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCINT;}
-<SYSCIMP>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCIMP;}
-<SYSCIMPH>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCIMPH;}
-<SYSCCTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCCTOR;}
-<SYSCDTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return ySCDTOR;}
+<SYSCHDR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR;}
+<SYSCINT>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCINT;}
+<SYSCIMP>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMP;}
+<SYSCIMPH>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMPH;}
+<SYSCCTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCCTOR;}
+<SYSCDTOR>[ \t]*[^` \t\n][^\n]*\n	{ NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCDTOR;}
 <IGNORE>[ \t]*[^` \t\n][^\n]*\n		{ NEXTLINE(); }
 
   /* Pick up text-type data */
 <SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
-  [ \t]*\n		{ NEXTLINE(); yymore();}
+  {wsnr}*		{ yymore();}
+  \n			{ NEXTLINE(); yymore();}
   \r			;
 }
 
@@ -697,9 +718,7 @@ escid	\\[^ \t\f\r\n]+
 
 <V95,V01,V05,S05,PSL>{
   "`"[a-zA-Z_0-9]+	{ yyerrorf("Define or directive not defined: %s",yytext); }
-
   "//"[^\n]+		{ }  /* throw away single line comments */
-
   .			{yylval.fileline = CRELINE(); return yytext[0];}	/* return single char ops. */
 }
 

test_regress/driver.pl

@@ -32,8 +32,8 @@ use vars qw ($Debug %Vars $Driver $Fork);
 
 $::Driver = 1;
 
-eval "use Parallel::Forker; \$Fork=Parallel::Forker->new();";
-$Fork = Forker->new() if !$Fork;
+eval "use Parallel::Forker; \$Fork=Parallel::Forker->new(use_sig_child=>1);";
+$Fork = Forker->new(use_sig_child=>1) if !$Fork;
 $SIG{CHLD} = sub { $Fork->sig_child() if $Fork; };
 $SIG{TERM} = sub { $Fork->kill_tree_all('TERM') if $Fork; die "Quitting...\n"; };
 

test_regress/t/t_case_wild.v

@@ -60,6 +60,9 @@ module sub (/*AUTOARG*/
    output reg [4:0]  out2;
 
    always @* begin
+      // Test empty cases
+      casez (in[0])
+      endcase
       casez (in)
 	24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
 	24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};

test_regress/t/t_func.v

@@ -16,6 +16,7 @@ module t;
       if (add(add(3'd1)) != 3'd3) $stop;
       if (global != 4) $stop;
       if (munge4(4'b0010) != 4'b1011) $stop;
+      if (toint(2) != 3) $stop;
       if (global != 5) $stop;
       setit;
       incr(global,global,32'h10);
@@ -104,4 +105,9 @@ module t;
       nil_func = fa + fb;
    endfunction
 
+   function integer toint;
+      input integer fa;
+      toint = fa + 32'h1;
+   endfunction
+
 endmodule

test_regress/t/t_inst_v2k.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -24,6 +24,8 @@ module t (/*AUTOARG*/
 
    wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
 
+   hello hsub;
+
    t_inst_v2k_sub sub
      (
       // Outputs
@@ -55,6 +57,10 @@ module t (/*AUTOARG*/
 
 endmodule
 
+module hello;
+   initial $write ("Hello\n");
+endmodule
+
 // Local Variables:
 // compile-command: "./vlint __FILE__"
 // End: