Add --top-module option to select between multiple tops. [Stefan Thiede]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1010 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix no-module include files on command line.  [Stefan Thiede]
 
+***  Add --top-module option to select between multiple tops. [Stefan Thiede]
+
 * Verilator 3.660 2008/03/23
 
 ***  Add support for hard-coding VERILATOR_ROOT etc in the executables,

bin/verilator

@@ -217,6 +217,7 @@ descriptions in the next sections for more information.
     --sc                        Create SystemC output
     --sp                        Create SystemPerl output
     --stats                     Create statistics file
+    --top-module <topname>	Name of top level input module
     --trace                     Enable waveform creation
     --trace-depth <levels>      Depth of tracing
     -U<var>                     Undefine preprocessor define
@@ -451,8 +452,9 @@ the backward-compatible default of sc_bv's.
 
 =item --prefix I<topname>
 
-Specifies the name of the top level class.  Defaults to the name of the first
-Verilog file passed on the command line.
+Specifies the name of the top level class and makefile.  Defaults to V
+prepended to the name of the --top-module switch, or V prepended to the
+first Verilog filename passed on the command line.
 
 =item --profile-cfuncs
 
@@ -498,6 +500,13 @@ Specifies SystemPerl output mode; see also --cc and -sc.
 
 Creates a dump file with statistics on the design in {prefix}__stats.txt.
 
+=item --top-module I<topname>
+
+When the input Verilog contains more than one top level module, specifies
+the name of the top level Verilog module to become the top, and sets the
+default for if --prefix is not used.  This is not needed with standard
+designs with only one top.
+
 =item --trace
 
 Adds waveform tracing code to the model, this will create additional

src/V3LinkLevel.cpp

@@ -85,6 +85,21 @@ void V3LinkLevel::modSortByLevel() {
     // Sort modules by levels, root down to lowest children
     // Calculate levels again in case we added modules
     UINFO(2,"modSortByLevel()\n");
+
+    if (v3Global.opt.topModule()!="") {
+	bool hit = false;
+	for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
+	    if (nodep->name() == v3Global.opt.topModule()) {
+		hit = true;
+	    } else {
+		nodep->level(3);
+	    }
+	}
+	if (!hit) {
+	    v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' was not found in design.");
+	}
+    }
+
     LinkLevelVisitor visitor;
     visitor.main(v3Global.rootp());
 
@@ -92,8 +107,11 @@ void V3LinkLevel::modSortByLevel() {
     AstModule* topp = NULL;
     for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
 	if (nodep->level()<=2) {
-	    if (topp) nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: "
-				    <<nodep->prettyName()<<" and "<<topp->prettyName());
+	    if (topp) {
+		nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: "
+			      <<nodep->prettyName()<<" and "<<topp->prettyName());
+		nodep->v3warn(MULTITOP, "Fix, or use --top-module option to select which you want.");
+	    }
 	    topp = nodep;
 	}
 	vec.push_back(nodep);

src/V3Options.cpp

@@ -429,6 +429,7 @@ void V3Options::parseOpts (FileLine* fl, int argc, char** argv) {
     }
 
     // Default prefix to the filename
+    if (prefix()=="") m_prefix = string("V")+topModule();
     if (prefix()=="") m_prefix = string("V")+filenameNonExt(*(vFiles().begin()));
     if (modPrefix()=="") m_modPrefix = prefix();
 
@@ -654,6 +655,9 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift; m_prefix = argv[i];
 		if (m_modPrefix=="") m_modPrefix = m_prefix;
 	    }
+	    else if ( !strcmp (sw, "-top-module") && (i+1)<argc ) {
+		shift; m_topModule = argv[i];
+	    }
 	    else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
 		shift;
 		if (!strcmp (argv[i], "0")) { m_xAssign="0"; }

src/V3Options.h

@@ -88,6 +88,7 @@ class V3Options {
     string	m_prefix;	// main switch: --prefix
     string	m_modPrefix;	// main switch: --mod-prefix
     string	m_xAssign;	// main switch: --x-assign
+    string	m_topModule;	// main switch: --top-module
 
     // MEMBERS (optimizations)
     //				// main switch: -Op: --public
@@ -175,6 +176,7 @@ class V3Options {
     string makeDir() const { return m_makeDir; }
     string prefix() const { return m_prefix; }
     string modPrefix() const { return m_modPrefix; }
+    string topModule() const { return m_topModule; }
     string xAssign() const { return m_xAssign; }
     const V3StringSet& cppFiles() const { return m_cppFiles; }
     const V3StringSet& libraryFiles() const { return m_libraryFiles; }

test_regress/t/t_flag_topmodule.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--top-module b"],
+	 ) if $Last_Self->{v3};
+
+execute (
+	 check_finished=>1,
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_flag_topmodule.v

@@ -0,0 +1,32 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module a;
+   c c ();
+   initial begin
+      $write("Bad top modules\n");
+      $stop;
+   end
+endmodule
+
+module b;
+   d d ();
+endmodule
+
+module c;
+   initial begin
+      $write("Bad top modules\n");
+      $stop;
+   end
+endmodule
+
+module d;
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+

test_regress/t/t_flag_topmodule_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_flag_topmodule.v");
+
+compile (
+	 fails=>$Last_Self->{v3},
+	 nc=>0,  # Need to get it not to give the prompt
+	 expect=>
+'%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Unsupported: Multiple top level modules: .*
+%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Fix, or use --top-module option to select which you want.
+%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_flag_topmodule_bad2.pl

@@ -3,18 +3,20 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 
+top_filename("t/t_flag_topmodule.v");
+
 compile (
 	 fails=>$Last_Self->{v3},
+	 v_flags2 => ["--top-module notfound"],
 	 nc=>0,  # Need to get it not to give the prompt
 	 expect=>
-'%Error-MULTITOP: t/t_mod_bad_twotop.v:\d+: Unsupported: Multiple top level modules: t2 and t
+'%Error: Specified --top-module \'notfound\' was not found in design.
 %Error: Exiting due to.*',
-	 );
+	 ) if $Last_Self->{v3};
 
 ok(1);
 1;
-

test_regress/t/t_mod_bad_twotop.v

@@ -1,19 +0,0 @@
-// $Id:$
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
-
-module t;
-   initial begin
-      $write("Two top modules\n");
-      $stop;
-   end
-endmodule
-
-module t2;
-   initial begin
-      $write("Two top modules\n");
-      $stop;
-   end
-endmodule