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Fix ranges on gate primitive instantiations 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1038 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2008-04-25 11:48:18 +00:00
parent 0110f0193e
commit 506c36beed
4 changed files with 17 additions and 10 deletions
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2
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@ -25,6 +25,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix internal error when params get non-constants. [Johan Wouters]
**** Fix ranges on gate primitive instantiations. [Stefan Thiede]
* Verilator 3.661 2008/04/04
*** The --enable-defenv configure option added in 3.660 is now the default.

2
bin/verilator
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@ -1550,7 +1550,7 @@ them with a $write with the appropriate format specifier.
=item $finish, $stop
The rarely used optional exit code to finish and stop is ignored.
The rarely used optional parameter to $finish and $stop is ignored.
=item $fopen, $fclose, $fdisplay, $fwrite

16
src/verilog.y
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@ -1161,21 +1161,21 @@ gateXnorList: gateXnor { $$ = $1; }
| gateXnor ',' gateXnor { $$ = $1->addNext($3); }
;
gateBuf: gateIdE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
gateBuf: gateIdE instRangeE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
;
gateNot: gateIdE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
gateNot: gateIdE instRangeE '(' varRefDotBit ',' expr ')' { $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
;
gateAnd: gateIdE '(' varRefDotBit ',' gateAndPinList ')' { $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
gateAnd: gateIdE instRangeE '(' varRefDotBit ',' gateAndPinList ')' { $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
;
gateNand: gateIdE '(' varRefDotBit ',' gateAndPinList ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
gateNand: gateIdE instRangeE '(' varRefDotBit ',' gateAndPinList ')' { $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
;
gateOr: gateIdE '(' varRefDotBit ',' gateOrPinList ')' { $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
gateOr: gateIdE instRangeE '(' varRefDotBit ',' gateOrPinList ')' { $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
;
gateNor: gateIdE '(' varRefDotBit ',' gateOrPinList ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
gateNor: gateIdE instRangeE '(' varRefDotBit ',' gateOrPinList ')' { $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
;
gateXor: gateIdE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW ($2,$3,$5); $$->allowImplicit(true); }
gateXor: gateIdE instRangeE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW ($3,$4,$6); $$->allowImplicit(true); }
;
gateXnor: gateIdE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW ($2,$3,new AstNot($4,$5)); $$->allowImplicit(true); }
gateXnor: gateIdE instRangeE '(' varRefDotBit ',' gateXorPinList ')' { $$ = new AstAssignW ($3,$4,new AstNot($5,$6)); $$->allowImplicit(true); }
;
gateIdE: /*empty*/ {}

7
test_regress/t/t_gate_basic.v
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@ -21,13 +21,17 @@ module t (/*AUTOARG*/
// verilator lint_off IMPLICIT
not NT0 (nt0, a[0]);
and #1 AN0 (an0, a[0], b[0]);
nand #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
or OR0 (or0, a[0], b[0]);
nor NR0 (nr0, a[0], b[0], b[2]);
xor (xo0, a[0], b[0]);
xnor (xn0, a[0], b[0], b[2]);
// verilator lint_on IMPLICIT
parameter BITS=32;
wire [BITS-1:0] ba;
buf BARRAY [BITS-1:0] (ba, a);
`ifdef verilator
specify
specparam CDS_LIBNAME = "foobar";
@ -65,6 +69,7 @@ module t (/*AUTOARG*/
if (nr0 !== 1'b1) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b1) $stop;
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (bf[0] !== 1'b1) $stop;